Patent application number | Description | Published |
20090296511 | MICROPROCESSOR WITH PROGRAM-ACCESSIBLE RE-WRITABLE NON-VOLATILE STATE EMBODIED IN BLOWABLE FUSES OF THE MICROPROCESSOR - A microprocessor includes re-writeable non-volatile state (RNS) addressable by an instruction executed by the microprocessor that instructs the microprocessor to write a new value to the RNS. A plurality of fuses are each readable to determine whether the fuse is blown or unblown, in response to the microprocessor decoding the instruction. A Boolean logic unit performs Boolean operations on the values read from the plurality of fuses to determine a current RNS value. A fuse blowing device blows at least one unblown fuse to change the current RNS value to the new value when the new value is different than the current value. The microprocessor can read the plurality of fuses, perform the Boolean operations, and blow at least one unblown fuse to change the current value of the RNS to a new value multiple times in response to a program running on the microprocessor executing the instruction multiple times. | 12-03-2009 |
20110035622 | DETECTION AND CORRECTION OF FUSE RE-GROWTH IN A MICROPROCESSOR - A microprocessor includes a first plurality of fuses selectively blown with control values, a second plurality of fuses selectively blown collectively with an error correction value computed from the control values, control hardware that receives the control values and provides them to circuits of the microprocessor for controlling operation thereof. A state machine, serially coupled to the control hardware and to the fuses, serially scans the control values from the first fuses to the control hardware and serially scans the control values and the error correction value to a first register. The microprocessor reads the control values and error correction value from the first register, detects and corrects an error in the control values using the error correction value, writes the corrected control values to a second register, and causes the state machine to serially scan the corrected control values from the second register to the control hardware. | 02-10-2011 |
20110316583 | APPARATUS AND METHOD FOR OVERRIDE ACCESS TO A SECURED PROGRAMMABLE FUSE ARRAY - An apparatus in an integrated circuit for re-enabling the use of precluded extended JTAG operations. The apparatus includes a JTAG control chain, a feature fuse, a machine specific register, and an access controller. The JTAG control chain is configured to enable/disable the extended JTAG operations. The feature fuse is configured to indicate whether the extended JTAG features are to be disabled. The machine specific register is configured to store a value therein. The access controller is coupled to the feature fuse, the machine specific register, and the JTAG control chain, and is configured to determine that the feature fuse is blown, and is configured to direct the JTAG control chain to enable the precluded extended JTAG operations if the value matches an override value within the access controller during a period that the value is stored within the machine specific register. | 12-29-2011 |
20110316613 | MICROPROCESSOR APPARATUS AND METHOD FOR SECURING A PROGRAMMABLE FUSE ARRAY - An apparatus in an integrated circuit for precluding the use of extended JTAG operations. The apparatus has a JTAG control chain, a feature fuse, and an access controller. The JTAG control chain is configured to enable/disable the extended JTAG operations. The feature fuse is configured to indicate whether the extended JTAG features are to be disabled. The access controller is coupled to the feature fuse and the JTAG control chain. The access controller determines if the feature fuse is blown, and directs the JTAG control chain to disable the extended JTAG operations. | 12-29-2011 |
20110316614 | APPARATUS AND METHOD FOR TAMPER PROTECTION OF A MICROPROCESSOR FUSE ARRAY - An apparatus in an integrated circuit for precluding the use of extended JTAG operations. The apparatus has a JTAG control chain, a feature fuse, a level sensor, and an access controller. The JTAG control chain is configured to enable/disable the extended JTAG operations. The feature fuse is configured to indicate whether the extended JTAG features are to be disabled. The level sensor is configured to monitor an external voltage signal, and configured to indicate that the external voltage signal is at an illegal level. The access controller is coupled to the feature fuse, the level sensor, and the JTAG control chain, and is configured to determine if the feature fuse is blown, and is configured to direct the JTAG control chain to disable the extended JTAG operations if the external voltage signal is at an illegal level regardless of whether the feature fuse is blown. | 12-29-2011 |
20150054543 | APPARATUS AND METHOD FOR RAPID FUSE BANK ACCESS IN A MULTI-CORE PROCESSOR - An apparatus includes a fuse array, a random access memory (RAM), and a plurality of cores. The fuse array is disposed on a die, where the fuse array has a plurality of semiconductor fuses programmed with compressed configuration data. The RAM is disposed separately on the die. The plurality of cores is disposed separately on the die, where each of the plurality of cores is coupled to the fuse array and the RAM, and where the each of the plurality of cores accesses either the fuse array or the RAM upon power-up/reset as indicated by contents of a load data register to obtain the compressed configuration data. | 02-26-2015 |
20150055395 | EXTENDED FUSE REPROGRAMMABILITY MECHANISM - An apparatus includes a semiconductor fuse array, disposed on a die, into which is programmed configuration data. The semiconductor fuse array has a first plurality of semiconductor fuses and a second plurality of semiconductor fuses. The first plurality of semiconductor fuses is configured to store the configuration data in an encoded and compressed format. The second plurality of semiconductor fuses is configured to store first fuse correction data that indicates locations and values corresponding to a first one or more fuses within the first plurality of fuses whose states are to be changed from that which was previously stored. | 02-26-2015 |
20150055427 | MULTI-CORE MICROPROCESSOR CONFIGURATION DATA COMPRESSION AND DECOMPRESSION SYSTEM - An apparatus has a fuse array, a device programmer, and a plurality of cores. The fuse array is disposed on a die, where the fuse array comprises a plurality of semiconductor fuses. The device programmer is coupled to the fuse array and is configured to access the configuration data, to compress the configuration data to yield compressed configuration data, and to program the fuse array with the compressed configuration data. The plurality of cores is disposed separately on the die and is coupled to the fuse array, where each of the plurality of cores accesses and decompresses all of the compressed configuration data upon power-up/reset, for initialization of elements within the each of the plurality of cores. | 02-26-2015 |
20150055428 | MICROPROCESSOR MECHANISM FOR DECOMPRESSION OF CACHE CORRECTION DATA - An apparatus has a fuse array, a cache memory, and cores. The fuse array is disposed on a die, into which is programmed the configuration data. The fuse array includes a first plurality of fuses and a second plurality of fuses. The first plurality of fuses stores compressed cache correction data. The second plurality of fuses stores compressed fuse correction data that indicates locations and values corresponding to one or more fuses within the first plurality of fuses whose states are to be changed from that which was previously stored. The cores are disposed on the die, where each of the cores accesses the fuse array upon power-up/reset. The each of the cores includes a cache fuses decompressor that changes the states according to the locations and the values, decompresses the compressed cache correction data, and distributes decompressed cached correction data to initialize the cache memory. | 02-26-2015 |
20150055429 | APPARATUS AND METHOD FOR COMPRESSION AND DECOMPRESSION OF MICROPROCESSOR CONFIGURATION DATA - An apparatus is contemplated for storing and providing configuration data to a microprocessor. The apparatus has a core, disposed on a die, and a fuse array, disposed on the die and coupled to the core, where the fuse array comprises a plurality of semiconductor fuses programmed with compressed configuration data for the core, where the compressed configuration data is generated by compression of data within a virtual fuse array that corresponds to the core, and where the core accesses and decompresses the compressed configuration data upon power-up/reset, for initialization of elements within the core. | 02-26-2015 |
20150058563 | MULTI-CORE FUSE DECOMPRESSION MECHANISM - An apparatus is contemplated for storing and decompressing configuration data in a multi-core microprocessor. The apparatus includes a shared fuse array and a plurality of microprocessor cores. The shared fuse array is disposed on a die and comprises a plurality of semiconductor fuses programmed with compressed configuration data. The plurality of microprocessor cores is also disposed on the die, where each of the plurality of microprocessor cores is coupled to the shared fuse array and is configured to access all of the compressed configuration data during power-up/reset, for initialization of elements within the each of the plurality of cores. The each of the plurality of cores have a reset controller that is configured to decompress the all of the compressed configuration data, and to distribute decompressed configuration data to initialize the elements. | 02-26-2015 |
20150058564 | APPARATUS AND METHOD FOR EXTENDED CACHE CORRECTION - An apparatus includes a semiconductor fuse array, a cache memory, and a plurality of cores. The semiconductor fuse array is disposed on a die, into which is programmed the configuration data. The semiconductor fuse array has a first plurality of semiconductor fuses that is configured to store compressed cache correction data. The a cache memory is disposed on the die. The plurality of cores is disposed on the die, where each of the plurality of cores is coupled to the semiconductor fuse array and the cache memory, and is configured to access the semiconductor fuse array upon power-up/reset, to decompress the compressed cache correction data, and to distribute decompressed cached correction data to initialize the cache memory. | 02-26-2015 |
20150058565 | APPARATUS AND METHOD FOR COMPRESSION OF CONFIGURATION DATA - An apparatus includes a device programmer, coupled to a plurality of semiconductor fuses disposed on a die, configured to program the plurality of semiconductor fuses with compressed configuration data for a plurality of cores disposed separately on the die. The device programmer has a virtual fuse array and a compressor. The virtual fuse array is configured to store the configuration data for the plurality of cores. The configuration data includes a plurality of data types. The compressor is coupled to the virtual fuse array and is configured to read the virtual fuse array, and is configured to compress the configuration data by employing a plurality of compression algorithms to generate the compressed configuration data, where the plurality of compression algorithms correspond to the plurality of data types. | 02-26-2015 |
20150058598 | APPARATUS AND METHOD FOR CONFIGURABLE REDUNDANT FUSE BANKS - An apparatus is contemplated for storing and providing configuration data to an integrated circuit device, the apparatus has a fuse array and a plurality of cores. The fuse array is disposed on a die. The fuse array has a first plurality of semiconductor fuses and a second plurality of semiconductor fuses. The plurality of cores is disposed on the die, where each of the plurality of cores is coupled to the fuse array. The each of the plurality of cores includes array control, configured to access the first and second pluralities of fuses, and configured to process first states of the first plurality of semiconductor fuses and second states of the second plurality of semiconductor fuses according to contents of a configuration data register. | 02-26-2015 |
20150058609 | APPARATUS AND METHOD FOR STORAGE AND DECOMPRESSION OF CONFIGURATION DATA - An apparatus includes a plurality of cores and a fuse array. The plurality of cores is disposed on a die. The fuse array is disposed on the die and is coupled to each of the plurality of cores, where the fuse array includes a plurality of semiconductor fuses that are programmed with compressed configuration data for the each of the plurality of cores, and where the each of the plurality of cores accesses and decompresses all of the compressed configuration data upon power-up/reset, for initialization of elements within the each of the plurality of cores. | 02-26-2015 |
20150058610 | CORE-SPECIFIC FUSE MECHANISM FOR A MULTI-CORE DIE - An apparatus including a plurality of cores and a fuse array. The plurality of cores is disposed on a die. The fuse array is disposed on the die and is coupled to each of the plurality of cores, where the fuse array includes a first plurality of semiconductor fuses and a second plurality of semiconductor fuses. The first plurality of semiconductor fuses is programmed with compressed configuration data for the each of the plurality of cores. The second plurality of semiconductor fuses is programmed with core designation data that associates some of the compressed configuration data with one of the plurality of cores, where the one of the plurality of cores accesses and decompresses the some of the compressed configuration data upon power-up/reset, for initialization of elements within the one of the plurality of cores. | 02-26-2015 |
20150058695 | CORRECTABLE CONFIGURATION DATA COMPRESSION AND DECOMPRESSION SYSTEM - An apparatus has a shared fuse array and a plurality of microprocessor cores. The shared fuse array is disposed on a die, the shared fuse array having a plurality of semiconductor fuses programmed with compressed configuration data and error checking and correction (ECC) codes. The plurality of microprocessor cores is disposed on the die, where each of the plurality of microprocessor cores is coupled to the shared fuse array and is configured to access all of the compressed configuration data during power-up/reset, for initialization of elements within the each of the plurality of cores. The each of the plurality of cores includes a reset controller that is configured to access the compressed configuration data and the ECC codes, to correct errors resulting in corrected compressed configuration data, to decompress all of the corrected compressed configuration data, and to distribute decompressed configuration data to initialize the elements. | 02-26-2015 |