Patent application number | Description | Published |
20080201511 | Device Identification Coding of Inter-Integrated Circuit Slave Devices - Consistent with one example embodiment, communications systems, using a serial data transfer bus having a serial data line and a clock line used to implement a communications protocol, incorporate identification of inter-integrated circuit slave devices using device identification coding. The communications system includes a slave device having a device identification code identifying one or more parameters. Communications circuitry in the slave device is configured to communicate with a master device on the I2C serial data transfer bus using the communications protocol. In response to a transmission of a device identification address from the master device, the slave device is configured to transmit an ACKNOWLEDGE, and in response to a transmission of a slave device address and the device identification address from the master device, the slave device is configured to transmit the device identification code from the slave device to the master. | 08-21-2008 |
20080215779 | Slave Device with Latched Request for Service - Consistent with one example embodiment, communications systems ( | 09-04-2008 |
20080215780 | Simultaneous Control Of Multiple I/O Banks In An 12C Slave Device - Consistent with one example embodiment, communications systems, using a serial data transfer bus having a serial data line and a clock line used to implement a communications protocol, incorporate programmable loading of a logic value into parallel slave device registers. The communications system includes a slave device having two or more registers, each register having two or more bits, each register configured to load data therein received in accordance with the communications protocol over the data transfer bus in a first configuration, and to load a single logic value into the plurality of bits in a second configuration. A programmable configuration register is configured to be programmed, in accordance with the communications protocol over the data transfer bus, to select two or more of the registers for loading of the single logic value into the two or more of bits of the selected registers in the second configuration. | 09-04-2008 |
20080258766 | Mixed Signal Integrated Circuit - This invention relates to mixed signal integrated circuits, that is, integrated circuits comprising both analogue and digital circuitry. More particularly, it concerns reduction of noise in such a device. When a digital circuit is included in the same integrated circuit device as an analogue circuit, the digital circuit may be an additional source of a considerable amount of noise. This results in cross-talk, electrical interference and signal distortion imposed on the analogue signals. The invention provides an integrated circuit comprising analogue circuitry ( | 10-23-2008 |
20100205326 | PROGRAMMING PARALLEL I2C SLAVE DEVICES FROM A SINGLE I2C DATA STREAM - Consistent with one example embodiment, communications systems, using a serial data transfer bus having a serial data line and a clock line used to implement a communications protocol, incorporate programming of parallel slave devices concurrently using an I | 08-12-2010 |
20100217903 | SIMULTANEOUS CONTROL OF MULTIPLE I/O BANKS IN AN I2C SLAVE DEVICE - Consistent with one example embodiment, communications systems ( | 08-26-2010 |
20100223486 | METHOD AND SYSTEM FOR I2C CLOCK GENERATION | 09-02-2010 |
20110187425 | PHASE-LOCKED LOOP SYSTEMS USING ADAPTIVE LOW-PASS FILTERS IN SWITCHED BANDWIDTH FEEDBACK LOOPS - Methods and systems directed toward a PLL circuit ( | 08-04-2011 |
Patent application number | Description | Published |
20080237364 | Flux air cap and spray nozzle designs - Methods and apparatus to improve flux air cap and/or spray nozzle designs are described. In one embodiment, a flux nozzle may include a cylindrical portion and a conical portion. Other embodiments are also described. | 10-02-2008 |
20120266972 | ROTATIONAL-FLOW SPRAY NOZZLE AND PROCESS OF USING SAME - A solder-flux composition is sprayed onto a substrate by rotating the solder-flux composition inside a spray cap, and before the solder-flux liquid exits the spray cap, perturbing the flow thereof with a fluid. | 10-25-2012 |
20140357020 | METHODS FOR HIGH PRECISION MICROELECTRONIC DIE INTEGRATION - The subject matter of the present description relates to methods for the precise integration of microelectronic dice within a multichip package which substantially reduce or eliminate any misalign caused by the movement of the microelectronic dice during the integration process. These methods may include the use of a temporary adhesive in conjunction with a carrier having at least one recess for microelectronic die alignment, the use of a precision molded carrier for microelectronic die alignment, the use of magnetic alignment of microelectronic dice on a reusable carrier, and/or the use of a temporary adhesive with molding processes on a reusable carrier. | 12-04-2014 |
20150179622 | SOLDER PAD DEVICE AND METHOD - An electronic device including a solder pad structure and methods of forming an electrical interconnection are shown. Solder pads including one or more projections extending from the pads are shown where the projections occupy only a fraction of a surface area of the pads. Processes such as thermal compression bonding using solder pads as described area also shown. | 06-25-2015 |
20150187681 | FLEXIBLE MICROELECTRONIC ASSEMBLY AND METHOD - This disclosure relates generally to a system and method including a substrate and an electronic component. The substrate includes a circuit board including a hole, a routing layer, and a first interconnect portion positioned, at least in part, within the hole. The electronic component includes a second interconnect portion, coupled to the first interconnect portion, forming an interconnect between the electronic component and the routing layer. | 07-02-2015 |
20150262968 | METHODS FOR HIGH PRECISION MICROELECTRONIC DIE INTEGRATION - The subject matter of the present description relates to methods for the precise integration of microelectronic dice within a multichip package which substantially reduce or eliminate any misalign caused by the movement of the microelectronic dice during the integration process. These methods may include the use of a temporary adhesive in conjunction with a carrier having at least one recess for microelectronic die alignment, the use of a precision molded carrier for microelectronic die alignment, the use of magnetic alignment of microelectronic dice on a reusable carrier, and/or the use of a temporary adhesive with molding processes on a reusable carrier. | 09-17-2015 |
Patent application number | Description | Published |
20140091470 | DIE WARPAGE CONTROL FOR THIN DIE ASSEMBLY - Die warpage is controlled for the assembly of thin dies. In one example, a device having a substrate on a back side and components in front side layers is formed. A backside layer is formed over the substrate, the layer resisting warpage of the device when the device is heated. The device is attached to a substrate by heating. | 04-03-2014 |
20150163904 | HIGH DENSITY INTERCONNECTION OF MICROELECTRONIC DEVICES - A microelectronic package of the present description may comprises a first microelectronic device having at least one row of connection structures electrically connected thereto and a second microelectronic device having at least one row of connection structures electrically connected thereto, wherein the connection structures within the at least one first microelectronic device row are aligned with corresponding connection structures within the at least one second microelectronic device row in an x-direction. An interconnect comprising an interconnect substrate having a plurality of electrically isolated conductive traces extending in the x-direction on a first surface of the interconnect substrate may be attached to the at least one first microelectronic device connection structure row and the at least one second microelectronic device connection structure row, such that at least one interconnect conductive trace forms a connection between a first microelectronic device connection structure and its corresponding second microelectronic device connection structure. | 06-11-2015 |
20150237713 | ELECTRO-MAGNETIC INTERFERENCE (EMI) SHIELDING TECHNIQUES AND CONFIGURATIONS - Embodiments of the present disclosure are directed towards electro-magnetic interference (EMI) shielding techniques and configurations. In one embodiment, an apparatus includes a first substrate, a die having interconnect structures coupled with the first substrate to route input/output (I/O) signals between the die and the first substrate and a second substrate coupled with the first substrate, wherein the die is disposed between the first substrate and the second substrate and at least one of the first substrate and the second substrate include traces configured to provide electro-magnetic interference (EMI) shielding for the die. Other embodiments may be described and/or claimed. | 08-20-2015 |
Patent application number | Description | Published |
20140212993 | METHOD OF MANUFACTURING A MAGNETORESISTIVE DEVICE - A method of manufacturing a magnetoresistive-based device includes etching a hard mask layer, the etching having a selectivity greater than 2:1 and preferably less than 5:1 of the hard mask layer to a photo resist thereover. Optionally, the photo resist is trimmed prior to the etch, and oxygen may be applied during or just subsequent to the trim of the photo resist to increase side shrinkage. An additional step includes an oxygen treatment during the etch to remove polymer from the structure and etch chamber. | 07-31-2014 |
20140315329 | METHOD OF MANUFACTURING A MAGNETORESISTIVE-BASED DEVICE - A method of manufacturing a magnetoresistive-based device having magnetic material layers formed between a first electrically conductive layer and a second electrically conductive layer, the magnetic materials layers including a tunnel barrier layer formed between a first magnetic materials layer and a second magnetic materials layer, including removing the first electrically conductive layer and the first magnetic materials layer unprotected by a first hard mask, to form a first electrode and a first magnetic materials, respectively; and removing the tunnel barrier layer, second magnetic materials layer, and second electrically conductive layer unprotected by the second hard mask to form a tunnel barrier, second magnetic materials, and a second electrode. | 10-23-2014 |
20150102006 | ISOLATION OF MAGNETIC LAYERS DURING ETCH IN A MAGNETORESISTIVE DEVICE - Isolation of magnetic layers in the magnetoresistive stack is achieved by passivation of sidewalls of the magnetic layers or deposition of a thin film of non-magnetic dielectric material on the sidewalls prior to subsequent etching steps. Etching the magnetic layers using a non-reactive gas further prevents degradation of the sidewalls. | 04-16-2015 |
20150236248 | TOP ELECTRODE ETCH IN A MAGNETORESISTIVE DEVICE AND DEVICES MANUFACTURED USING SAME - A two-step etching process is used to form the top electrode for a magnetoresistive device. The level of isotropy is different for each of the two etching steps, thereby providing advantages associated with isotropic etching as well as more anisotropic etching. The level of isotropy is controlled by varying power and pressure during plasma etching operations. | 08-20-2015 |
20150236249 | NON-REACTIVE PHOTORESIST REMOVAL AND SPACER LAYER OPTIMIZATION IN A MAGNETORESISTIVE DEVICE - In forming a top electrode for a magnetoresistive device, photoresist used in patterning the electrode is stripped using a non-reactive stripping process. Such a non-reactive stripping process uses water vapor or some other non-oxidizing gas that also passivates exposed portions the magnetoresistive device. In such magnetoresistive devices, a non-reactive spacer layer is included that helps prevent diffusion between layers in the magnetoresistive device, where the non-reactive nature of the spacer layer prevents sidewall roughness that can interfere with accurate formation of the lower portions of the magnetoresistive device. | 08-20-2015 |
20150236250 | TOP ELECTRODE ETCH IN A MAGNETORESISTIVE DEVICE AND DEVICES MANUFACTURED USING SAME - A two-step etching process is used to form the top electrode for a magnetoresistive device. The etching chemistries are different for each of the two etching steps. The first chemistry used to etch the top portion of the electrode is more selective with respect to the conductive material of the top electrode, thereby reducing unwanted erosion of the photoresist and hard mask layers. The second chemistry is less corrosive than the first chemistry and does not damage the layers underlying the top electrode, such as those included in the magnetic tunnel junction. | 08-20-2015 |