Patent application number | Description | Published |
20120118383 | Autonomous Integrated Circuit - An autonomous integrated circuit (IC) includes a solar cell formed on a bottom substrate of a silicon-on-insulator (SOI) substrate as a handle substrate; an insulating layer of the SOI substrate located on top of the solar cell; and a device layer formed on a top semiconductor layer of the SOI substrate located on top of the insulating layer, wherein a top contact of the device layer is electrically connected to a bottom contact of the solar cell such that the solar cell is enabled to power the device layer. | 05-17-2012 |
20120205784 | GROWING COMPRESSIVELY STRAINED SILICON DIRECTLY ON SILICON AT LOW TEMPERATURES - Compressively strained silicon is epitaxially grown directly onto a silicon substrate at low temperature using hydrogen to engineer the strain level. Hydrogen dilution may be varied during such growth to provide a strain gradient. | 08-16-2012 |
20120210932 | LOW-TEMPERATURE SELECTIVE EPITAXIAL GROWTH OF SILICON FOR DEVICE INTEGRATION - An epitaxy method includes providing an exposed crystalline region of a substrate material. Silicon is epitaxially deposited on the substrate material in a low temperature process wherein a deposition temperature is less than 500 degrees Celsius. A source gas is diluted with a dilution gas with a gas ratio of dilution gas to source gas of less than 1000. | 08-23-2012 |
20120211079 | SILICON PHOTOVOLTAIC ELEMENT AND FABRICATION METHOD - A method of forming a photovoltaic device that includes providing an absorption layer of a first crystalline semiconductor material having a first conductivity type, and epitaxially growing a second crystalline semiconductor layer of a second conductivity type that is opposite the first conductivity type. The first conductivity type may be p-type and the second conductivity type may be n-type, or the first conductivity type may be n-type and the second conductivity type may be p-type. The temperature of the epitaxially growing the second crystalline semiconductor layer does not exceed 500° C. Contacts are formed in electrical communication with the absorption layer and the second crystalline semiconductor layer. | 08-23-2012 |
20120255600 | METHOD OF BONDING AND FORMATION OF BACK SURFACE FIELD (BSF) FOR MULTI-JUNCTION III-V SOLAR CELLS - A photovoltaic device including at least one top cell that include at least one semiconductor material; a bottom cell of a germanium containing material having a thickness of 10 microns or less; and a back surface field (BSF) region provided by a eutectic alloy layer of aluminum and germanium on the back surface of the bottom cell of that is opposite the interface between the bottom cell and at least one of the top cells. The eutectic alloy of aluminum and germanium bonds the bottom cell of the germanium-containing material to a supporting substrate. | 10-11-2012 |
20120285517 | SCHOTTKY BARRIER SOLAR CELLS WITH HIGH AND LOW WORK FUNCTION METAL CONTACTS - A Schottky Barrier solar cell having at least one of a low work function region and a high work function region provided on the front or back surface of a lightly-doped absorber material, which may be produced in a variety of different geometries. The method of producing the Schottky Barrier solar cells allows for short processing times and the use of low temperatures. | 11-15-2012 |
20120285518 | Solar cell with interdigitated back contacts formed from high and low work-function-tuned silicides of the same metal - A solar cell having n-type and p-type interdigitated back contacts (IBCs), which cover the entire back surface of the absorber layer. The spatial separation of the IBCs is in a direction perpendicular to the back surface, thus providing borderless contacts having a zero-footprint separation. As the contacts are on the back, photons incident on the cell's front surface can be absorbed without any shadowing. | 11-15-2012 |
20120312361 | EMITTER STRUCTURE AND FABRICATION METHOD FOR SILICON HETEROJUNCTION SOLAR CELL - A method of forming a photovoltaic device that includes providing an absorption layer of a first crystalline semiconductor material having a first conductivity type, epitaxially growing a second crystalline semiconductor layer of a second conductivity type that is opposite the first conductivity type, and growing a doped amorphous or nanocrystalline passivation layer of a second conductivity type that is opposite to the first conductivity type. The first conductivity type may be p-type and the second conductivity type may be n-type, or the first conductivity type may be n-type and the second conductivity type may be p-type. The temperature of the epitaxially growing the second crystalline semiconductor layer does not exceed 500° C. Contacts are formed in electrical communication with the absorption layer and the second crystalline semiconductor layer. | 12-13-2012 |
20120312362 | SILICON-CONTAINING HETEROJUNCTION PHOTOVOLTAIC ELEMENT AND DEVICE - A photovoltaic device is provided in which the tunneling barrier for hole collection at either the front contact or the back contact of a silicon heterojunction cell is reduced, without compromising the surface passivation either the front contact or at the back contact. This is achieved in the present disclosure by replacing the intrinsic and/or doped hydrogenated amorphous silicon (a-Si:H) layer(s) at the back contact or at the front contact with an intrinsic and/or doped layer(s) of a semiconductor material having a lower valence band-offset than that of a:Si—H with c-Si, and/or a higher activated doping concentration compared to that of doped hydrogenated amorphous Si. The higher level of activated doping is due to the higher doping efficiency of the back contact or front contact semiconductor material compared to that of amorphous Si, and/or modulation doping of the back or front contact semiconducting material. As a result, the tunneling barrier for hole collection is reduced and the cell efficiency is improved accordingly. | 12-13-2012 |
20120318334 | SPALLING METHODS TO FORM MULTI-JUNCTION PHOTOVOLTAIC STRUCTURE - A method cleaving a semiconductor material that includes providing a germanium substrate having a germanium and tin alloy layer is present therein. A stressor layer is deposited on a surface of the germanium substrate. A stress from the stressor layer is applied to the germanium substrate, in which the stress cleaves the germanium substrate to provide a cleaved surface. The cleaved surface of the germanium substrate is then selective to the germanium and tin alloy layer of the germanium substrate. In another embodiment, the germanium and tin alloy layer may function as a fracture plane during a spalling method. | 12-20-2012 |
20120322230 | METHOD FOR FORMING TWO DEVICE WAFERS FROM A SINGLE BASE SUBSTRATE UTILIZING A CONTROLLED SPALLING PROCESS - The present disclosure provides a method for forming two device wafers starting from a single base substrate. The method includes first providing a structure which includes a base substrate with device layers located on, or within, a topmost surface and a bottommost surface of the base substrate. The base substrate may have double side polished surfaces. The structure including the device layers is spalled in a region within the base substrate that is between the device layers. The spalling provides a first device wafer including a portion of the base substrate and one of the device layers, and a second device wafer including another portion of the base substrate and the other of the device layer. | 12-20-2012 |
20120329197 | METHOD OF BONDING AND FORMATION OF BACK SURFACE FIELD (BSF) FOR MULTI-JUNCTION III-V SOLAR CELLS - A photovoltaic device including at least one top cell that include at least one III-V semiconductor material; a bottom cell of a germanium containing material having a thickness of | 12-27-2012 |
20120329206 | SILICON-CONTAINING HETEROJUNCTION PHOTOVOLTAIC ELEMENT AND DEVICE - In one embodiment, a method of forming a photovoltaic device is provided which includes providing an absorption layer comprising a silicon-containing semiconductor layer of a first conductivity type and having a top surface and a bottom surface that opposes the top surface. A front contact is formed on the top surface of the absorption layer, and a back contact is formed on the bottom surface of the absorption layer. The forming of the front contact and the back contact can occur in any order. The back contact that is formed comprises at least one back contact semiconductor material layer of the first conductivity type and having a lower band-offset than that of hydrogenated amorphous silicon with crystalline Si and/or a higher activated doping of the first conductivity type than that of the doped hydrogenated amorphous silicon layer. | 12-27-2012 |
20130005116 | EDGE-EXCLUSION SPALLING METHOD FOR IMPROVING SUBSTRATE REUSABILITY - A method to minimize edge-related substrate breakage during spalling using an edge-exclusion region where the stressor layer is either non-present (excluded either during deposition or removed afterwards) or present but significantly non-adhered to the substrate surface in the exclusion region is provided. In one embodiment, the method includes forming an edge exclusion material on an upper surface and near an edge of a base substrate. A stressor layer is then formed on exposed portions of the upper surface of the base substrate and atop the edge exclusion material, A portion of the base substrate that is located beneath the stressor layer and which is not covered by the edge exclusion material is then spalled. | 01-03-2013 |
20130014811 | HETEROJUNCTION III-V SOLAR CELL PERFORMANCEAANM Bedell; Stephen W.AACI Wappingers FallsAAST NYAACO USAAGP Bedell; Stephen W. Wappingers Falls NY USAANM Hekmatshoartabari; BahmanAACI Mount KiscoAAST NYAACO USAAGP Hekmatshoartabari; Bahman Mount Kisco NY USAANM Sadana; Devendra K.AACI PleasantvilleAAST NYAACO USAAGP Sadana; Devendra K. Pleasantville NY USAANM Shahidi; Ghavam G.AACI Pound RidgeAAST NYAACO USAAGP Shahidi; Ghavam G. Pound Ridge NY USAANM Shahrjerdi; DavoodAACI OssiningAAST NYAACO USAAGP Shahrjerdi; Davood Ossining NY US | 01-17-2013 |
20130019944 | METHOD OF STABILIZING HYDROGENATED AMORPHOUS SILICON AND AMORPHOUS HYDROGENATED SILICON ALLOYS - A method of forming a semiconductor material of a photovoltaic device that includes providing a surface of a hydrogenated amorphous silicon containing material, and annealing the hydrogenated amorphous silicon containing material in a deuterium containing atmosphere. Deuterium from the deuterium-containing atmosphere is introduced to the lattice of the hydrogenated amorphous silicon containing material through the surface of the hydrogenated amorphous silicon containing material. In some embodiments, the deuterium that is introduced to the lattice of the hydrogenated amorphous silicon containing material increases the stability of the hydrogenated amorphous silicon containing material. | 01-24-2013 |
20130019945 | METHOD OF STABILIZING HYDROGENATED AMORPHOUS SILICON AND AMORPHOUS HYDROGENATED SILICON ALLOYS - A method of forming a semiconductor material of a photovoltaic device that includes providing a surface of a hydrogenated amorphous silicon containing material, and annealing the hydrogenated amorphous silicon containing material in a deuterium containing atmosphere. Deuterium from the deuterium-containing atmosphere is introduced to the lattice of the hydrogenated amorphous silicon containing material through the surface of the hydrogenated amorphous silicon containing material. In some embodiments, the deuterium that is introduced to the lattice of the hydrogenated amorphous silicon containing material increases the stability of the hydrogenated amorphous silicon containing material. | 01-24-2013 |
20130025653 | III-V PHOTOVOLTAIC ELEMENTS - Solar cell structures that have improved carrier collection efficiencies at a heterointerface are provided by low temperature epitaxial growth of silicon on a III-V base. Additionally, a solar cell structure having improved open circuit voltage includes a shallow junction III-V emitter formed by epitaxy or diffusion followed by the epitaxy of Si | 01-31-2013 |
20130025654 | MULTI-JUNCTION PHOTOVOLTAIC DEVICE AND FABRICATION METHOD - A method of forming a photovoltaic device that includes bonding a substrate to a germanium-containing semiconductor layer with a stressor layer, wherein the stressor layer cleaves the germanium-containing semiconductor layer. At least one semiconductor layer is formed on a cleaved surface of the germanium-containing semiconductor layer that is opposite the conductivity type of the germanium-containing semiconductor layer to provide a first solar cell. The first solar cell absorbs a first range of wavelengths. At least one second solar cell may be formed on the first solar cell, wherein the at least one second solar cell is composed of at least one semiconductor material to absorb a second range of wavelengths that is different than the first range wavelengths absorbed by the first solar cell. | 01-31-2013 |
20130025659 | MULTI-JUNCTION PHOTOVOLTAIC DEVICE AND FABRICATION METHOD - A method of forming a photovoltaic device that includes bonding a substrate to a germanium-containing semiconductor layer with a stressor layer, wherein the stressor layer cleaves the germanium-containing semiconductor layer. At least one semiconductor layer is formed on a cleaved surface of the germanium-containing semiconductor layer that is opposite the conductivity type of the germanium-containing semiconductor layer to provide a first solar cell. The first solar cell absorbs a first range of wavelengths. At least one second solar cell may be formed on the first solar cell, wherein the at least one second solar cell is composed of at least one semiconductor material to absorb a second range of wavelengths that is different than the first range wavelengths absorbed by the first solar cell. | 01-31-2013 |
20130082357 | PREFORMED TEXTURED SEMICONDUCTOR LAYER - A base layer of a semiconductor material is formed with a naturally textured surface. The base layer may be incorporated within a photovoltaic structure. A controlled spalling technique, in which substrate fracture is propagated in a selected direction to cause the formation of facets, is employed. Spalling in the [110] directions of a (001) silicon substrate results in the formation of such facets of the resulting base layer, providing a natural surface texture. | 04-04-2013 |
20130092218 | BACK-SURFACE FIELD STRUCTURES FOR MULTI-JUNCTION III-V PHOTOVOLTAIC DEVICES - A multi-junction III-V photovoltaic device is provided that includes at least one top cell comprised of at least one III-V compound semiconductor material; and a bottom cell in contact with a surface of the at least one top cell. The bottom cell includes a germanium-containing layer in contact with the at least one top cell, at least one intrinsic hydrogenated silicon-containing layer in contact with a surface of the germanium-containing layer, and at least one doped hydrogenated silicon-containing layer in contact with a surface of the at least one intrinsic hydrogenated silicon-containing layer. The intrinsic and doped silicon-containing layers can be amorphous, nano/micro-crystalline, poly-crystalline or single-crystalline. | 04-18-2013 |
20130095598 | BACK-SURFACE FIELD STRUCTURES FOR MULTI-JUNCTION III-V PHOTOVOLTAIC DEVICES - A multi-junction III-V photovoltaic device is provided that includes at least one top cell comprised of at least one III-V compound semiconductor material; and a bottom cell in contact with a surface of the at least one top cell. The bottom cell includes a germanium-containing layer in contact with the at least one top cell, at least one intrinsic hydrogenated silicon-containing layer in contact with a surface of the germanium-containing layer, and at least one doped hydrogenated silicon-containing layer in contact with a surface of the at least one intrinsic hydrogenated silicon-containing layer. The intrinsic and doped silicon-containing layers can be amorphous, nano/micro-crystalline, poly-crystalline or single-crystalline. | 04-18-2013 |
20130112275 | SILICON HETEROJUNCTION PHOTOVOLTAIC DEVICE WITH WIDE BAND GAP EMITTER - A photovoltaic device including a single junction solar cell provided by an absorption layer of a type IV semiconductor material having a first conductivity, and an emitter layer of a type III-V semiconductor material having a second conductivity, wherein the type III-V semiconductor material has a thickness that is no greater than 50 nm. | 05-09-2013 |
20130180564 | FIELD-EFFECT PHOTOVOLTAIC ELEMENTS - Photovoltaic devices such as solar cells having one or more field-effect hole or electron inversion/accumulation layers as contact regions are configured such that the electric field required for charge inversion and/or accumulation is provided by the output voltage of the photovoltaic device or that of an integrated solar cell unit. In some embodiments, a power source may be connected between a gate electrode and a contact region on the opposite side of photovoltaic device. In other embodiments, the photovoltaic device or integrated unit is self-powering. | 07-18-2013 |
20130193441 | Semiconductor Substrates Using Bandgap Material Between III-V Channel Material and Insulator Layer - Improved semiconductor substrates are provided that employ a wide bandgap material between the channel and the insulator. A semiconductor substrate comprises a channel layer comprised of a III-V material; an insulator layer; and a wide bandgap material between the channel layer and the insulator layer, wherein a conduction band offset (ΔE | 08-01-2013 |
20130193482 | Fin Structures with Damage-Free Sidewalls for Multi-Gate Mosfets - Improved Fin Field Effect Transistors (FinFET) are provided, as well as improved techniques for forming fins for a FinFET. A fin for a FinFET is formed by forming a semi-insulating layer on an insulator that gives a sufficiently large conduction band offset (ΔE | 08-01-2013 |
20130193483 | Mosfet Structures Having Compressively Strained Silicon Channel - MOSFET structures are provided having a compressively strained silicon channel. A semiconductor device is provided that comprises a field effect transistor (FET) structure having a gate stack on a silicon substrate, wherein the field effect transistor structure comprises a channel formed below the gate stack; and a compressively strained silicon layer on at least a portion of the silicon substrate to compressively strain the channel. | 08-01-2013 |
20130196486 | Semiconductor Substrates Using Bandgap Material Between III-V Channel Material and Insulator Layer - Improved semiconductor substrates are provided that employ a wide bandgap material between the channel and the insulator. A semiconductor substrate comprises a channel layer comprised of a III-V material; an insulator layer; and a wide bandgap material between the channel layer and the insulator layer, wherein a conduction band offset (ΔE) between the channel layer and the wide bandgap material is between 0.05 eV and 0.8 eV. The channel layer can be comprised of, for example, In | 08-01-2013 |
20130196488 | Fin Structures with Damage-Free Sidewalls for Multi-Gate Mosfets - Improved Fin Field Effect Transistors (FinFET) are provided, as well as improved techniques for forming fins for a FinFET. A fin for a FinFET is formed by forming a semi-insulating layer on an insulator that gives a sufficiently large conduction band offset (ΔE | 08-01-2013 |
20130244372 | SILICON PHOTOVOLTAIC ELEMENT AND FABRICATION METHOD - A method of forming a photovoltaic device that includes providing an absorption layer of a first crystalline semiconductor material having a first conductivity type, and epitaxially growing a second crystalline semiconductor layer of a second conductivity type that is opposite the first conductivity type. The first conductivity type may be p-type and the second conductivity type may be n-type, or the first conductivity type may be n-type and the second conductivity type may be p-type. The temperature of the epitaxially growing the second crystalline semiconductor layer does not exceed 500° C. Contacts are formed in electrical communication with the absorption layer and the second crystalline semiconductor layer. | 09-19-2013 |
20130307075 | CRYSTALLINE THIN-FILM TRANSISTORS AND METHODS OF FORMING SAME - Thin film transistors containing a gate structure on a crystalline semiconductor material including a crystalline active channel layer are provided. The gate structure of the present disclosure includes an insulator stack of, from bottom to top, a hydrogenated non-crystalline semiconductor material layer portion and a hydrogenated non-crystalline silicon nitride portion. Doped crystalline semiconductor source/drain regions are located on opposing sides of the gate structure and on surface portions of the crystalline semiconductor material. | 11-21-2013 |
20130313551 | HETEROJUNCTION BIPOLAR TRANSISTORS WITH INTRINSIC INTERLAYERS - Heterojunction bipolar transistors are provided that include at least one contact (e.g., collector, emitter, and/or base) formed by a heterojunction between a crystalline semiconductor material and a doped non-crystalline semiconductor material layer. An interfacial intrinsic non-crystalline semiconductor material layer is present at the heterojunction between the crystalline semiconductor material and the doped non-crystalline semiconductor material layer. The presence of the interfacial intrinsic non-crystalline semiconductor material layer improves the surface passivation of the crystalline semiconductor material by reducing the interface defect density at the heterojunction. | 11-28-2013 |
20130313552 | HETEROJUNCTION BIPOLAR TRANSISTORS WITH THIN EPITAXIAL CONTACTS - Heterojunction bipolar transistors are provided that include at least one contact (e.g., collector, and/or emitter, and/or base) formed by a heterojunction between a crystalline semiconductor material and a doped non-crystalline semiconductor material layer. A highly doped epitaxial semiconductor layer comprising a highly doped hydrogenated crystalline semiconductor material layer portion is present at the heterojunction between the crystalline semiconductor material and the doped non-crystalline semiconductor material layer. Minority carriers within the highly doped epitaxial semiconductor layer have a diffusion length that is larger than a thickness of the highly doped epitaxial semiconductor layer. | 11-28-2013 |
20130316520 | METHODS OF FORMING CONTACT REGIONS USING SACRIFICIAL LAYERS - Methods of patterning semiconductor contact materials on a crystalline semiconductor material which allow high-quality interfaces between the crystalline semiconductor material and the patterned semiconductor contact material are provided. Blanket layers of passivation material and sacrificial material are formed on the crystalline semiconductor material. A first contact opening is formed into the blanker layer of sacrificial material. The first contact opening is extended into blanket layer of passivation material, stopping on a first surface portion of the crystalline semiconductor material, using remaining sacrificial material portions as an etch mask. A semiconductor contact material is formed on the exposed first surface portion of the crystalline semiconductor material. In some embodiments, an electrode material portion can be formed over the first contact opening, and then a second blanket layer of sacrificial material can be formed, followed by forming a next contact opening. | 11-28-2013 |
20130328110 | THIN FILM HYBRID JUNCTION FIELD EFFECT TRANSISTOR - Junction field effect transistors are provided which include a gate junction located on a surface of a crystalline semiconductor material of a first conductivity type. The gate junction can be selected from one of a doped hydrogenated crystalline semiconductor material layer portion of a second conductivity type which is opposite the first conductivity type, a doped hydrogenated non-crystalline semiconductor material layer portion of a second conductivity type which is opposite the first conductivity type, and a Schottky contact. | 12-12-2013 |
20140060627 | FIELD-EFFECT LOCALIZED EMITTER PHOTOVOLTAIC DEVICE - Photovoltaic structures are provided with field-effect inversion/accumulation layers as emitter layers induced by work-function differences between gate conductor layers and substrates thereof. Localized contact regions are in electrical communication with the gate conductors of such structures for repelling minority carriers. Such localized contact regions may include doped crystalline or polycrystalline silicon regions between the gate conductor and silicon absorption layers. Fabrication of the structures can be conducted without alignment between metal contacts and the localized contact regions or high temperature processing. | 03-06-2014 |
20140183686 | AUTONOMOUS INTEGRATED CIRCUITS - An autonomous integrated circuit (IC) includes a solar cell formed on a bottom substrate of a silicon-on-insulator (SOI) substrate as a handle substrate; an insulating layer of the SOI substrate located on top of the solar cell; and a device layer formed on a top semiconductor layer of the SOI substrate located on top of the insulating layer, wherein a top contact of the device layer is electrically connected to a bottom contact of the solar cell such that the solar cell is enabled to power the device layer. | 07-03-2014 |
20140190564 | HETEROJUNCTION III-V SOLAR CELL PERFORMANCE | 07-10-2014 |
20150047704 | III-V PHOTOVOLTAIC ELEMENTS - Solar cell structures that have improved carrier collection efficiencies at a heterointerface are provided by low temperature epitaxial growth of silicon on a III-V base. Additionally, a solar cell structure having improved open circuit voltage includes a shallow junction III-V emitter formed by epitaxy or diffusion followed by the epitaxy of Si | 02-19-2015 |