Patent application number | Description | Published |
20080203536 | BIPOLAR TRANSISTOR USING SELECTIVE DIELECTRIC DEPOSITION AND METHODS FOR FABRICATION THEREOF - A bipolar transistor structure and related methods for fabrication thereof are provided. A vertical spacer layer is selectively deposited after implanting an extrinsic base region into a semiconductor substrate while using an ion implantation mask located upon a screen dielectric layer located upon the semiconductor substrate. A portion of the ion implantation mask may remain embedded and aligned within a sidewall of an aperture within the vertical spacer layer. The selective deposition of the vertical spacer layer allows for a reduced thermal budget and reduced process complexity when fabricating the bipolar transistor. | 08-28-2008 |
20080217730 | METHODS OF FORMING GAS DIELECTRIC AND RELATED STRUCTURE - Methods of forming a gas dielectric and a related structure are disclosed. In one embodiment, the method includes providing a wiring level including at least one conductive portion within a sacrificial dielectric; forming a nanofiber layer over the wiring level; vaporizing the sacrificial dielectric by heating; evacuating the vaporized sacrificial layer; and sealing pores in the nanofiber layer. | 09-11-2008 |
20080248624 | METHOD OF MAKING INTEGRATED CIRCUIT (IC) INCLUDING AT LEAST ONE STORAGE CELL - A storage cell, integrated circuit (IC) chip with one or more storage cells that may be in an array of the storage cells and a method of forming the storage cell and IC. Each storage cell includes a stylus, the tip of which is phase change material. The phase change tip may be sandwiched between an electrode and conductive material, e.g., titanium nitride (TiN), tantalum nitride (TaN) or n-type semiconductor. The phase change layer may be a chalcogenide and in particular a germanium (Ge), antimony (Sb), tellurium (Te) (GST) layer. | 10-09-2008 |
20080257156 | Carbon Nanotubes As Low Voltage Field Emission Sources for Particle Precipitators - An air particle precipitator and a method of air filtration comprise a housing unit; a first conductor in the housing unit; a second conductor in the housing unit; and a carbon nanotube grown on the second conductor. Preferably, the first conductor is positioned opposite to the second conductor. The air particle precipitator further comprises an electric field source adapted to apply an electric field to the housing unit. Moreover, the carbon nanotube is adapted to ionize gas in the housing unit, wherein the ionized gas charges gas particulates located in the housing unit, and wherein the first conductor is adapted to trap the charged gas particulates. The air particle precipitator may further comprise a metal layer over the carbon nanotube. | 10-23-2008 |
20080271606 | CHEMICAL AND PARTICULATE FILTERS CONTAINING CHEMICALLY MODIFIED CARBON NANOTUBE STRUCTURES - A carbon nanotube filter, a use for a carbon nanotube filter and a method of forming a carbon nanotube filter. The method including (a) providing a carbon source and a carbon nanotube catalyst; (b) growing carbon nanotubes by reacting the carbon source with the nanotube catalyst; (c) forming chemically active carbon nanotubes by forming a chemically active layer on the carbon nanotubes or forming chemically reactive groups on sidewalls of the carbon nanotubes; and (d) placing the chemically active nanotubes in a filter housing. | 11-06-2008 |
20080282893 | CHEMICAL AND PARTICULATE FILTERS CONTAINING CHEMICALLY MODIFIED CARBON NANOTUBE STRUCTURES - A carbon nanotube filter. The filter including a filter housing; and chemically active carbon nanotubes within the filter housing, the chemically active carbon nanotubes comprising a chemically active layer formed on carbon nanotubes or comprising chemically reactive groups on sidewalls of the carbon nanotubes; and media containing the chemically active carbon nanotubes. | 11-20-2008 |
20080284992 | EXPOSURES SYSTEM INCLUDING CHEMICAL AND PARTICULATE FILTERS CONTAINING CHEMICALLY MODIFIED CARBON NANOTUBE STRUCTURES - An exposure system for exposing a photoresist layer on a top surface of a wafer to light. The exposure system including: an environment chamber containing a light source, one or more focusing lenses, a mask holder, a slit and a wafer stage, the light source, all aligned to an optical axis, the wafer stage moveable in two different orthogonal directions orthogonal to the optical axis, the mask holder and the slit moveable in one of the two orthogonal directions; a filter in a sidewall of the environment chamber, the filter including: a filter housing containing chemically active carbon nanotubes, the chemically active carbon nanotubes comprising a chemically active layer formed on carbon nanotubes or comprising chemically reactive groups on sidewalls of the carbon nanotubes; and means for forcing air or inert gas first through the filter then into the environment chamber and then out of the environment chamber. | 11-20-2008 |
20080286466 | CHEMICAL AND PARTICULATE FILTERS CONTAINING CHEMICALLY MODIFIED CARBON NANOTUBE STRUCTURES - A carbon nanotube filter, a use for a carbon nanotube filter and a method of forming a carbon nanotube filter. The method including (a) providing a carbon source and a carbon nanotube catalyst; (b) growing carbon nanotubes by reacting the carbon source with the nanotube catalyst; (c) forming chemically active carbon nanotubes by forming a chemically active layer on the carbon nanotubes or forming chemically reactive groups on sidewalls of the carbon nanotubes; and (d) placing the chemically active nanotubes in a filter housing. | 11-20-2008 |
20080286971 | CMOS Gate Structures Fabricated by Selective Oxidation - A sidewall image transfer process for forming sub-lithographic structures employs a layer of sacrificial material that is deposited over a structure layer and covered by a cover layer. The sacrificial material layer and the cover layer are patterned with conventional resist and etched to form a sacrificial mandrel. The edges of the mandrel are oxidized or nitrided in a plasma at low temperature, after which the material layer and the cover layer are stripped, leaving sublithographic sidewalls. The sidewalls are used as hardmasks to etch sublithographic gate structures in the gate conductor layer. | 11-20-2008 |
20090001337 | Phase Change Memory Cell with Vertical Transistor - A memory cell in an integrated circuit is fabricated in part by forming a lower electrode feature, an island, a sacrificial feature, a gate feature, and a phase change feature. The island is formed on the lower electrode feature and has one or more sidewalls. It comprises a lower doped feature, a middle doped feature formed above the lower doped feature, and an upper doped feature formed above the middle doped feature. The sacrificial feature is formed above the island, while the gate feature is formed along each sidewall of the island. The gate feature overlies at least a portion of the middle doped feature of the island and is operative to control an electrical resistance therein. Finally, the phase feature is formed above the island at least in part by replacing at least a portion of the sacrificial feature with a phase change material. The phase change material is operative to switch between lower and higher electrical resistance states in response to an application of an electrical signal. | 01-01-2009 |
20090014767 | CARBON NANOTUBE CONDUCTOR FOR TRENCH CAPACITORS - A trench-type storage device includes a trench in a substrate ( | 01-15-2009 |
20090032491 | CONDUCTIVE ELEMENT FORMING USING SACRIFICIAL LAYER PATTERNED TO FORM DIELECTRIC LAYER - Methods of forming a conductive element for an integrated circuit (IC) chip and a related structure are disclosed. One embodiment of the method may include forming a first sacrificial layer having a pattern therein for a first dielectric layer to surround the conductive element; forming the first dielectric layer within the patterned first sacrificial layer; removing the patterned first sacrificial layer, leaving the first dielectric layer; and forming the conductive element in a space vacated by the patterned first sacrificial layer. The methods prevent damage caused to low dielectric constant dielectric layers during etching and stripping/cleaning processes. | 02-05-2009 |
20090057730 | METHODS FOR FORMING SELF-ALIGNED BORDERLESS CONTACTS FOR STRAIN ENGINEERED LOGIC DEVICES AND STRUCTURE THEREOF - A method for forming a borderless contact for a semiconductor FET (Field Effect Transistor) device, the method comprising, forming a gate conductor stack on a substrate, forming spacers on the substrate, such that the spacers and the gate conductor stack partially define a volume above the gate conductor stack, wherein the spacers are sized to define the volume such that a stress liner layer deposited on the gate conductor stack substantially fills the volume, depositing a liner layer on the substrate, the spacers, and the gate conductor stack, depositing a dielectric layer on the liner layer, etching to form a contact hole in the dielectric layer, etching to form the contact hole in the liner layer, such that a portion of a source/drain diffusion area formed in the substrate is exposed and depositing contact metal in the contact hole. | 03-05-2009 |
20090072317 | MICROELECTRONIC STRUCTURE BY SELECTIVE DEPOSITION - A finFET structure includes a semiconductor fin located over a substrate. A gate electrode is located traversing the semiconductor fin. The gate electrode has a spacer layer located adjoining a sidewall thereof. The spacer layer does not cover completely a sidewall of the semiconductor fin. The gate electrode and the spacer layer may be formed using a vapor deposition method that provides for selective deposition upon a sidewall of a mandrel layer but not upon an adjoining surface of the substrate, so that the spacer layer does not cover completely the sidewall of the semiconductor fin. Other microelectronic structures may be fabricated using the lateral growth methodology. | 03-19-2009 |
20090075439 | MICROELECTRONIC STRUCTURE BY SELECTIVE DEPOSITION - A finFET structure includes a semiconductor fin located over a substrate. A gate electrode is located traversing the semiconductor fin. The gate electrode has a spacer layer located adjoining a sidewall thereof. The spacer layer does not cover completely a sidewall of the semiconductor fin. The gate electrode and the spacer layer may be formed using a vapor deposition method that provides for selective deposition upon a sidewall of a mandrel layer but not upon an adjoining surface of the substrate so that the spacer layer does not cover completely the sidewall of the semiconductor fin. Other microelectronic structures may be fabricated using the lateral growth methodology. | 03-19-2009 |
20090087795 | METHOD AND APPARATUS FOR CLEANING A SEMICONDUCTOR SUBSTRATE IN AN IMMERSION LITHOGRAPHY SYSTEM - A method and apparatus for reduction and prevention of residue formation and removal of residues formed in an immersion lithography tool. The apparatus including incorporation of a cleaning mechanism within the immersion head of an immersion lithographic system or including a cleaning mechanism in a cleaning station of an immersion lithographic system. | 04-02-2009 |
20090121298 | FIELD EFFECT TRANSISTOR - A transistor. The transistor including: a well region in a substrate; a gate dielectric layer on a top surface of the well region; a polysilicon gate electrode on a top surface of the gate dielectric layer; spacers formed on opposite sidewalls of the polysilicon gate electrode; source/drain regions formed on opposite sides of the polysilicon gate electrode in the well region; a first doped region in the polysilicon gate electrode, the first doped region extending into the polysilicon gate electrode from a top surface of the polysilicon gate electrode; and a buried second doped region in the polysilicon gate electrode. | 05-14-2009 |
20090184400 | VIA GOUGING METHODS AND RELATED SEMICONDUCTOR STRUCTURE - Methods for via gouging and a related semiconductor structure are disclosed. In one embodiment, the method includes forming a via opening in a dielectric material, the via opening aligned with a conductor; forming a protective coating over the dielectric material and in the via opening; performing via gouging; and removing the protective coating over horizontal surfaces of the dielectric material. A semiconductor structure may include a via having an interface with a conductor, the interface including a three-dimensionally shaped region extending into and past a surface of the conductor, wherein an outer edge of the three-dimensionally shaped region is distanced from an outermost surface of the via. | 07-23-2009 |
20090200636 | SUB-LITHOGRAPHIC DIMENSIONED AIR GAP FORMATION AND RELATED STRUCTURE - Sub-lithographic dimensioned air gap formation and related structure are disclosed. In one embodiment, a method includes forming a dielectric layer including interconnects on a substrate; depositing a cap layer on the dielectric layer; depositing a photoresist over the cap layer; patterning the photoresist to include a first trench pattern at most partially overlying the interconnects; forming a spacer within the first trench pattern to form a second trench pattern having a sub-lithographic dimension; transferring the second trench pattern into the cap layer and into the dielectric layer between the interconnects; and depositing another dielectric layer to form an air gap by pinching off the trench in the dielectric layer. | 08-13-2009 |
20090278226 | STRUCTURE FOR CONDUCTIVE LINER FOR RAD HARD TOTAL DOSE IMMUNITY AND STRUCTURE THEREOF - The invention relates to a design structure, and more particularly, to a design structure for a conductive liner for rad hard total dose immunity and a structure thereof. The structure includes at least one shallow trench isolation structure having oxide material and formed in an SIO. A dielectric liner is formed at an interface of the SIO within the at least one shallow trench isolation structure. A metal or metal alloy layer is formed in the at least one shallow trench isolation structure and between the dielectric liner and the oxide material. | 11-12-2009 |
20090278258 | INTERCONNECT STRUCTURE WITH A MUSHROOM-SHAPED OXIDE CAPPING LAYER AND METHOD FOR FABRICATING SAME - An interconnect structure is provided that includes a dielectric material | 11-12-2009 |
20090280619 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE HAVING CONDUCTIVE LINER FOR RAD HARD TOTAL DOSE IMMUNITY - The invention relates to a method includes etching at least one shallow trench in at least an SIO layer; forming a dielectric liner at an interface of the SIO layer and the SIO layer; forming a metal or metal alloy layer in the shallow trench on the dielectric liner; and filling the shallow trench with oxide material over the metal or metal alloy. | 11-12-2009 |
20090305508 | INTEGRATED CIRCUIT WITH UPSTANDING STYLUS - A stylus, an integrated circuit (IC) and method of forming the IC. The stylus extends upward from its apex and has a substantially circular cross section that decreases in diameter upward from the apex. The stylus is formed in a mold that may be formed in an orifice in a dielectric layer between wiring layers. The mold may include multiple concentric layers. For a more pronounced, non-linear stylus taper, each layer may be thinner than its next adjacent outer concentric layer. | 12-10-2009 |
20090309226 | Interconnect Structure for Electromigration Enhancement - An interconnect structure having enhanced electromigration resistance is provided in which a lower portion of a via opening includes a multi-layered liner. The multi-layered liner includes, from a patterned surface of a dielectric material outwards, a diffusion barrier, a multi-material layer and a metal-containing hard mask. The multi-material layer includes a first material layer comprised of residue from an underlying dielectric capping layer, and a second material layer comprised of residue from an underlying metallic capping layer. The present invention also provides a method of fabricating such an interconnect structure which includes the multi-layered liner within a lower portion of a via opening formed within a dielectric material. | 12-17-2009 |
20090321833 | VERTICAL PROFILE FinFET GATE FORMED VIA PLATING UPON A THIN GATE DIELECTRIC - Methods of making vertical profile FinFET gate electrodes via plating upon a thin gate dielectric are disclosed. In one embodiment, a method for forming a transistor, comprises: providing a semiconductor topography comprising a semiconductor substrate and a semiconductor fin structure extending above the substrate; forming a gate dielectric across exposed surfaces of the semiconductor topography; patterning a mask upon the semiconductor topography such that only a select portion of the gate dielectric is exposed that defines where a gate electrode is to be formed; and plating a metallic material upon the select portion of the gate dielectric to form a gate electrode across a portion of the fin structure. | 12-31-2009 |
20100009131 | MULTI-EXPOSURE LITHOGRAPHY EMPLOYING A SINGLE ANTI-REFLECTIVE COATING LAYER - A first photoresist is applied over an optically dense layer and lithographically patterned to form an array of first photoresist portions having a pitch near twice a minimum feature size. The pattern in the first photoresist portions, or a first pattern, is transferred into the ARC layer and partly into the optically dense layer. A second photoresist is applied and patterned into another array having a pitch near twice the minimum feature size and interlaced with the first pattern. The pattern in the second photoresist, or a second pattern, is transferred through the ARC portions and partly into the optically dense layer. The ARC portions are patterned with a composite pattern including the first pattern and the second pattern. The composite pattern is transferred through the optically dense layer and into the underlayer to form a sublithographic pattern in the underlayer. | 01-14-2010 |
20100119422 | CHEMICAL AND PARTICULATE FILTERS CONTAINING CHEMICALLY MODIFIED CARBON NANOTUBE STRUCTURES - A carbon nanotube filter. The filter including a filter housing; and chemically active carbon nanotubes within the filter housing, the chemically active carbon nanotubes comprising a chemically active layer formed on carbon nanotubes or comprising chemically reactive groups on sidewalls of the carbon nanotubes; and media containing the chemically active carbon nanotubes. | 05-13-2010 |
20100193471 | METHOD AND SYSTEM FOR CONTROLLING RADICAL DISTRIBUTION - A plasma processing system includes a processing chamber, a substrate holder configured to hold a substrate for plasma processing, and a gas injection assembly. The gas injection assembly includes a first evacuation port located substantially in a center of the gas injection assembly and configured to evacuate gases from a central region of the substrate, and a gas injection system configured to inject gases in the process chamber. The plasma processing system also includes a second evacuation port configured to evacuate gases from a peripheral region surrounding the central region of the substrate. | 08-05-2010 |
20100227471 | Pseudo Hybrid Structure for Low K Interconnect Integration - A method and apparatus are described for fabricating an ultra low-k interconnect structure by depositing and curing a first via layer ( | 09-09-2010 |
20100264543 | INTERCONNECT STRUCTURE - An interconnect structure and methods for forming semiconductor interconnect structures are disclosed. In one embodiment, the interconnect structure includes: a substrate including a first liner layer and a first metal layer thereover; a dielectric barrier layer over the first metal layer and the substrate; an inter-level dielectric layer over the dielectric barrier layer; a via extending between the inter-level dielectric layer, the dielectric barrier layer, and the first metal layer, the via including a second liner layer and a second metal layer thereover; and a diffusion barrier layer located between the second liner layer and the first metal layer, wherein a portion of the diffusion barrier layer is located under the dielectric barrier layer. | 10-21-2010 |
20110027951 | SHARED GATE FOR CONVENTIONAL PLANAR DEVICE AND HORIZONTAL CNT - A semiconductor structure in which a planar semiconductor device and a horizontal carbon nanotube transistor have a shared gate and a method of fabricating the same are provided in the present application. The hybrid semiconductor structure includes at least one horizontal carbon nanotube transistor and at least one planar semiconductor device, in which the at least one horizontal carbon nanotube transistor and the at least one planar semiconductor device have a shared gate and the at least one horizontal carbon nanotube transistor is located above a gate of the at least one planar semiconductor device. | 02-03-2011 |
20110084403 | PAD BONDING EMPLOYING A SELF-ALIGNED PLATED LINER FOR ADHESION ENHANCEMENT - Two substrates are brought together and placed in a plating bath. In one embodiment, a conductive material is plated in microscopic cavities present at the interface between a first metal pad and a second metal pad to form at least one interfacial plated metal liner portion that adheres to a surface of the first metal pad and a surface of the second metal pad. In another embodiment, at least one metal pad is recessed relative to a dielectric surface before being brought together. The two substrates are placed in a plating bath and a conductive material is plated in the cavity between the first metal pad and the second metal pad to form a contiguous plated metal liner layer that adheres to a surface of the first metal pad and a surface of the second metal pad. | 04-14-2011 |
20110101538 | CREATION OF VIAS AND TRENCHES WITH DIFFERENT DEPTHS - Embodiments of the invention provide a method of creating vias and trenches with different length. The method includes depositing a plurality of dielectric layers on top of a semiconductor structure with the plurality of dielectric layers being separated by at least one etch-stop layer; creating multiple openings from a top surface of the plurality of dielectric layers down into the plurality of dielectric layers by a non-selective etching process, wherein at least one of the multiple openings has a depth below the etch-step layer; and continuing etching the multiple openings by a selective etching process until one or more openings of the multiple openings that are above the etch-stop layer reach and expose the etch-stop layer. Semiconductor structures made thereby are also provided. | 05-05-2011 |
20110163450 | INTEGRATED CIRCUIT LINE WITH ELECTROMIGRATION BARRIERS - A method for fabricating an integrated circuit comprising an electromigration barrier in a line of the integrated circuit includes forming a spacer; forming a segmented line adjacent to opposing sides of the spacer, the segmented line formed from a first conductive material; removing the spacer to form an empty line break; and filling the empty line break with a second conductive material to form an electromigration barrier that isolates electromigration effects within individual segments of the segmented line. An integrated circuit comprising an electromigration barrier includes a line, the line comprising a first conductive material, the line further comprising a plurality of line segments separated by one or more electromigration barriers, wherein the one or more electromigration barriers comprise a second conductive material that isolates electromigration effects within individual segments of the line. | 07-07-2011 |
20110193230 | FORMATION OF AIR GAP WITH PROTECTION OF METAL LINES - A method is provided for fabricating a microelectronic element having an air gap in a dielectric layer thereof. A dielectric cap layer can be formed which has a first portion overlying surfaces of metal lines, the first portion extending a first height above a height of a surface of the dielectric layer and a second portion overlying the dielectric layer surface and extending a second height above the height of the surface of the dielectric layer, the second height being greater than the first height. After forming the cap layer, a mask can be formed over the cap layer. The mask can have a multiplicity of randomly disposed holes. Each hole may expose a surface of only the second portion of the cap layer which has the greater height. The mask may fully cover a surface of the first portion of the cap layer having the lower height. Subsequently, an etchant can be directed towards the first and second portions of the cap layer to form holes in the cap layer aligned with the holes in the mask. Material can be removed from the dielectric layer where exposed to the etchant by the holes in the cap layer. At such time, the mask can protect the first portion of the cap layer and the metal lines from being attacked by the etchant. | 08-11-2011 |
20110266621 | FIELD EFFECT TRANSISTOR - A transistor. The transistor including: a well region in a substrate; a gate dielectric layer on a top surface of the well region; a polysilicon gate electrode on a top surface of the gate dielectric layer; spacers formed on opposite sidewalls of the polysilicon gate electrode; source/drain regions formed on opposite sides of the polysilicon gate electrode in the well region; a first doped region in the polysilicon gate electrode, the first doped region extending into the polysilicon gate electrode from a top surface of the polysilicon gate electrode; and a buried second doped region in the polysilicon gate electrode. | 11-03-2011 |
20110266682 | MICROELECTRONIC STRUCTURE INCLUDING AIR GAP - A microelectronic structure and a method for fabricating the microelectronic structure provide a plurality of voids interposed between a plurality of conductor layers. The plurality of voids is also located between a liner layer and an inter-level dielectric layer. The voids provide for enhanced electrical performance of the microelectronic structure. | 11-03-2011 |
20110303983 | FINFET DEVICES AND METHODS OF MANUFACTURE - A finFET structure and method of manufacture such structure is provided with lowered Ceff and enhanced stress. The finFET structure includes a plurality of finFET structures and a stress material forming part of a gate stack and in a space between adjacent ones of the plurality of finFET structures. | 12-15-2011 |
20120037962 | SEMICONDUCTOR STRUCTURE HAVING A CONTACT-LEVEL AIR GAP WITHIN THE INTERLAYER DIELECTRICS ABOVE A SEMICONDUCTOR DEVICE AND A METHOD OF FORMING THE SEMICONDUCTOR STRUCTURE USING A SELF-ASSEMBLY APPROACH - Disclosed are embodiments of a semiconductor structure having a contact-level air gap within the interlayer dielectrics above a semiconductor device in order to minimize parasitic capacitances (e.g., contact-to-contact capacitance, contact-to-diffusion region capacitance, gate-to-contact capacitance, gate-to-diffusion region capacitance, etc.). Specifically, the structure can comprise a semiconductor device on a substrate and at least three dielectric layers stacked above the semiconductor device. An air gap is positioned with the second dielectric layer aligned above the semiconductor device and extending vertically from the first dielectric layer to the third dielectric layer. Also disclosed are embodiments of a method of forming such a semiconductor structure using a self-assembly approach. | 02-16-2012 |
20120074520 | ELECTRICAL FUSE STRUCTURE AND METHOD OF FABRICATING SAME - A high programming efficiency electrical fuse is provided utilizing a dual damascene structure located atop a metal layer. The dual damascene structure includes a patterned dielectric material having a line opening located above and connected to an underlying via opening. The via opening is located atop and is connected to the metal layer. The dual damascene structure also includes a conductive feature within the line opening and the via opening. Dielectric spacers are also present within the line opening and the via opening. The dielectric spacers are present on vertical sidewalls of the patterned dielectric material and separate the conductive feature from the patterned dielectric material. The presence of the dielectric spacers within the line opening and the via opening reduces the area in which the conductive feature is formed. As such, a high programming efficiency electrical fuse is provided in which space is saved. | 03-29-2012 |
20120086128 | BORDERLESS INTERCONNECT LINE STRUCTURE SELF-ALIGNED TO UPPER AND LOWER LEVEL CONTACT VIAS - A metal layer is deposited on a planar surface on which top surfaces of underlying metal vias are exposed. The metal layer is patterned to form at least one metal block, which has a horizontal cross-sectional area of a metal line to be formed and at least one overlying metal via to be formed. Each upper portion of underlying metal vias is recessed outside of the area of a metal block located directly above. The upper portion of the at least one metal block is lithographically patterned to form an integrated line and via structure including a metal line having a substantially constant width and at least one overlying metal via having the same substantially constant width and borderlessly aligned to the metal line. An overlying-level dielectric material layer is deposited and planarized so that top surface(s) of the at least one overlying metal via is/are exposed. | 04-12-2012 |
20120104470 | REPLACEMENT GATE MOSFET WITH RAISED SOURCE AND DRAIN - A disposable dielectric spacer is formed on sidewalls of a disposable material stack. Raised source/drain regions are formed on planar source/drain regions by selective epitaxy. The disposable dielectric spacer is removed to expose portions of a semiconductor layer between the disposable material stack and the source/drain regions including the raised source/drain regions. Dopant ions are implanted to form source/drain extension regions in the exposed portions of the semiconductor layer. A gate-level dielectric layer is deposited and planarized. The disposable material stack is removed and a gate stack including a gate dielectric and a gate electrode fill a cavity formed by removal of the disposable material stack. Optionally, an inner dielectric spacer may be formed on sidewalls of the gate-level dielectric layer within the cavity prior to formation of the gate stack to tailor a gate length of a field effect transistor. | 05-03-2012 |
20120104512 | SEALED AIR GAP FOR SEMICONDUCTOR CHIP - A semiconductor chip including a substrate; a dielectric layer over the substrate; a gate within the dielectric layer, the gate including a sidewall; a contact contacting a portion of the gate and a portion of the sidewall; and a sealed air gap between the sidewall, the dielectric layer and the contact. | 05-03-2012 |
20120104619 | SUBLITHOGRAPHIC PATTERNING EMPLOYING IMAGE TRANSFER OF A CONTROLLABLY DAMAGED DIELECTRIC SIDEWALL - A first low dielectric constant (low-k) dielectric material layer is lithographically patterned to form a recessed region having expose substantially vertical sidewalls, which are subsequently damaged to de-carbonize a surface portion at the sidewalls having a sublithographic width. A second low-k dielectric material layer is deposited to fill the recessed region and planarized to exposed top surfaces of the damaged low-k dielectric material portion. The damaged low-k dielectric material portion is removed selective to the first and second low-k dielectric material layers to form a trench with a sublithographic width. A portion of the pattern of the sublithographic-width trench is transferred into a metallic layer and optionally to an underlying dielectric masking material layer to define a trench with a sublithographic width, which can be employed as a template to confine the widths of via holes and line trenches to be subsequently formed in an interconnect-level dielectric material layer. | 05-03-2012 |
20120142182 | MICROELECTRONIC STRUCTURE BY SELECTIVE DEPOSITION - A finFET structure includes a semiconductor fin located over a substrate. A gate electrode is located traversing the semiconductor fin. The gate electrode has a spacer layer located adjoining a sidewall thereof. The spacer layer does not cover completely a sidewall of the semiconductor fin. The gate electrode and the spacer layer may be formed using a vapor deposition method that provides for selective deposition upon a sidewall of a mandrel layer but not upon an adjoining surface of the substrate, so that the spacer layer does not cover completely the sidewall of the semiconductor fin. Other microelectronic structures may be fabricated using the lateral growth methodology. | 06-07-2012 |
20120153503 | CREATION OF VIAS AND TRENCHES WITH DIFFERENT DEPTHS - Embodiments of the invention provide a method of creating vias and trenches with different length. The method includes depositing a plurality of dielectric layers on top of a semiconductor structure with the plurality of dielectric layers being separated by at least one etch-stop layer; creating multiple openings from a top surface of the plurality of dielectric layers down into the plurality of dielectric layers by a non-selective etching process, wherein at least one of the multiple openings has a depth below the etch-step layer; and continuing etching the multiple openings by a selective etching process until one or more openings of the multiple openings that are above the etch-stop layer reach and expose the etch-stop layer. Semiconductor structures made thereby are also provided. | 06-21-2012 |
20120171859 | CREATION OF VIAS AND TRENCHES WITH DIFFERENT DEPTHS - Embodiments of the invention provide a method of creating vias and trenches with different length. The method includes depositing a plurality of dielectric layers on top of a semiconductor structure with the plurality of dielectric layers being separated by at least one etch-stop layer; creating multiple openings from a top surface of the plurality of dielectric layers down into the plurality of dielectric layers by a non-selective etching process, wherein at least one of the multiple openings has a depth below the etch-step layer; and continuing etching the multiple openings by a selective etching process until one or more openings of the multiple openings that are above the etch-stop layer reach and expose the etch-stop layer. Semiconductor structures made thereby are also provided. | 07-05-2012 |
20120175775 | INTEGRATED CIRCUIT LINE WITH ELECTROMIGRATION BARRIERS - An integrated circuit comprising an electromigration barrier includes a line, the line comprising a first conductive material, the line further comprising a plurality of line segments separated by one or more electromigration barriers, wherein the one or more electromigration barriers comprise a second conductive material that isolates electromigration effects within individual segments of the line. | 07-12-2012 |
20120187566 | AIR-DIELECTRIC FOR SUBTRACTIVE ETCH LINE AND VIA METALLIZATION - A method and structure is disclosed whereby multiple interconnect layers having effective air gaps positioned in regions most susceptible to capacitive coupling can be formed. The method includes providing a layer of conductive features, the layer including at least two line members disposed on a substrate and spaced from one another by less than or equal to an effective distance, and at least one such line member also having a via member extending away from the substrate, depositing a poorly conformal dielectric coating to form an air gap between such line members, and exposing a top end of the via. | 07-26-2012 |
20120190179 | METHODS OF MANUFACTURING FINFET DEVICES - A finFET structure and method of manufacture such structure is provided with lowered Ceff and enhanced stress. The finFET structure includes a plurality of finFET structures and a stress material forming part of a gate stack and in a space between adjacent ones of the plurality of finFET structures. | 07-26-2012 |
20120190187 | PAD BONDING EMPLOYING A SELF-ALIGNED PLATED LINER FOR ADHESION ENHANCEMENT - Two substrates are brought together and placed in a plating bath. In one embodiment, a conductive material is plated in microscopic cavities present at the interface between a first metal pad and a second metal pad to form at least one interfacial plated metal liner portion that adheres to a surface of the first metal pad and a surface of the second metal pad. In another embodiment, at least one metal pad is recessed relative to a dielectric surface before being brought together. The two substrates are placed in a plating bath and a conductive material is plated in the cavity between the first metal pad and the second metal pad to form a contiguous plated metal liner layer that adheres to a surface of the first metal pad and a surface of the second metal pad. | 07-26-2012 |
20120199886 | SEALED AIR GAP FOR SEMICONDUCTOR CHIP - A semiconductor chip, including a substrate; a dielectric layer over the substrate; a gate within the dielectric layer, the gate including a sidewall; a source and a drain in the substrate adjacent to the gate; a tapered contact contacting a portion of one of the source or the drain; and a sealed air gap between the sidewall and the contact. | 08-09-2012 |
20120208356 | Device component forming method with a trim step prior to sidewall image transfer (SIT) processing - Disclosed is an imaging method for patterning component shapes (e.g., fins, gate electrodes, etc.) into a substrate. By conducting a trim step prior to performing either an additive or subtractive sidewall image transfer process, the method avoids the formation of a loop pattern in a hard mask and, thus, avoids a post-SIT process trim step requiring alignment of a trim mask to sub-lithographic features to form a hard mask pattern with the discrete segments. In one embodiment a hard mask is trimmed prior to conducting an additive SIT process so that a loop pattern is not formed. In another embodiment an oxide layer and memory layer that are used to form a mandrel are trimmed prior to the conducting a subtractive SIT process. A mask is then used to protect portions of the mandrel during etch back of the oxide layer so that a loop pattern is not formed. | 08-16-2012 |
20120241913 | MICROELECTRONIC SUBSTRATE HAVING REMOVABLE EDGE EXTENSION ELEMENT - An article including a microelectronic substrate is provided as an article usable during the processing of the microelectronic substrate. Such article includes a microelectronic substrate having a front surface, a rear surface opposite the front surface and a peripheral edge at boundaries of the front and rear surfaces. The front surface is a major surface of the article. A removable annular edge extension element having a front surface, a rear surface and an inner edge extending between the front and rear surfaces has the inner edge joined to the peripheral edge of the microelectronic substrate. In such way, a continuous surface is formed which includes the front surface of the edge extension element extending laterally from the peripheral edge of the microelectronic substrate and the front surface of the microelectronic substrate, the continuous surface being substantially co-planar and flat where the peripheral edge is joined to the inner edge. | 09-27-2012 |
20120248508 | FORMING BORDERLESS CONTACT FOR TRANSISTORS IN A REPLACEMENT METAL GATE PROCESS - Embodiments of the present invention provide a method of forming a semiconductor structure. The method includes creating an opening inside a dielectric layer, the dielectric layer being formed on top of a substrate and the opening exposing a channel region of a transistor in the substrate; depositing a work-function layer lining the opening and covering the channel region; forming a gate conductor covering a first portion of the work-function layer, the first portion of the work-function layer being on top of the channel region; and removing a second portion of the work-function layer, the second portion of the work-function layer surrounding the first portion of the work-function layer, wherein the removal of the second portion of the work-function layer insulates the first portion of the work-function layer from rest of the work-function layer. | 10-04-2012 |
20120273848 | BORDERLESS CONTACT STRUCTURE EMPLOYING DUAL ETCH STOP LAYERS - Each gate structure formed on the substrate includes a gate dielectric, a gate conductor, a first etch stop layer, and a gate cap dielectric. A second etch stop layer is formed over the gate structures, gate spacers, and source and drain regions. A first contact-level dielectric layer and a second contact-level dielectric layer are formed over the second etch stop layer. Gate contact via holes extending at least to the top surface of the gate cap dielectrics are formed. Source/drain contact via holes extending to the interface between the first and second contact-level dielectric layers are subsequently formed. The various contact via holes are vertically extended by simultaneously etching exposed gate cap dielectrics and exposed portions of the first contact-level dielectric layer, then by simultaneously etching the first and second etch stop layers. Source/drain contact vias self-aligned to the outer surfaces gate spacers are thereby formed. | 11-01-2012 |
20120282779 | SIDEWALL IMAGE TRANSFER PROCESS EMPLOYING A CAP MATERIAL LAYER FOR A METAL NITRIDE LAYER - A cap material layer is deposited on a metal nitride layer. An antireflective coating (ARC) layer, an organic planarizing layer (OPL), and patterned line structures are formed upon the cap material layer. The pattern in the patterned line structures is transferred into the ARC layer and the OPL. Exposed portions of the cap material layer are etched simultaneously with the etch removal of the patterned line structures and the ARC layer. The OPL is employed to etch the metal nitride layer. The patterned cap material layer located over the metal nitride layer protects the top surface of the metal nitride layer, and enables high fidelity reproduction of the pattern in the metal nitride layer without pattern distortion. The metal nitride layer is subsequently employed as an etch mask for pattern transfer into an underlying layer. | 11-08-2012 |
20120326237 | LOW-PROFILE LOCAL INTERCONNECT AND METHOD OF MAKING THE SAME - Embodiments of the present invention provide a structure. The structure includes a plurality of field-effect-transistors having gate stacks formed on top of a semiconductor substrate, the gate stacks having spacers formed at sidewalls thereof; and one or more conductive contacts formed directly on top of the semiconductor substrate and interconnecting at least one source/drain of one of the plurality of field-effect-transistors to at least one source/drain of another one of the plurality of field-effect-transistors, wherein the one or more conductive contacts is part of a low-profile local interconnect that has a height lower than a height of the gate stacks. | 12-27-2012 |
20120329275 | BORDERLESS INTERCONNECT LINE STRUCTURE SELF-ALIGNED TO UPPER AND LOWER LEVEL CONTACT VIAS - A metal layer is deposited on a planar surface on which top surfaces of underlying metal vias are exposed. The metal layer is patterned to form at least one metal block, which has a horizontal cross-sectional area of a metal line to be formed and at least one overlying metal via to be formed. Each upper portion of underlying metal vias is recessed outside of the area of a metal block located directly above. The upper portion of the at least one metal block is lithographically patterned to form an integrated line and via structure including a metal line having a substantially constant width and at least one overlying metal via having the same substantially constant width and borderlessly aligned to the metal line. An overlying-level dielectric material layer is deposited and planarized so that top surface(s) of the at least one overlying metal via is/are exposed. | 12-27-2012 |
20130009249 | FINFET DEVICES AND METHODS OF MANUFACTURE - A finFET structure and method of manufacture such structure is provided with lowered Ceff and enhanced stress. The finFET structure includes a plurality of finFET structures and a stress material forming part of a gate stack and in a space between adjacent ones of the plurality of finFET structures. | 01-10-2013 |
20130009282 | MICROELECTRONIC STRUCTURE INCLUDING AIR GAP - A microelectronic structure and a method for fabricating the microelectronic structure provide a plurality of voids interposed between a plurality of conductor layers. The plurality of voids is also located between a liner layer and an inter-level dielectric layer. The voids provide for enhanced electrical performance of the microelectronic structure. | 01-10-2013 |
20130012017 | MICROELECTRONIC STRUCTURE INCLUDING AIR GAP - A microelectronic structure and a method for fabricating the microelectronic structure provide a plurality of voids interposed between a plurality of conductor layers. The plurality of voids is also located between a liner layer and an inter-level dielectric layer. The voids provide for enhanced electrical performance of the microelectronic structure. | 01-10-2013 |
20130023115 | Borderless Contacts in Semiconductor Devices - A method includes depositing a dummy fill material over exposed portions of a substrate and a gate stack disposed on the substrate, removing portions of the dummy fill material to expose portions of the substrate, forming a layer of spacer material over the exposed portions of the substrate, the dummy fill material and the gate stack, removing portions of the layer of spacer material to expose portions of the substrate and the dummy fill material, depositing a dielectric layer over the exposed portions of the spacer material, the substrate, and the gate stack, removing portions of the dielectric layer to expose portions of the spacer material, removing exposed portions of the spacer material to expose portions of the substrate and define at least one cavity in the dielectric layer, and depositing a conductive material in the at least one cavity. | 01-24-2013 |
20130026570 | BORDERLESS CONTACT FOR ULTRA-THIN BODY DEVICES - After formation of a semiconductor device on a semiconductor-on-insulator (SOI) layer, a first dielectric layer is formed over a recessed top surface of a shallow trench isolation structure. A second dielectric layer that can be etched selective to the first dielectric layer is deposited over the first dielectric layer. A contact via hole for a device component located in or on a top semiconductor layer is formed by an etch. During the etch, the second dielectric layer is removed selective to the first dielectric layer, thereby limiting overetch into the first dielectric layer. Due to the etch selectivity, a sufficient amount of the first dielectric layer is present between the bottom of the contact via hole and a bottom semiconductor layer, thus providing electrical isolation for the ETSOI device from the bottom semiconductor layer. | 01-31-2013 |
20130026635 | Hybrid Copper Interconnect Structure and Method of Fabricating Same - A hybrid interconnect structure containing copper regions that have different impurities levels within a same opening is provided. In one embodiment, the interconnect structure includes a patterned dielectric material having at least one opening located therein. A dual material liner is located at least on sidewalls of the patterned dielectric material within the at least one opening. The structure further includes a first copper region having a first impurity level located within a bottom region of the at least one opening and a second copper region having a second impurity level located within a top region of the at least one opening and atop the first copper region. In accordance with the present disclosure, the first impurity level of the first copper region is different from the second impurity level of the second copper region. The copper regions containing the different impurities levels can be achieved utilizing a combination of physical vapor deposition of a copper region having a low impurity level (i.e., less than 20 ppm) and copper reflow, with electroplating another copper region having a high impurity level (i.e., 100 ppm or greater). | 01-31-2013 |
20130043556 | SIZE-FILTERED MULTIMETAL STRUCTURES - A size-filtered metal interconnect structure allows formation of metal structures having different compositions. Trenches having different widths are formed in a dielectric material layer. A blocking material layer is conformally deposited to completely fill trenches having a width less than a threshold width. An isotropic etch is performed to remove the blocking material layer in wide trenches, i.e., trenches having a width greater than the threshold width, while narrow trenches, i.e., trenches having a width less than the threshold width, remain plugged with remaining portions of the blocking material layer. The wide trenches are filled and planarized with a first metal to form first metal structures having a width greater than the critical width. The remaining portions of the blocking material layer are removed to form cavities, which are filled with a second metal to form second metal structures having a width less than the critical width. | 02-21-2013 |
20130069161 | INTEGRATED CIRCUIT STRUCTURE HAVING SELECTIVELY FORMED METAL CAP - Methods of forming an integrated circuit structure utilizing a selectively formed and at least partially oxidized metal cap over a gate, and associated structures. In one embodiment, a method includes providing a precursor structure including a transistor having a metal gate; forming an etch stop layer over an exposed portion of the metal gate; at least partially oxidizing the etch stop layer; and forming a dielectric layer over the at least partially oxidized etch stop layer. | 03-21-2013 |
20130112462 | Metal Alloy Cap Integration - A metal interconnect structure, which includes metal alloy capping layers, and a method of manufacturing the same. The originally deposited alloy capping layer element within the interconnect features will diffuse into and segregate onto top surface of the metal interconnect. The metal alloy capping material is deposited on a reflowed copper surface and is not physically in contact with sidewalls of the interconnect features. Thus, there is a reduction in electrical resistivity impact from residual alloy elements in the interconnect structure. That is, there is a reduction, of alloy elements inside the features of the metal interconnect structure. The metal interconnect structure includes a dielectric layer with a recessed line, a liner material on sidewalls, a copper material, an alloy cap, and a capping layer. | 05-09-2013 |
20130130489 | SEALED AIR GAP FOR SEMICONDUCTOR CHIP - A method for forming a sealed air gap for a semiconductor chip including forming a gate over a substrate; forming a sacrificial spacer adjacent to the gate; forming a first dielectric layer about the gate and the sacrificial spacer; forming a contact to the gate; substantially removing the sacrificial spacer, wherein a space is formed between the gate and the first dielectric layer; and forming a sealed air gap in the space by depositing a second dielectric layer over the first dielectric layer. | 05-23-2013 |
20130134517 | BORDERLESS CONTACT FOR ULTRA-THIN BODY DEVICES - After formation of a semiconductor device on a semiconductor-on-insulator (SOI) layer, a first dielectric layer is formed over a recessed top surface of a shallow trench isolation structure. A second dielectric layer that can be etched selective to the first dielectric layer is deposited over the first dielectric layer. A contact via hole for a device component located in or on a top semiconductor layer is formed by an etch. During the etch, the second dielectric layer is removed selective to the first dielectric layer, thereby limiting overetch into the first dielectric layer. Due to the etch selectivity, a sufficient amount of the first dielectric layer is present between the bottom of the contact via hole and a bottom semiconductor layer, thus providing electrical isolation for the ETSOI device from the bottom semiconductor layer. | 05-30-2013 |
20130134590 | FORMATION OF AIR GAP WITH PROTECTION OF METAL LINES - A microelectronic substrate which includes a dielectric layer overlying a semiconductor region of a substrate, the dielectric layer having an exposed top surface; a plurality of metal lines of a first metal disposed within the dielectric layer, each metal line having edges and a surface exposed at the top surface of the dielectric layer; a dielectric cap layer having a first portion overlying the surfaces of the metal lines and a second portion overlying the dielectric layer between the metal lines, the first portion has a first height above the surface of the dielectric layer, and the second portion has a second height above the surface of the dielectric layer, the second height being greater than the first height; and an air gap disposed between the metal lines, the air gap underlying the second portion of the cap layer. | 05-30-2013 |
20130161697 | REPLACEMENT GATE MOSFET WITH RAISED SOURCE AND DRAIN - A disposable dielectric spacer is formed on sidewalls of a disposable material stack. Raised source/drain regions are formed on planar source/drain regions by selective epitaxy. The disposable dielectric spacer is removed to expose portions of a semiconductor layer between the disposable material stack and the source/drain regions including the raised source/drain regions. Dopant ions are implanted to form source/drain extension regions in the exposed portions of the semiconductor layer. A gate-level dielectric layer is deposited and planarized. The disposable material stack is removed and a gate stack including a gate dielectric and a gate electrode fill a cavity formed by removal of the disposable material stack. Optionally, an inner dielectric spacer may be formed on sidewalls of the gate-level dielectric layer within the cavity prior to formation of the gate stack to tailor a gate length of a field effect transistor. | 06-27-2013 |
20130168749 | BORDERLESS CONTACT STRUCTURE EMPLOYING DUAL ETCH STOP LAYERS - Each gate structure formed on the substrate includes a gate dielectric, a gate conductor, a first etch stop layer, and a gate cap dielectric. A second etch stop layer is formed over the gate structures, gate spacers, and source and drain regions. A first contact-level dielectric layer and a second contact-level dielectric layer are formed over the second etch stop layer. Gate contact via holes extending at least to the top surface of the gate cap dielectrics are formed. Source/drain contact via holes extending to the interface between the first and second contact-level dielectric layers are subsequently formed. The various contact via holes are vertically extended by simultaneously etching exposed gate cap dielectrics and exposed portions of the first contact-level dielectric layer, then by simultaneously etching the first and second etch stop layers. Source/drain contact vias self-aligned to the outer surfaces gate spacers are thereby formed. | 07-04-2013 |
20130168806 | ELECTRICAL FUSE STRUCTURE AND METHOD OF FABRICATING SAME - A high programming efficiency electrical fuse is provided utilizing a dual damascene structure located atop a metal layer. The dual damascene structure includes a patterned dielectric material having a line opening located above and connected to an underlying via opening. The via opening is located atop and is connected to the metal layer. The dual damascene structure also includes a conductive feature within the line opening and the via opening. Dielectric spacers are also present within the line opening and the via opening. The dielectric spacers are present on vertical sidewalls of the patterned dielectric material and separate the conductive feature from the patterned dielectric material. The presence of the dielectric spacers within the line opening and the via opening reduces the area in which the conductive feature is formed. As such, a high programming efficiency electrical fuse is provided in which space is saved. | 07-04-2013 |
20130175619 | SILICON-ON-INSULATOR TRANSISTOR WITH SELF-ALIGNED BORDERLESS SOURCE/DRAIN CONTACTS - A transistor includes a semiconductor layer, a gate spacer on the semiconductor layer, a gate dielectric comprising a first portion above the semiconductor layer and a second portion on sidewalls of the gate spacer, a work function metal layer comprising a first portion on the first portion of the gate dielectric and a second portion on sidewalls of the gate dielectric, a gate conductor on the first portion of the work function layer and abutting the second portion of the work function layer, a dielectric layer on the semiconductor layer and abutting the gate spacer, an oxide film above only one of the work function layer and the gate conductor, an oxide cap, source/drain regions, and a source/drain contact passing through the dielectric layer and contacting an upper surface of one of the source/drain regions. A portion of the source/drain contact is located directly on the oxide cap. | 07-11-2013 |
20130175622 | ELECTRICAL ISOLATION STRUCTURES FOR ULTRA-THIN SEMICONDUCTOR-ON-INSULATOR DEVICES - After formation of raised source and drain regions, a conformal dielectric material liner is deposited within recessed regions formed by removal of shallow trench isolation structures and underlying portions of a buried insulator layer in a semiconductor-on-insulator (SOI) substrate. A dielectric material that is different from the material of the conformal dielectric material liner is subsequently deposited and planarized to form a planarized dielectric material layer. The planarized dielectric material layer is recessed selective to the conformal dielectric material liner to form dielectric fill portions that fill the recessed regions. Horizontal portions of the conformal dielectric material liner are removed by an anisotropic etch, while remaining portions of the conformal dielectric material liner form an outer gate spacer. At least one contact-level dielectric layer is deposited. Contact via structures electrically isolated from a handle substrate can be formed within the contact via holes. | 07-11-2013 |
20130178052 | METHOD FOR FABRICATING SILICON-ON-INSULATOR TRANSISTOR WITH SELF-ALIGNED BORDERLESS SOURCE/DRAIN CONTACTS - A method is provided for fabricating a transistor. A replacement gate stack is formed on a semiconductor layer, a gate spacer is formed, and a dielectric layer is formed. The dummy gate stack is removed to form a cavity. A gate dielectric and a work function metal layer are formed in the cavity. The cavity is filled with a gate conductor. One and only one of the gate conductor and the work function metal layer are selectively recessed. An oxide film is formed in the recess such that its upper surface is co-planar with the upper surface of the dielectric layer. The oxide film is used to selectively grow an oxide cap. An interlayer dielectric is formed and etched to form a cavity for a source/drain contact. A source/drain contact is formed in the contact cavity, with a portion of the source/drain contact being located directly on the oxide cap. | 07-11-2013 |
20130181261 | BORDERLESS CONTACT STRUCTURE - A borderless contact structure or partially borderless contact structure and methods of manufacture are disclosed. The method includes forming a gate structure and a space within the gate structure, defined by spacers. The method further includes blanket depositing a sealing material in the space, over the gate structure and on a semiconductor material. The method further includes removing the sealing material from over the gate structure and on the semiconductor material, leaving the sealing material within the space. The method further includes forming an interlevel dielectric material over the gate structure. The method further includes patterning the interlevel dielectric material to form an opening exposing the semiconductor material and a portion of the gate structure. The method further includes forming a contact in the opening formed in the interlevel dielectric material. | 07-18-2013 |
20130187203 | FORMATION OF THE DIELECTRIC CAP LAYER FOR A REPLACEMENT GATE STRUCTURE - Gate to contact shorts are reduced by forming dielectric caps in replaced gate structures. Embodiments include forming a replaced gate structure on a substrate, the replaced gate structure including an ILD having a cavity, a first metal on a top surface of the ILD and lining the cavity, and a second metal on the first metal and filling the cavity, planarizing the first and second metals, forming an oxide on the second metal, removing the oxide, recessing the first and second metals in the cavity, forming a recess, and filling the recess with a dielectric material. Embodiments further include dielectric caps having vertical sidewalls, a trapezoidal shape, a T-shape, or a Y-shape. | 07-25-2013 |
20130207270 | DUAL-METAL SELF-ALIGNED WIRES AND VIAS - Method of forming a semiconductor structure which includes forming first conductive spacers on a semiconductor substrate; forming second conductive spacers with respect to the first conductive spacers, at least one of the second conductive spacers adjacent to and in contact with each of the first conductive spacers to form combined conductive spacers; recessing the second conductive spacers with respect to the first conductive spacers so that the first conductive spacers extend beyond the second conductive spacers; depositing an ILD to cover the first and second spacers except for an exposed edge of the first conductive spacers; patterning the exposed edges of the first conductive spacers to recess the edges of the first conductive spacers in predetermined locations to form recesses with respect to the ILD; and filling the recesses with an insulating material to leave unrecessed edges of the first conductive spacers as vias to subsequent wiring features. | 08-15-2013 |
20130216776 | DUAL HARD MASK LITHOGRAPHY PROCESS - A first metallic hard mask layer over an interconnect-level dielectric layer is patterned with a line pattern. At least one dielectric material layer, a second metallic hard mask layer, a first organic planarization layer (OPL), and a first photoresist are applied above the first metallic hard mask layer. A first via pattern is transferred from the first photoresist layer into the second metallic hard mask layer. A second OPL and a second photoresist are applied and patterned with a second via pattern, which is transferred into the second metallic hard mask layer. A first composite pattern of the first and second via patterns is transferred into the at least one dielectric material layer. A second composite pattern that limits the first composite pattern with the areas of the openings in the first metallic hard mask layer is transferred into the interconnect-level dielectric layer. | 08-22-2013 |
20130307033 | Borderless Contact For An Aluminum-Containing Gate - An aluminum-containing material is employed to form replacement gate electrodes. A contact-level dielectric material layer is formed above a planarization dielectric layer in which the replacement gate electrodes are embedded. At least one contact via cavity is formed through the contact-level dielectric layer. Any portion of the replacement gate electrodes that is physically exposed at a bottom of the at least one contact via cavity is vertically recessed. Physically exposed portions of the aluminum-containing material within the replacement gate electrodes are oxidized to form dielectric aluminum compound portions. Subsequently, each of the at least one active via cavity is further extended to an underlying active region, which can be a source region or a drain region. A contact via structure formed within each of the at least one active via cavity can be electrically isolated from the replacement gate electrodes by the dielectric aluminum compound portions. | 11-21-2013 |
20130307086 | MASK FREE PROTECTION OF WORK FUNCTION MATERIAL PORTIONS IN WIDE REPLACEMENT GATE ELECTRODES - In a replacement gate scheme, after formation of a gate dielectric layer, a work function material layer completely fills a narrow gate trench, while not filling a wide gate trench. A dielectric material layer is deposited and planarized over the work function material layer, and is subsequently recessed to form a dielectric material portion overlying a horizontal portion of the work function material layer within the wide gate trench. The work function material layer is recessed employing the dielectric material portion as a part of an etch mask to form work function material portions. A conductive material is deposited and planarized to form gate conductor portions, and a dielectric material is deposited and planarized to form gate cap dielectrics. | 11-21-2013 |
20130309852 | BORDERLESS CONTACT FOR AN ALUMINUM-CONTAINING GATE - An aluminum-containing material is employed to form replacement gate electrodes. A contact-level dielectric material layer is formed above a planarization dielectric layer in which the replacement gate electrodes are embedded. At least one contact via cavity is formed through the contact-level dielectric layer. Any portion of the replacement gate electrodes that is physically exposed at a bottom of the at least one contact via cavity is vertically recessed. Physically exposed portions of the aluminum-containing material within the replacement gate electrodes are oxidized to form dielectric aluminum compound portions. Subsequently, each of the at least one active via cavity is further extended to an underlying active region, which can be a source region or a drain region. A contact via structure formed within each of the at least one active via cavity can be electrically isolated from the replacement gate electrodes by the dielectric aluminum compound portions. | 11-21-2013 |
20130309857 | MASK FREE PROTECTION OF WORK FUNCTION MATERIAL PORTIONS IN WIDE REPLACEMENT GATE ELECTRODES - In a replacement gate scheme, after formation of a gate dielectric layer, a work function material layer completely fills a narrow gate trench, while not filling a wide gate trench. A dielectric material layer is deposited and planarized over the work function material layer, and is subsequently recessed to form a dielectric material portion overlying a horizontal portion of the work function material layer within the wide gate trench. The work function material layer is recessed employing the dielectric material portion as a part of an etch mask to form work function material portions. A conductive material is deposited and planarized to form gate conductor portions, and a dielectric material is deposited and planarized to form gate cap dielectrics. | 11-21-2013 |
20130313717 | SPACER FOR ENHANCING VIA PATTERN OVERLAY TOLERENCE - After formation of line openings in a hard mask layer, hard mask level spacers are formed on sidewalls of the hard mask layer. A photoresist is applied and patterned to form a via pattern including a via opening. The overlay tolerance for printing the via pattern is increased by the lateral thickness of the hard mask level spacers. A portion of a dielectric material layer is patterned to form a via cavity pattern by an etch that employs the hard mask layer and the hard mask level spacers as etch masks. The hard mask level spacers are subsequently removed, and the pattern of the line is subsequently transferred into an upper portion of the dielectric material layer, while the via cavity pattern is transferred to a lower portion of the dielectric material layer. | 11-28-2013 |
20130320411 | BORDERLESS CONTACTS FOR METAL GATES THROUGH SELECTIVE CAP DEPOSITION - A semiconductor device including a gate structure present on a channel portion of a substrate, in which the gate structure includes at least one high-k gate dielectric layer and at least one metal gate conductor. A source region and a drain region is present on opposing sides of the channel portion of the substrate. A metal oxide gate cap is present on an upper surface of the metal gate conductor. The metal oxide composition of the metal oxide gate cap may be zirconium oxide, aluminum oxide, magnesium oxide, hafnium oxide or a combination thereof. Contacts may extend through an intralevel dielectric layer into contact with at least one of the source region and the drain region. | 12-05-2013 |
20130320414 | BORDERLESS CONTACTS FOR METAL GATES THROUGH SELECTIVE CAP DEPOSITION - A semiconductor device including a gate structure present on a channel portion of a substrate, in which the gate structure includes at least one high-k gate dielectric layer and at least one metal gate conductor. A source region and a drain region is present on opposing sides of the channel portion of the substrate. A metal oxide gate cap is present on an upper surface of the metal gate conductor. The metal oxide composition of the metal oxide gate cap may be zirconium oxide, aluminum oxide, magnesium oxide, hafnium oxide or a combination thereof. Contacts may extend through an intralevel dielectric layer into contact with at least one of the source region and the drain region. | 12-05-2013 |
20130320545 | HYBRID COPPER INTERCONNECT STRUCTURE AND METHOD OF FABRICATING SAME - A hybrid interconnect structure containing copper regions that have different impurities levels within a same opening is provided. In one embodiment, the interconnect structure includes a patterned dielectric material having at least one opening located therein. A dual material liner is located at least on sidewalls of the patterned dielectric material within the at least one opening. The structure further includes a first copper region having a first impurity level located within a bottom region of the at least one opening and a second copper region having a second impurity level located within a top region of the at least one opening and atop the first copper region. In accordance with the present disclosure, the first impurity level of the first copper region is different from the second impurity level of the second copper region. | 12-05-2013 |
20130320546 | DUAL-METAL SELF-ALIGNED WIRES AND VIAS - Disclosed is a semiconductor structure which includes a semiconductor substrate and a wiring layer on the semiconductor substrate. The wiring layer includes a plurality of fin-like structures comprising a first metal; a first layer of a second metal on each of the plurality of fin-like structures wherein the first metal is different from the second metal, the first layer of the second metal having a height less than each of the plurality of fin-like structures; and an interlayer dielectric (ILD) covering the plurality of fin-like structures and the first layer of the second metal except for exposed edges of the plurality of fin-like structures at predetermined locations, and at locations other than the predetermined locations, the height of the plurality of fin-like structures has been reduced so as to be covered by the ILD. | 12-05-2013 |
20130328111 | RECESSING AND CAPPING OF GATE STRUCTURES WITH VARYING METAL COMPOSITIONS - A method for recessing and capping metal gate structures is disclosed. Embodiments include: forming a dummy gate electrode on a substrate; forming a hard mask over the dummy gate electrode; forming spacers on opposite sides of the dummy gate electrode and the hard mask; forming an interlayer dielectric (ILD) over the substrate adjacent the spacers; forming a first trench in the ILD down to the dummy gate electrode; removing the dummy gate electrode to form a second trench below the first trench; forming a metal gate structure in the first and second trenches; and forming a gate cap over the metal gate structure. | 12-12-2013 |
20130328208 | DUAL DAMASCENE DUAL ALIGNMENT INTERCONNECT SCHEME - A stack of a first metal line and a first dielectric cap material portion is formed within a line trench of first dielectric material layer. A second dielectric material layer is formed thereafter. A line trench extending between the top surface and the bottom surface of the second dielectric material layer is patterned. A photoresist layer is applied over the second dielectric material layer and patterned with a via pattern. An underlying portion of the first dielectric cap material is removed by an etch selective to the dielectric materials of the first and second dielectric material layer to form a via cavity that is laterally confined along the widthwise direction of the line trench and along the widthwise direction of the first metal line. A dual damascene line and via structure is formed, which includes a via structure that is laterally confined along two independent horizontal directions. | 12-12-2013 |
20140027917 | NON-LITHOGRAPHIC LINE PATTERN FORMATION - A metal layer is deposited over an underlying material layer. The metal layer includes an elemental metal that can be converted into a dielectric metal-containing compound by plasma oxidation and/or nitridation. A hard mask portion is formed over the metal layer. Plasma oxidation or nitridation is performed to convert physically exposed surfaces of the metal layer into the dielectric metal-containing compound. The sequence of a surface pull back of the hard mask portion, trench etching, another surface pull back, and conversion of top surfaces into the dielectric metal-containing compound are repeated to form a line pattern having a spacing that is not limited by lithographic minimum dimensions. | 01-30-2014 |
20140027923 | NON-LITHOGRAPHIC HOLE PATTERN FORMATION - A metal layer is deposited over a material layer. The metal layer includes an elemental metal that can be converted into a dielectric metal-containing compound by plasma oxidation or nitridation. A hard mask portion is formed over the metal layer. A plasma impermeable spacer is formed on at least one first sidewall of the hard mask portion, while at least one second sidewall of the hard mask portion is physically exposed. Plasma oxidation or nitridation is performed to convert physically exposed surfaces of the metal layer into the dielectric metal-containing compound. A sequence of a surface pull back of the hard mask portion, cavity etching, another surface pull back, and conversion of top surfaces into the dielectric metal-containing compound are repeated to form a hole pattern having a spacing that is not limited by lithographic minimum dimensions. | 01-30-2014 |
20140035142 | PROFILE CONTROL IN INTERCONNECT STRUCTURES - The profile of a via can be controlled by forming a profile control liner within each via opening that is formed into a dielectric material prior to forming a line opening within the dielectric material. The presence of the profile control liner within each via opening during the formation of the line opening prevents rounding of the corners of a dielectric material portion that is present beneath the line opening and adjacent the via opening. | 02-06-2014 |
20140061799 | SILICON-ON-INSULATOR TRANSISTOR WITH SELF-ALIGNED BORDERLESS SOURCE/DRAIN CONTACTS - A method is provided for fabricating an integrated circuit that includes multiple transistors. A replacement gate stack is formed on a semiconductor layer, a gate spacer is formed, and a dielectric layer is formed. The dummy gate stack is removed to form a cavity. A gate dielectric and a work function metal layer are formed in the cavity. The cavity is filled with a gate conductor. One and only one of the gate conductor and the work function metal layer are selectively recessed. An oxide film is formed in the recess such that its upper surface is co-planar with the upper surface of the dielectric layer. The oxide film is used to selectively grow an oxide cap. An interlayer dielectric is formed and etched to form a cavity for a source/drain contact. A source/drain contact is formed in the contact cavity, with a portion of the source/drain contact being located directly on the oxide cap. | 03-06-2014 |
20140061800 | ELECTRICAL ISOLATION STRUCTURES FOR ULTRA-THIN SEMICONDUCTOR-ON-INSULATOR DEVICES - After formation of raised source and drain regions, a conformal dielectric material liner is deposited within recessed regions formed by removal of shallow trench isolation structures and underlying portions of a buried insulator layer in a semiconductor-on-insulator (SOI) substrate. A dielectric material that is different from the material of the conformal dielectric material liner is subsequently deposited and planarized to form a planarized dielectric material layer. The planarized dielectric material layer is recessed selective to the conformal dielectric material liner to form dielectric fill portions that fill the recessed regions. Horizontal portions of the conformal dielectric material liner are removed by an anisotropic etch, while remaining portions of the conformal dielectric material liner form an outer gate spacer. At least one contact-level dielectric layer is deposited. Contact via structures electrically isolated from a handle substrate can be formed within the contact via holes. | 03-06-2014 |
20140061930 | OVERLAY-TOLERANT VIA MASK AND REACTIVE ION ETCH (RIE) TECHNIQUE - A method is provided that includes first etching a substrate according to a first mask. The first etching forms a first etch feature in the substrate to a first depth. The first etching also forms a sliver opening in the substrate. The sliver opening may then be filled with a fill material. A second mask may be formed by removing a portion of the first mask. The substrate exposed by the second mask may be etched with a second etch, in which the second etching is selective to the fill material. The second etching extends the first etch feature to a second depth that is greater than the first depth, and the second etch forms a second etch feature. The first etch feature and the second etch feature may then be filled with a conductive metal. | 03-06-2014 |
20140065813 | SIZE-FILTERED MULTIMETAL STRUCTURES - A size-filtered metal interconnect structure allows formation of metal structures having different compositions. Trenches having different widths are formed in a dielectric material layer. A blocking material layer is conformally deposited to completely fill trenches having a width less than a threshold width. An isotropic etch is performed to remove the blocking material layer in wide trenches, i.e., trenches having a width greater than the threshold width, while narrow trenches, i.e., trenches having a width less than the threshold width, remain plugged with remaining portions of the blocking material layer. The wide trenches are filled and planarized with a first metal to form first metal structures having a width greater than the critical width. The remaining portions of the blocking material layer are removed to form cavities, which are filled with a second metal to form second metal structures having a width less than the critical width. | 03-06-2014 |
20140068541 | INTERCONNECT STRUCTURES AND METHODS FOR BACK END OF THE LINE INTEGRATION - A method of forming a semiconductor structure includes forming a sacrificial conductive material layer. The method also includes forming a trench in the sacrificial conductive material layer. The method further includes forming a conductive feature in the trench. The method additionally includes removing the sacrificial conductive material layer selective to the conductive feature. The method also includes forming an insulating layer around the conductive feature to embed the conductive feature in the insulating layer. | 03-06-2014 |
20140070282 | SELF-ALIGNED CONTACTS - Self-aligned contacts in a metal gate structure and methods of manufacture are disclosed herein. The method includes forming a metal gate structure having a sidewall structure. The method further includes recessing the metal gate structure and forming a masking material within the recess. The method further includes forming a borderless contact adjacent to the metal gate structure, overlapping the masking material and the sidewall structure. | 03-13-2014 |
20140077276 | MIDDLE-OF-LINE BORDERLESS CONTACT STRUCTURE AND METHOD OF FORMING - Various embodiments disclosed include semiconductor structures and methods of forming such structures. In one embodiment, a method includes: providing a semiconductor structure including: a substrate; at least one gate structure overlying the substrate; and an interlayer dielectric overlying the substrate and the at least one gate structure; removing the ILD overlying the substrate to expose the substrate; forming a silicide layer over the substrate; forming a conductor over the silicide layer and the at least one gate structure; forming an opening in the conductor to expose a portion of a gate region of the at least one gate structure; and forming a dielectric in the opening in the conductor. | 03-20-2014 |
20140110817 | SUB-LITHOGRAPHIC SEMICONDUCTOR STRUCTURES WITH NON-CONSTANT PITCH - Fin structures and methods of manufacturing fin structures using a dual-material sidewall image transfer mask to enable patterning of sub-lithographic features is disclosed. The method of forming a plurality of fins includes forming a first set of fins having a first pitch. The method further includes forming an adjacent fin to the first set of fins. The adjacent fin and a nearest fin of the first set of fins have a second pitch larger than the first pitch. The first set of fins and the adjacent fin are sub-lithographic features formed using a sidewall image transfer process. | 04-24-2014 |
20140110846 | DUAL HARD MASK LITHOGRAPHY PROCESS - A first metallic hard mask layer over an interconnect-level dielectric layer is patterned with a line pattern. At least one dielectric material layer, a second metallic hard mask layer, a first organic planarization layer (OPL), and a first photoresist are applied above the first metallic hard mask layer. A first via pattern is transferred from the first photoresist layer into the second metallic hard mask layer. A second OPL and a second photoresist are applied and patterned with a second via pattern, which is transferred into the second metallic hard mask layer. A first composite pattern of the first and second via patterns is transferred into the at least one dielectric material layer. A second composite pattern that limits the first composite pattern with the areas of the openings in the first metallic hard mask layer is transferred into the interconnect-level dielectric layer. | 04-24-2014 |
20140124933 | COPPER INTERCONNECT STRUCTURES AND METHODS OF MAKING SAME - A structure and method of making the structure. The structure includes a dielectric layer on a substrate; a first wire formed in a first trench in the dielectric layer, a first liner on sidewalls and a bottom of the first trench and a first copper layer filling all remaining space in the first trench; a second wire formed in a second trench in the dielectric layer, a second liner on sidewalls and a bottom of the second trench and a second copper layer filling all remaining space in the second trench; and an electromigration stop formed in a third trench in the dielectric layer, a third liner on sidewalls and a bottom of the third trench and a third copper layer filling all remaining space in the third trench, the electromigration stop between and abutting respective ends of the first and second wires. | 05-08-2014 |
20140159169 | RECESSING AND CAPPING OF GATE STRUCTURES WITH VARYING METAL COMPOSITIONS - A approach for recessing and capping metal gate structures is disclosed. Embodiments include: forming a dummy gate electrode on a substrate; forming a hard mask over the dummy gate electrode; forming spacers on opposite sides of the dummy gate electrode and the hard mask; forming an interlayer dielectric (ILD) over the substrate adjacent the spacers; forming a first trench in the ILD down to the dummy gate electrode; removing the dummy gate electrode to form a second trench below the first trench; forming a metal gate structure in the first and second trenches; and forming a gate cap over the metal gate structure. | 06-12-2014 |
20140190935 | DUAL MANDREL SIDEWALL IMAGE TRANSFER PROCESSES - A combination of two lithographically patterned mandrels can be employed in conjunction with sidewall spacers to provide two spacers. The two spacers may intersect each other and/or contact sidewall surfaces of each other to provide a thickness that is a sum of the thicknesses of the two spacers. Further, the two spacers may be patterned to provide various patterns. In addition, portions of at least one of the two spacers may be etched employing an etch mask. Additionally or alternately, an additional material may be selectively added to portions of one of the two spacers. | 07-10-2014 |
20140203453 | AIR-DIELECTRIC FOR SUBTRACTIVE ETCH LINE AND VIA METALLIZATION - A method and structure is disclosed whereby multiple interconnect layers having effective air gaps positioned in regions most susceptible to capacitive coupling can be formed. The method includes providing a layer of conductive features, the layer including at least two line members disposed on a substrate and spaced from one another by less than or equal to an effective distance, and at least one such line member also having a via member extending away from the substrate, depositing a poorly conformal dielectric coating to form an air gap between such line members, and exposing a top end of the via. | 07-24-2014 |
20140231918 | FINFETS AND FIN ISOLATION STRUCTURES - FinFETs and fin isolation structures and methods of manufacturing the same are disclosed. The method includes patterning a bulk substrate to form a plurality of fin structures of a first dimension and of a second dimension. The method includes forming oxide material in spaces between the plurality of fin structures of the first dimension and the second dimension. The method includes forming a capping material over sidewalls of selected ones of the fin structures of the first dimension and the second dimension. The method includes recessing the oxide material to expose the bulk substrate on sidewalls below the capping material. The method includes performing an oxidation process to form silicon on insulation fin structures and bulk fin structures with gating. The method further includes forming a gate structure over the SOI fin structures and the bulk fin structures. | 08-21-2014 |
20140264490 | REPLACEMENT GATE ELECTRODE WITH A SELF-ALIGNED DIELECTRIC SPACER - A dielectric disposable gate structure can be formed across a semiconductor material portion, and active semiconductor regions are formed within the semiconductor material portion. Raised active semiconductor regions are grown over the active semiconductor regions while the dielectric disposable gate structure limits the extent of the raised active semiconductor regions. A planarization dielectric layer is formed over the raised active semiconductor regions. In one embodiment, the dielectric disposable gate structure is removed, and a dielectric gate spacer can be formed by conversion of surface portions of the raised active semiconductor regions around a gate cavity. Alternately, an etch mask layer overlying peripheral portions of the disposable gate structure can be formed, and a gate cavity and a dielectric spacer can be formed by anisotropically etching an unmasked portion of the dielectric disposable gate structure. A replacement gate structure can be formed in the gate cavity. | 09-18-2014 |
20140264878 | COPPER INTERCONNECT STRUCTURES AND METHODS OF MAKING SAME - A structure and method of making the structure. The structure includes a dielectric layer on a substrate; a first wire formed in a first trench in the dielectric layer, a first liner on sidewalls and a bottom of the first trench and a first copper layer filling all remaining space in the first trench; a second wire formed in a second trench in the dielectric layer, a second liner on sidewalls and a bottom of the second trench and a second copper layer filling all remaining space in the second trench; and an electromigration stop formed in a third trench in the dielectric layer, a third liner on sidewalls and a bottom of the third trench and a third copper layer filling all remaining space in the third trench, the electromigration stop between and abutting respective ends of the first and second wires. | 09-18-2014 |
20140299924 | FORMATION OF THE DIELECTRIC CAP LAYER FOR A REPLACEMENT GATE STRUCTURE - Gate to contact shorts are reduced by forming dielectric caps in replaced gate structures. Embodiments include forming a replaced gate structure on a substrate, the replaced gate structure including an ILD having a cavity, a first metal on a top surface of the ILD and lining the cavity, and a second metal on the first metal and filling the cavity, planarizing the first and second metals, forming an oxide on the second metal, removing the oxide, recessing the first and second metals in the cavity, forming a recess, and filling the recess with a dielectric material. Embodiments further include dielectric caps having vertical sidewalls, a trapezoidal shape, a T-shape, or a Y-shape. | 10-09-2014 |
20140339629 | CONTACT FORMATION FOR ULTRA-SCALED DEVICES - Embodiments of the invention provide approaches for forming gate and source/drain (S/D) contacts. Specifically, the semiconductor device includes a gate transistor formed over a substrate, a S/D contact formed over a trench-silicide (TS) layer and positioned adjacent the gate transistor, and a gate contact formed over the gate transistor, wherein at least a portion of the gate contact is aligned over the TS layer. This structure enables contact with the TS layer, thereby decreasing the distance between the gate contact and the source/drain, which is desirable for ultra-area-scaling. | 11-20-2014 |
20140342549 | DUAL DAMASCENE DUAL ALIGNMENT INTERCONNECT SCHEME - A stack of a first metal line and a first dielectric cap material portion is formed within a line trench of first dielectric material layer. A second dielectric material layer is formed thereafter. A line trench extending between the top surface and the bottom surface of the second dielectric material layer is patterned. A photoresist layer is applied over the second dielectric material layer and patterned with a via pattern. An underlying portion of the first dielectric cap material is removed by an etch selective to the dielectric materials of the first and second dielectric material layer to form a via cavity that is laterally confined along the widthwise direction of the line trench and along the widthwise direction of the first metal line. A dual damascene line and via structure is formed, which includes a via structure that is laterally confined along two independent horizontal directions. | 11-20-2014 |
20140346640 | NON-LITHOGRAPHIC HOLE PATTERN FORMATION - A metal layer is deposited over a material layer. The metal layer includes an elemental metal that can be converted into a dielectric metal-containing compound by plasma oxidation or nitridation. A hard mask portion is formed over the metal layer. A plasma impermeable spacer is formed on at least one first sidewall of the hard mask portion, while at least one second sidewall of the hard mask portion is physically exposed. Plasma oxidation or nitridation is performed to convert physically exposed surfaces of the metal layer into the dielectric metal-containing compound. A sequence of a surface pull back of the hard mask portion, cavity etching, another surface pull back, and conversion of top surfaces into the dielectric metal-containing compound are repeated to form a hole pattern having a spacing that is not limited by lithographic minimum dimensions. | 11-27-2014 |
20140349088 | NON-LITHOGRAPHIC LINE PATTERN FORMATION - A metal layer is deposited over an underlying material layer. The metal layer includes an elemental metal that can be converted into a dielectric metal-containing compound by plasma oxidation and/or nitridation. A hard mask portion is formed over the metal layer. Plasma oxidation or nitridation is performed to convert physically exposed surfaces of the metal layer into the dielectric metal-containing compound. The sequence of a surface pull back of the hard mask portion, trench etching, another surface pull back, and conversion of top surfaces into the dielectric metal-containing compound are repeated to form a line pattern having a spacing that is not limited by lithographic minimum dimensions. | 11-27-2014 |
20140363941 | REPLACEMENT GATE ELECTRODE WITH A SELF-ALIGNED DIELECTRIC SPACER - A dielectric disposable gate structure can be formed across a semiconductor material portion, and active semiconductor regions are formed within the semiconductor material portion. Raised active semiconductor regions are grown over the active semiconductor regions while the dielectric disposable gate structure limits the extent of the raised active semiconductor regions. A planarization dielectric layer is formed over the raised active semiconductor regions. In one embodiment, the dielectric disposable gate structure is removed, and a dielectric gate spacer can be formed by conversion of surface portions of the raised active semiconductor regions around a gate cavity. Alternately, an etch mask layer overlying peripheral portions of the disposable gate structure can be formed, and a gate cavity and a dielectric spacer can be formed by anisotropically etching an unmasked portion of the dielectric disposable gate structure. A replacement gate structure can be formed in the gate cavity. | 12-11-2014 |
20150035026 | MIDDLE-OF-LINE BORDERLESS CONTACT STRUCTURE AND METHOD OF FORMING - Various embodiments disclosed include semiconductor structures and methods of forming such structures. In one embodiment, a method includes: providing a semiconductor structure including: a substrate; at least one gate structure overlying the substrate; and an interlayer dielectric overlying the substrate and the at least one gate structure; removing the ILD overlying the substrate to expose the substrate; forming a silicide layer over the substrate; forming a conductor over the silicide layer and the at least one gate structure; forming an opening in the conductor to expose a portion of a gate region of the at least one gate structure; and forming a dielectric in the opening in the conductor. | 02-05-2015 |
20150035154 | PROFILE CONTROL IN INTERCONNECT STRUCTURES - The profile of a via can be controlled by forming a profile control liner within each via opening that is formed into a dielectric material prior to forming a line opening within the dielectric material. The presence of the profile control liner within each via opening during the formation of the line opening prevents rounding of the corners of a dielectric material portion that is present beneath the line opening and adjacent the via opening. | 02-05-2015 |
20150035157 | SPACER FOR ENHANCING VIA PATTERN OVERLAY TOLERENCE - After formation of line openings in a hard mask layer, hard mask level spacers are formed on sidewalls of the hard mask layer. A photoresist is applied and patterned to form a via pattern including a via opening. The overlay tolerance for printing the via pattern is increased by the lateral thickness of the hard mask level spacers. A portion of a dielectric material layer is patterned to form a via cavity pattern by an etch that employs the hard mask layer and the hard mask level spacers as etch masks. The hard mask level spacers are subsequently removed , and the pattern of the line is subsequently transferred into an upper portion of the dielectric material layer, while the via cavity pattern is transferred to a lower portion of the dielectric material layer. | 02-05-2015 |