Patent application number | Description | Published |
20090106616 | Integrated circuit using speculative execution - An integrated circuit | 04-23-2009 |
20090161442 | Data Processing System - A data processing system comprising a memory array having a plurality of memory cells ( | 06-25-2009 |
20100064287 | Scheduling control within a data processing system - A processor | 03-11-2010 |
20100235697 | Error detection in precharged logic - An integrated circuit | 09-16-2010 |
20100299557 | Providing tuning limits for operational parameters in data processing apparatus - The application discloses a means of setting tuning limits for operational parameters in a processing stage within a data processing apparatus for processing a signal. The processing stage comprises: an input for receiving the signal, processing circuitry for processing the signal and an output for outputting the processed signal at an output time; an error detecting circuit for determining if a signal output by the processing stage between the output time and a predetermined time later does not have a stable value, the predetermined time later being before a next output time, and for signaling an error if the signal is not stable; a tuning circuit for adjusting at least one operational parameter of the processing stage; a tuning limiting circuit for providing at least one tuning limit for the tuning circuit, such that the at least one operational parameter is not adjusted beyond the corresponding at least one tuning limit, a tuning limiting circuit for providing at least one tuning limit for said tuning circuit, such that said at least one operational parameter is not adjusted beyond said corresponding at least one tuning limit, the tuning limiting circuit being configured to provide the at least one tuning limit such that a signal passing along a critical path of the processing stage tuned to the tuning limit is estimated to reach the output of the processing stage at a preset time later than the output time, the preset time being less than the predetermined time. | 11-25-2010 |
20110246843 | ERROR DETECTION IN PRECHARGED LOGIC - An integrated circuit is provided with domino logic including a speculative node and a checker node. Precharged circuitry precharges both the speculative node and the checker node. Logic circuitry provides a discharge path for the speculative node and the checker node in dependence upon input signal values. Evaluation control circuitry first couples the speculative node to the logic circuitry and then subsequently couples the checker node to the logic circuitry such that these can be discharged if the input signals to the logic circuitry have appropriate values. Error detection circuitry detects an error when the speculative node and the checker node are not one of both discharged or both undischarged. | 10-06-2011 |
20120124421 | Error management within a data processing system - A data processing system | 05-17-2012 |
20130151891 | LIMITING CERTAIN PROCESSING ACTIVITIES AS ERROR RATE PROBABILITY RISES - A data processing apparatus configured to operate in a voltage and frequency operating region that is located beyond a safe region where errors do not arise, but within operating region limits such that the errors are rare. The data processing apparatus comprises: error detection circuitry and error recovery circuitry; the error detection circuitry being configured to determine if a signal sampled in the processing apparatus changes within a time window occurring after the signal has been sampled and during a same clock cycle as the sampling and to signal an error if the signal does change. The data processing apparatus further comprises performance control circuitry configured to determine when the data processing apparatus is operating close to the operating region limits where an error rate is raised and in response to determining operation close to the operating region limits to modify a behaviour of the data processing apparatus by at least one of: limiting speculative processing, and selecting timing insensitive processing paths and circuitry. | 06-13-2013 |
20130166952 | DATA PROCESSING APPARATUS WITH AN EXECUTION PIPELINE AND ERROR RECOVERY UNIT AND METHOD OF OPERATING THE DATA PROCESSING APPARATUS - A data processing apparatus executes instructions in a sequence of pipelined execution stages. An error detection unit twice samples a signal associated with execution of an instruction and generates an error signal if the samples differ. An exception storage unit maintains an age-ordered list of entries corresponding to instructions issued to the execution pipeline and can mark an entry to show if the error signal has been generated in association with that instruction. A timer unit is responsive to generation of the error signal to initiate timing of a predetermined time period. An error recovery unit initiates a soft pipeline flush procedure if an oldest pending entry in the list has said error marker stored in association therewith and initiates a hard pipeline flush procedure if said predetermined time period elapses, said hard flush procedure comprising resetting said pipeline to a predetermined state. | 06-27-2013 |
20130166980 | ERROR RECOVERY IN A DATA PROCESSING APPARATUS - A data processing apparatus has error detection units each configured to generate an error signal if a first and second sample of a signal associated with execution of an instruction differ. Error value generation circuitry generates an error value showing if any of the error detection units have generated the error signal. Error value stabilisation circuitry performs a stabilisation procedure comprising re-sampling the error value to remove metastability. Error recovery circuitry initiates re-execution of the instruction if the error value is asserted. Count circuitry holds a counter value in association with the error value, the counter value set to a predetermined value when the error value is generated and decremented each time the error value is re-sampled prior to reaching the error value stabilisation circuitry. The error value bypasses the stabilisation procedure if the counter value is zero before the error value reaches the error value stabilisation circuitry. | 06-27-2013 |
20140068371 | INTEGRATED CIRCUIT WITH ERROR REPAIR AND FAULT TOLERANCE - An integrated circuit is provided with error detection circuitry and error repair circuitry. Error tolerance circuitry is responsive to a control parameter to selectively disable the error repair circuitry. The control parameter is dependent on the processing performed within the circuit. For example, the control parameter may be generated in dependence upon the program instruction being executed, the output signal value which is in error, the previous behavior of the circuit or in other ways. | 03-06-2014 |
20140115376 | INTEGRATED CIRCUIT WITH ERROR REPAIR AND FAULT TOLERANCE - An integrated circuit is provided with error detection circuitry and error repair circuitry. Error tolerance circuitry is responsive to a control parameter to selectively disable the error repair circuitry. The control parameter is dependent on the processing performed within the circuit. For example, the control parameter may be generated in dependence upon the program instruction being executed, the output signal value which is in error, the previous behavior of the circuit or in other ways. | 04-24-2014 |
20140115377 | INTEGRATED CIRCUIT WITH ERROR REPAIR AND FAULT TOLERANCE - An integrated circuit is provided with error detection circuitry and error repair circuitry. Error tolerance circuitry is responsive to a control parameter to selectively disable the error repair circuitry. The control parameter is dependent on the processing performed within the circuit. For example, the control parameter may be generated in dependence upon the program instruction being executed, the output signal value which is in error, the previous behavior of the circuit or in other ways. | 04-24-2014 |