| Patent application number | Description | Published |
|---|
| 20090189653 | Phase Lock Loop Clock Distribution Method and System - A method and apparatus and program use the quiet, regulated power supply inherent to the PLL to drive a CMOS buffer. In this manner, the CMOS buffer may distribute the reference clock in a manner that minimizes the power and space consumption associated with clock distribution processes. | 07-30-2009 |
| 20100001804 | SYSTEM TO IMPROVE A VOLTAGE-CONTROLLED OSCILLATOR AND ASSOCIATED METHODS - A system to improve a voltage-controlled oscillator may include a voltage-controlled oscillator. The system may also include a switch to control a first voltage passing through the voltage-controlled oscillator based upon a digital tune bit used to control the voltage-controlled oscillator's gain. | 01-07-2010 |
| 20110298474 | IMPLEMENTING INTEGRAL DYNAMIC VOLTAGE SENSING AND TRIGGER - A method and circuit for implementing dynamic voltage sensing and a trigger circuit, and a design structure on which the subject circuits resides are provided. The voltage sensing circuit includes a first quiet oscillator generating a reference clock, and a second noisy oscillator generating a noisy clock. A digital control loop coupled to the first quiet oscillator and the second noisy oscillator matches frequency of the first quiet oscillator and the second noisy oscillator. The reference clock drives a first predefined-bit shift register and the noisy clock drives a second predefined-bit shift register, where the second predefined-bit shift register is greater than the first predefined-bit shift register. When the first predefined-bit shift register overflows, the contents of the second predefined-bit shift register are evaluated. The contents of the second predefined-bit shift register are compared with a noise threshold select value to identify a noise event and trigger a noise detector control output. | 12-08-2011 |
| 20120212280 | IMPLEMENTING DUAL SPEED LEVEL SHIFTER WITH AUTOMATIC MODE CONTROL - A method and circuit for implementing a dual speed level shifter with automatic mode control, and a design structure on which the subject circuit resides are provided. A low speed level shifter and a high speed level shifter are used to provide a wide frequency range of operation. The circuit operates in one of a low speed mode or a high speed mode. The appropriate mode is selected automatically by detecting the frequency of the signal to be level shifted. When the incoming signal is slower than a reference frequency, the low speed level shifter is selected, and when the incoming signal is faster than the reference frequency, the high speed level shifter is selected. | 08-23-2012 |
| 20120331432 | IMPLEMENTING DUAL SPEED LEVEL SHIFTER WITH AUTOMATIC MODE CONTROL - A method and circuit for implementing a dual speed level shifter with automatic mode control, and a design structure on which the subject circuit resides are provided. A low speed level shifter and a high speed level shifter are used to provide a wide frequency range of operation. The circuit operates in one of a low speed mode or a high speed mode. The appropriate mode is selected automatically by detecting the frequency of the signal to be level shifted. When the incoming signal is slower than a reference frequency, the low speed level shifter is selected, and when the incoming signal is faster than the reference frequency, the high speed level shifter is selected. | 12-27-2012 |
| 20130088269 | IMPLEMENTING CONTROL VOLTAGE MIRROR - A circuit for implementing a control voltage mirror for phase error and jitter performance optimization and a design structure on which the subject circuit resides are provided. The control voltage mirror is used with a phase locked loop filter utilizing a thin oxide filter capacitor connected to a control voltage and a distal side of the capacitor connected to a voltage reference. The control voltage mirror includes an operational amplifier holding voltage across the capacitor to be near or at zero volts, substantially eliminating capacitor leakage current to provide phase error and jitter performance optimization. | 04-11-2013 |
| 20140167213 | Moat Construction to Reduce Noise Coupling to a Quiet Supply - A semiconductor chip having a P− substrate and an N+ epitaxial layer grown on the P− substrate is shown. A P− circuit layer is grown on top of the N+ epitaxial layer. A first moat having an electrically quiet ground connected to a first N+ epitaxial region is created by isolating the first N+ epitaxial region with a first deep trench. The first moat is surrounded, except for a DC path, by a second moat with a second N+ epitaxial region, created by isolating the second N+ epitaxial region with a second deep trench. The second moat may be arranged as a rectangular spiral around the first moat. | 06-19-2014 |
| 20160142062 | DIFFERENTIAL PHASE-FREQUENCY DETECTOR - A phase-frequency detector (PFD) is electrically coupled to a charge pump of a phase-locked-loop (PLL). The PFD includes a first differential latch electrically coupled to the charge pump. The first differential latch drives a differential pair of increment signals to the charge pump in response to differential pairs of both reference clock signals and reset signals. The PFD also includes a second differential latch electrically coupled to the charge pump. The second differential latch drives a differential pair of decrement signals to the charge pump in response to differential pairs of both feedback clock signals and reset signals. The PFD also includes a differential AND gate electrically coupled to both the first differential latch and the second differential latch. The differential AND gate drives the differential pair of reset signals to both of the differential latches in response to the differential pairs of both increment signals and decrement signals. | 05-19-2016 |
