Patent application number | Description | Published |
20080209248 | Method For Power Reduction And A Device Having Power Reduction Capabilities - A method for power reduction, the method includes determining whether to power down the at least portion of the component in response to a relationship between an estimated power gain and an estimated power loss resulting from powering down the at least portion of the component during the low power mode, and selectively providing power to at least a portion of a component of an integrated circuit during a low power mode. A device having power reduction capabilities, the device includes power switching circuitry adapted to selectively provide power to at least a portion of a component of the device during a low power mode, and a power management circuitry adapted to determine whether to power down at least the portion of the component during a low power mode in response to a relationship between an estimated power gain and an estimated power loss resulting from powering down the at least portion of the component during the low power. | 08-28-2008 |
20080250372 | Method and a Computer Readable Medium for Analyzing a Design of an Integrated Circuit - A method for analyzing an design of an integrated circuit, the method includes defining possible timings of signals to be provided to the integrated circuit and calculating hold violations; characterized by including a stage of determining relationships between clock events and corresponding data/control events that ideally precede the clock events, in response to the possible timing of signals; and determining hold parameters in response to the relationships. A computer readable medium having stored thereon a set of instructions, the set of instructions, when executed by a processor, cause the processor to define at least one internal delay of a designed component, characterized by causing the processor to define a cell that is characterized by multiple hold times and multiple setup values for a certain clock skew value. | 10-09-2008 |
20080256551 | System and Method For Storing State Information - A method for storing state information, the method includes storing, at a first circuit, state information representative of a state of a second circuit while the second circuit enters a low power mode; characterized by receiving an indication that a task switching from a first task to a second task should occur; storing a state information representative of a state of the second circuit, at the first circuit; receiving an indication that the first task should be resumed; and writing the stored state information from the first circuit to the second circuit. A system includes a first circuit and a second circuit, whereas the first circuit is connected to the second circuit and is adapted to store state information representative of a state of a second circuit; characterized by including a controller adapted to control a storage of the state information if at least a portion of the second circuit is powered down or if the second circuit is associated with a task switching operation. | 10-16-2008 |
20080270858 | Device and Method for Configuring Input/Output Pads - A method for configuring IO pads, the method includes determining a current configuration of multiple IO pads of an integrated circuit and whereas the method is characterized by generating multiple boundary scan register words that comprise Configuration information; and repeating the stage of serially writing a certain boundary scan register word to a boundary scan register and outputting the boundary scan register word to multiple IO pad control circuits. A device that includes a core, connected to a boundary scan register, a TAP controller and multiple IO pad circuits, the device is characterized by including a control circuit adapted to determine a current configuration of the IO pads, to generate multiple boundary scan register words that comprise configuration information; and to control a repetition of: writing a certain boundary scan register word to the boundary scan register and outputting the boundary scan register word to multiple IO pad control circuits. | 10-30-2008 |
20080294927 | Method and System for Clock Skew Reduction in Clock Trees - A system that includes a clock tree and multiple variable delay components. The system is characterized by including a first set of fuses indicative of identities of variable delay components that belong to a first set of variable delay components, a second set of fuses indicative of delay values of the variable delay components that belong to the first set of variable delay components, and a second set of variable delay components that are set to at least one default delay value. A method for reducing clock skews, the method includes providing a clock tree that includes a set of variable delay components. The method is characterized by selecting a first set of variable delay components in view of timing violations occurring due clock skews, setting delay values of variable delay components that form a first set of variable delay components by programming fuses, and setting delay values of variable delay components that form a second set of variable delay components to at least one default value. | 11-27-2008 |
20080307133 | Method for Synchronizing a Transmission of Information and a Device Having Synchronizing Capabilities - A method for synchronizing a transmission of information over a bus, and a device having synchronization capabilities. The device includes: a bus that includes multiple bus lines, a bus transmitter connected between an information source and the bus, a bus receiver connected between the bus and an information target; wherein the information source and the information target are mutually asynchronous; wherein the device is characterized by including a bus receiver control circuit that controls the bus receiver circuit and a bus transmitter control circuit that controls the bus transmitter circuit; wherein the bus transmitter control circuit enables to transmit information from the information source to the bus in response to a change in a value of a feedback signal sent from the bus receiver control circuit and wherein the bus receiver control circuit enables to provide information from the bus to the information target in response to a change in a value of a delayed strobe signal provided by a delay unit connected between the bus receiver control circuit and the bus transmitter control circuit. | 12-11-2008 |
20090003114 | Apparatus and Method for Reducing Power Consumption Using Selective Power Gating - A method for reducing power consumption of transistor-based circuit, the method includes: of receiving a low power mode indication; determining whether to supply power to at least a portion of the transistor-based circuit in response to a reset value of the transistor-based circuit and a state of the transistor-based circuit prior the receiving of the low power mode indication, and selectively providing power to at least a portion of the transistor-based circuit. An apparatus for reducing power consumption of a transistor-based circuit, the apparatus being connected to the transistor-based circuit, and is adapted to receive a low power mode indication, wherein the apparatus includes: means for determining whether to supply power to at least a portion of the transistor-based circuit in response a state of the transistor-based circuit prior the receiving of the low power mode indication; and means for power gating, adapted to selectively provide power to at least a portion of the transistor-based circuit in response to the determination. | 01-01-2009 |
20090006013 | Device and a Method For Estimating Transistor Parameter Variations - A method and a device for estimating parameter variations of transistors that belong to the same circuit. The method includes: providing the first circuit; providing a test circuit adapted to perform a first function and a stacked test circuit adapted to perform a second function that substantially equals the first function; wherein the test circuit, the stacked test circuit and the first circuit are processed under substantially the same processing conditions; determining a relationship between a parameter of the test circuit and a parameter of the stacked test circuit; and estimating parameter variations of transistors that belong to the first circuit in response to the determined relationship. | 01-01-2009 |
20090027819 | DEVICE HAVING FAILURE RECOVERY CAPABILITIES AND A METHOD FOR FAILURE RECOVERY - A device that has failure recovery capabilities and a method for power recovery. The method includes: detecting a potential power failure in response to a decrement rate of a supply voltage, and applying at least one failure recovery measure in response to a detected potential power failure. The device includes: a power source, an energy reservoir, at least one component, and a power failure circuit, adapted to detect a potential power failure in response to a decrement rate of a supply voltage. | 01-29-2009 |
20090174452 | DEVICE AND METHOD FOR HANDLING METASTABLE SIGNALS - A method and device for managing metastable signals. The device includes: a first latch and a second latch, a multiple switching point circuit, connected between an output node of the first latch and an input node of the second latch, wherein the multiple switching point circuit includes at least one pull up transistor and at least one pull down transistor that are selectively activated in response to a feedback signal provided from the second latch and in response to a an output signal of the first latch such as to define at least a low switching point that is lower than a high switching point of the multiple-switching point circuit; wherein a switching point of an inverter within the first latch is between the high and low switching points. | 07-09-2009 |
20090195265 | DEVICE AND METHOD FOR TESTING INTEGRATED CIRCUITS - A method and device for testing an integrated circuit. The method includes selecting between a shadow latch data retention mode and a shadow latch test mode; performing first test of an integrated circuit; storing, at the shadow latch if the shadow latch test mode is selected, information representative of a first test-imposed state; performing a second test of the integrated circuit; and generating a test equipment detectable signal if the first test-imposed state differs from a second test-imposed state of the tested latch. | 08-06-2009 |
20090315601 | DEVICE AND METHOD FOR TIMING ERROR MANAGEMENT - A device having timing error management capabilities and a method for timing error management. The device includes a first input node adapted to receive input data; a first latch, a second latch and a comparator, rising a first multiplexer and a second multiplexer; wherein the second multiplexer is adapted to provide input data to the second latch from the first input mode during a first operational mode of the device and to provide a first latch output signal to the second latch during a second operational mode; wherein the comparator is adapted to compare, during a first clock phase, between the first latch output signal and between a second latch output signal and in response to the comparison selectively generate an error signal. | 12-24-2009 |
20090322367 | INTEGRATED CIRCUIT AND A METHOD FOR MEASURING A QUIESCENT CURRENT OF A MODULE - A method for evaluating a quiescent current, the method includes: measuring, when a module is at a first mode, a first voltage drop on a first resistor that is coupled between a supply pin of an integrated circuit that comprises the module and a first test pin of the integrated circuit; assessing, when the module is at a second mode, a second voltage drop on a second resistor that is coupled between the supply pin and a second test pin of the integrated circuit; and evaluating a quiescent current of the module in response to the first and second voltage drops; wherein expected values of quiescent current of the module differ from one mode to the other; and wherein a resistance of the first resistor differs from the resistance of the second resistor. | 12-31-2009 |
20090327795 | METHOD FOR PROTECTING A SECURED REAL TIME CLOCK MODULE AND A DEVICE HAVING PROTECTION CAPABILITIES - A method for protecting a secured real time clock module, the method includes: locking multiple input ports of the secured real time clock module if the multiple input ports of the secured real time clock module are idle during at least a first duration; unlocking the multiple input ports of the secured real time clock module if a predefined high frequency code is received over a control input port of the secured real time clock module; and providing a secured real time clock signal when the multiple input ports of the secured real time clock module are locked and when the multiple input ports of the secured real time clock module are unlocked; wherein changes in a supply voltage results in a supply voltage induced changes of an input signal provided to an input port of the secured real time clock module; wherein a maximal frequency of the supply voltage induced changes of the input signal is lower then the high frequency of the predefined high frequency code. | 12-31-2009 |
20100019818 | DEVICE AND METHOD FOR POWER MANAGEMENT - A device having power management capabilities and a method for power management, the method includes: providing a clock signal and a supply voltage to at least one component of a device; detecting a timing error; delaying by a fraction of a clock cycle and in response to the detected timing error, a clock signal provided to at least one of the components; and determining a clock signal frequency and a level of the supply voltage in response to at least one detected timing error. | 01-28-2010 |
20100019837 | SYSTEM AND METHOD FOR POWER MANAGEMENT - A system, that includes: a memory unit adapted to store state duration statistics indicative of possible low power state durations and probabilities associates with the possible state durations; and a power controller, adapted to: receive a request to cause a circuit to enter a next state, and assist in causing the circuit to enter the next state if during a delay period that follows a reception of the request the power controller does not receive a request to cause the circuit to exit the next state; wherein the delay period is determined in response to: (i) the next state duration statistics, (ii) power saving gained from entering the next state; and (iii) power penalty associated with entering the next state and exiting the next state. | 01-28-2010 |
20100060342 | METHOD FOR POWER REDUCTION AND A DEVICE HAVING POWER REDUCTION CAPABILITIES - A device that includes: (i) an evaluated circuit; (ii) a leakage current dependent oscillator configured to generate an oscillating signal that has an oscillating frequency that represents a leakage current of the evaluated circuit; (iii) a switching current dependent oscillator configured to generate an oscillating signal that has an oscillating frequency that represents a switching induced current of the evaluated circuit; (iv) a power reduction module that is configured to: (a) compare between an oscillation frequency of the leakage current dependent oscillator and an oscillation frequency of the switching current dependent oscillator, to provide a current comparison result; (b) select a power reduction technique out of a dynamic voltage and frequency scaling technique and a power gating technique in view of the current comparison result; and (c) apply the selected power reduction technique. | 03-11-2010 |
20100070791 | POWER SUPPLY MONITORING METHOD AND SYSTEM - A device having a power supply monitoring capabilities, the device includes: a power supply unit; at least one real time clock generator counter adapted to receive a supply voltage from the power supply unit; a fixed value storage circuit that is un-accessible to software executed by a processor; wherein the fixed value storage circuit stores a fixed value; wherein the fixed value includes multiple bits; a volatile storage unit, being accessible to the processor; wherein the volatile storage unit is adapted to: (i) store a reset value after being reset; (ii) receive the fixed value during an initialization state; and (iii) store the fixed value until being reset; wherein the volatile storage unit is designed such that there is a low probability that the reset value equals the fixed value; and a comparator adapted to provide a tamper indication if the fixed value stored at the fixed value storage circuit differs from a value stored at the volatile storage unit. | 03-18-2010 |
20100182055 | DEVICE AND METHOD FOR DETECTING AND CORRECTING TIMING ERRORS - A device that includes an error detection circuit that is configured to detect a timing error resulting from a fast voltage drop by comparing a signal from a critical path to a signal from a replica path; and a clock signal provider that is adapted to receive a clock signal and to delay, by a fraction of the clock cycle and in response to a detection of the timing error, the clock signal to provide a delayed clock signal that is provided to a clocked circuit that is coupled to the critical path; and a controller that is configured determine a level of a supply voltage in response to a capability of the error detection circuit and the clock signal provider to manage fast voltage drops; wherein the supply voltage is provided to at least one component of the critical path. | 07-22-2010 |
20100202235 | DEVICE AND METHOD FOR STATE RETENTION POWER GATING - A device for state retention power gating, the device includes a group of circuits, each circuit is characterized by a reset state, wherein the device is characterized by including: a first memory entity adapted to save during a shut down period of the group circuits, at least one location of at least one non-reset-state circuit of the group of circuits. | 08-12-2010 |
20100225357 | REAL TIME CLOCK MONITORING METHOD AND SYSTEM - Method for monitoring a real time clock and a device having real time clock monitoring capabilities, the device includes: (i) a real time clock tree, (ii) a clock frequency monitor that is adapted to determine a frequency of a real time clock signal, during a short monitoring period; (iii) a monitoring enable module, adapted to activate the clock frequency monitor during short motoring periods and to deactivate the clock frequency monitor during other periods, wherein the monitoring enable module is adapted to determine a timing of the short monitoring periods in a non-deterministic manner; and (iv) a real time clock violation indication generator adapted to indicate that a real time clock violation occurred, in response to an error signal provided from the clock frequency monitor. | 09-09-2010 |
20100332851 | METHOD FOR PROTECTING A CRYPTOGRAPHIC MODULE AND A DEVICE HAVING CRYPTOGRAPHIC MODULE PROTECTION CAPABILITIES - A device and a method for protecting a cryptographic module of which the method includes: estimating a functionality of a circuit that is adapted to malfunction when a physical parameter has a first value different from a nominal parameter value at which the cryptographic module functions correctly. The cryptographic module malfunctions when the physical parameter has a second value different from the nominal parameter value and a difference between the first value and the nominal parameter value being smaller than a difference between the second value and the nominal parameter value. A cryptographic module protective measure is applied if estimating that the circuit malfunctions. | 12-30-2010 |
20120218033 | INTEGRATED CIRCUIT AND METHOD FOR REDUCTION OF SUPPLY VOLTAGE CHANGES - An integrated circuit and a method. The integrated circuit includes an internal component having an output for providing a driven input signal; an output driver, connected to the internal component, for converting said driven input signal in an output signal; an output pad for outputting said output signal to a component outside the integrated circuit; a power grid configured to supply a supply voltage to the output driver; a controllable current consuming component connected to the power grid, said connectable current consuming component being controllable to consume current in accordance with a supply voltage change reduction pattern; a change detector connected to the internal component and the controllable current consuming component, for detecting a change in said driven input signal prior to said change resulting in a change in said output signal and to control said current consuming component to consume current in response to said detecting. | 08-30-2012 |
20120235732 | INTEGRATED CIRCUIT COMPRISING REFERENCE VOLTAGE GENERATION CIRCUITRY AND ELECTRONIC DEVICE - An integrated circuit comprises reference voltage generation circuitry for providing a reference voltage for use within a transmission of electrical signals. The reference voltage generation circuitry comprises a reference voltage node operably coupled via a plurality of resistance elements to a plurality of signal nodes such that the reference voltage node assumes as the reference voltage an average of the voltage values of the signal nodes to which it is coupled. | 09-20-2012 |
20120319731 | INTEGRATED CIRCUIT DEVICE COMPRISING CLOCK GATING CIRCUITRY, ELECTRONIC DEVICE AND METHOD FOR DYNAMICALLY CONFIGURING CLOCK GATING - An integrated circuit comprises clock gating circuitry comprising at least one gating component located within a clock distribution network and arranged to enable at least one part of the clock distribution network to be gated, and gating control circuitry arranged to cause the at least one gating component to disable the at least one part of the clock distribution network upon certain conditions being fulfilled. The clock gating circuitry further comprises clock gating disabling circuitry configurable to enable the gating of the at least one part of the clock distribution network to be disabled. | 12-20-2012 |
20130007431 | INTEGRATED CIRCUIT DEVICE, SIGNAL PROCESSING SYSTEM, ELECTRONIC DEVICE AND METHOD THEREFOR - An integrated circuit device comprises a signal processing system having at least one first signal processing module fabricated by way of a first production process; and at least one second signal processing module fabricated by way of a second production process, wherein the second production process is different to the first production process. The signal processing system further comprises a signal processing management module arranged to: determine a desired system performance of the integrated circuit device; determine at least one operating condition of the signal processing system; and configure a signal processing operating mode of the signal processing system based at least partly on: the determined desired system performance; the at least one determined operating condition; and at least one of the first production process and the second production process. | 01-03-2013 |
20130124800 | APPARATUS AND METHOD FOR REDUCING PROCESSOR LATENCY - There is provided a data processing system comprising a central processing unit, a processor cache memory operably coupled to the central processing unit and an external connection operably coupled to the central processing unit and processor cache memory in which a portion of the data processing system is arranged to load data directly from the external connection into the processor cache memory and modify a source address of said directly loaded data. There is also provided a method of improving latency in a data processing system having a central processing unit operably coupled to a processor cache memory and an external connection operably coupled to the central processing unit and processor cache memory, comprising loading data directly from the external connection into the processor cache memory and modifying a source address for said data to become indicative of a location other than from the external connection. | 05-16-2013 |
20130132756 | ELECTRONIC CIRCUIT AND METHOD FOR STATE RETENTION POWER GATING - An electronic circuit includes a processor having a functional mode and a low power mode, said processor comprising state flip-flops and additional flip-flops; said state flip flips are arranged to store state information about a state of the processor when the processor is in the functional mode; said state flip-flops comprise non-reset flip-flops that are arranged to store at least one non-reset value when the processor exits the functional mode; a power management circuit for providing power to the processor when the processor is in the functional mode, and for preventing power from the processor when the processor is in the low power mode; a non-reset value identification module, coupled to the state flip-flops, said non-reset value identification module is arranged to identify the non-reset flip-flops and to generate non-reset information that identifies the non-reset flip-flops; and a recovery circuit, coupled to a memory module and to the state flip-flops. | 05-23-2013 |
20130300386 | INTEGRATED CIRCUIT DEVICE, VOLTAGE REGULATION CIRCUITRY AND METHOD FOR REGULATING A VOLTAGE SUPPLY SIGNAL - An integrated circuit (IC) device is provided that includes at least one internal voltage regulator arranged to receive a voltage supply signal at a first input thereof, receive a control signal at a second input thereof, regulate the received voltage supply signal in accordance with the received control signal, and provide a regulated voltage supply signal at an output thereof. The IC device further includes at least one voltage regulation power control module operably coupled to the second input of the at least one internal voltage regulator and arranged to provide the control signal thereto. The voltage regulation power control module is further arranged to receive at least one IC device conditional indication, and generate the control signal for the at least one internal voltage regulator based at least partly on an available thermal power budget for the IC device corresponding to the at least one IC device conditional indication. | 11-14-2013 |
20130308409 | INTEGRATED CIRCUIT DEVICE, POWER MANAGEMENT MODULE AND METHOD FOR PROVIDING POWER MANAGEMENT - An integrated circuit device comprising at least one memory module comprising a plurality of memory sub-modules, and at least one power management module arranged to provide power management for the at least one memory module. The at least one power management module is arranged to determine when content of at least one memory sub-module is redundant, and place the at least one memory sub-module into a powered-down state upon determining that content of the at least one memory sub-module is redundant. | 11-21-2013 |
20140002160 | INTEGRATED CIRCUIT AND METHOD FOR REDUCING AN IMPACT OF ELECTRICAL STRESS IN AN INTEGRATED CIRCUIT | 01-02-2014 |
20140077598 | VOLTAGE REGULATING CIRCUIT AND METHOD - A voltage regulating circuit is provided for regulating an output voltage in order to minimize an absolute difference between a level of said output voltage and a reference level. The voltage regulating circuit comprises a voltage regulator and a reference level generator. The reference level generator generates an internal reference level on the basis of said output voltage level and said reference level such that said internal reference level does not exceed said output voltage level by more than a maximum allowed increment. The voltage regulator regulates said output voltage in order to minimize an absolute difference between said output voltage level and said internal reference level. A method of regulating an output voltage is also disclosed. | 03-20-2014 |
20140115358 | INTEGRATED CIRCUIT DEVICE AND METHOD FOR CONTROLLING AN OPERATING MODE OF AN ON-DIE MEMORY - An integrated circuit device comprising at least one instruction processing module, at least one memory comprising at least one memory bank configurable to operate in a first functional mode and at least one further, lower-power mode, and at least one memory mode control module arranged to control switching of the at least one memory bank between the first functional mode and the at least one further, lower-power modes. | 04-24-2014 |
20140303804 | METHOD OF CONTROLLING A THERMAL BUDGET OF AN INTEGRATED CIRCUIT DEVICE, AN INTEGRATED CIRCUIT, A THERMAL CONTROL MODULE AND AN ELECTRONIC DEVICE THEREFOR - A method of controlling a thermal budget of an integrated circuit device is described. The method comprises obtaining a first junction temperature measurement value for the integrated circuit device at a first time instant, and a further junction temperature measurement value for the integrated circuit device at a further time instant. The method further comprises calculating a prospective junction temperature value for the integrated circuit device at a future time instant based at least partly on the first and further junction temperature measurement values; and configuring an operating condition of the integrated circuit device based at least partly on the calculated prospective junction temperature value. | 10-09-2014 |
20140325183 | INTEGRATED CIRCUIT DEVICE, ASYMMETRIC MULTI-CORE PROCESSING MODULE, ELECTRONIC DEVICE AND METHOD OF MANAGING EXECUTION OF COMPUTER PROGRAM CODE THEREFOR - An asymmetric multi-core processing module is described. The asymmetric multi-core processing module comprises at least one processing core of a first type, at least one processing core of at least one further type, and at least one core identifier configuration component. The at least one core identifier configuration component is arranged to enable dynamic configuration of a value of a core identifier of at least one of the processing cores of the first and at least one further types. | 10-30-2014 |