Patent application number | Description | Published |
20090157967 | Pre-Fetch Data and Pre-Fetch Data Relative - A prefetch data machine instruction having an M field performs a function on a cache line of data specifying an address of an operand. The operation comprises either prefetching a cache line of data from memory to a cache or reducing the access ownership of store and fetch or fetch only of the cache line in the cache or a combination thereof. The address of the operand is either based on a register value or the program counter value pointing to the prefetch data machine instruction. | 06-18-2009 |
20090182942 | Extract Cache Attribute Facility and Instruction Therefore - A facility and cache machine instruction of a computer architecture for specifying a target cache cache-level and a target cache attribute of interest for obtaining a cache attribute of one or more target caches. The requested cache attribute of the target cache(s) is saved in a register. | 07-16-2009 |
20090182964 | DYNAMIC ADDRESS TRANSLATION WITH FORMAT CONTROL - What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. An index portion of the virtual address is used to reference an entry in the translation table. If the format control field is enabled, a frame address of a large block of data in main storage is obtained from the translation table entry. The large block of data is a block of at least 1M byte in size. The frame address is then combined with an offset portion of the virtual address to form the translated address of a desired block of data within the large block of data in main storage. The desired large block of data addressed by the translated address is then accessed. | 07-16-2009 |
20090182966 | DYNAMIC ADDRESS TRANSLATION WITH FRAME MANAGEMENT - What is disclosed is a frame management function defined for a machine architecture of a computer system. In one embodiment, a frame management instruction is obtained which identifies a first and second general register. The first general register contains a frame management field having a key field with access-protection bits and a block-size indication. If the block-size indication indicates a large block then an operand address of a large block of data is obtained from the second general register. The large block of data has a plurality of small blocks each of which is associated with a corresponding storage key having a plurality of storage key access-protection bits. If the block size indication indicates a large block, the storage key access-protection bits of each corresponding storage key of each small block within the large block is set with the access-protection bits of the key field. | 07-16-2009 |
20090182971 | DYNAMIC ADDRESS TRANSLATION WITH FETCH PROTECTION - What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated is first obtained and an initial origin address of a translation table of the hierarchy of translation tables is obtained. Based on the obtained initial origin, a segment table entry is obtained. The segment table entry is configured to contain a format control and access validity fields. If the format control and access validity fields are enabled, the segment table entry further contains an access control field, a fetch protection field, and a segment-frame absolute address. Store operations are permitted only if the access control field matches a program access key provided by any one of a Program Status Word or an operand of a program instruction being executed. Fetch operations are permitted if the program access key associated with the virtual address is equal to the segment access control field. | 07-16-2009 |
20090182972 | DYNAMIC ADDRESS TRANSLATION WITH FORMAT CONTROL - What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. An index portion of the virtual address is used to reference an entry in the translation table. If a format control field contained in the translation table entry is enabled, the table entry contains a frame address of a large block of data of at least 1M byte in size. The frame address is then combined with an offset portion of the virtual address to form the translated address of a small 4K byte block of data in main storage or memory. | 07-16-2009 |
20090182983 | Compare and Branch Facility and Instruction Therefore - An atomic compare and branch instruction is executed that combines the function of a compare instruction having an option field with a conditional branch or jump instruction such that condition codes are preserved rather than setting condition codes to a value representative of the compare results. One comparand is obtained from any one of a memory location or an immediate field and the other comparand is obtained from a register field. | 07-16-2009 |
20090182984 | Execute Relative Long Facility and Instructions Therefore - A method, system and program product for an execute relative instruction, which when executed fetches and executes a target instruction at a relative address and then returns processing to the next instruction following the execute relative instruction. The relative address is formed by adding the value of the program counter to a sign extended immediate field. The fetched target instruction is optionally modified before execution by OR'ing bits into predetermined bits of the target instruction. | 07-16-2009 |
20090182985 | Move Facility and Instructions Therefore - A move instruction, having a signed immediate field, copies a sign extended signed immediate field value to an operand location in memory. The size of the operand is determined by the opcode of the instruction. Preferably, the address of the operand is determined by adding a displacement field of the instruction to a value associated with a register field of the instruction. | 07-16-2009 |
20090182988 | Compare Relative Long Facility and Instructions Therefore - A method, system and program product for comparing two operands wherein one operand is obtained from memory wherein the address of the memory operand is based an offset of the program counter rather than an explicitly defined address location. The offset is defined by an immediate field of the instruction which is sign extended and is aligned as a halfword address when added to the value of the program counter. | 07-16-2009 |
20090182992 | Load Relative and Store Relative Facility and Instructions Therefore - A method, system and program product for loading or storing memory data wherein the address of the memory operand is based an offset of the program counter rather than an explicitly defined address location. The offset is defined by an immediate field of the instruction which is sign extended and is aligned as a halfword address when added to the value of the program counter. | 07-16-2009 |
20090187724 | DYNAMIC ADDRESS TRANSLATION WITH FRAME MANAGEMENT - What is disclosed is a set key and clear frame management function defined for a machine architecture of a computer system. In one embodiment, a machine instruction is obtained which identifies a first and second general register. Obtained from the first general register is a frame size field indicating whether a storage frame is one of a small block or a large block of data. Obtained from the second general register is an operand address of a storage frame upon which the instruction is to be performed. If the storage frame is a small block, the instruction is performed only on the small block. If the indicated storage frame is a large block of data, an operand address of an initial first block of data within the large block of data is obtained from the second general register. The frame management instruction is performed on all blocks starting from the initial first block. | 07-23-2009 |
20090187728 | DYNAMIC ADDRESS TRANSLATION WITH CHANGE RECORDING OVERRIDE - What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. A segment table entry obtained from a segment table contains a format control field. If the format control field is enabled, a segment-frame absolute address of a large block of data in main storage is obtained from the segment table entry. Each 4K byte block of data within the large block has an associated storage key. Store operations associated with the virtual address are performed to the desired block of data. If the change recording override field is disabled, the change bit of the storage key associated with the desired 4K byte block is set to 1. An indication is then provided that the desired 4K byte block has been modified. | 07-23-2009 |
20090187732 | DYNAMIC ADDRESS TRANSLATION WITH DAT PROTECTION - What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of any one of a region first table, a region second table, a region third table, or a segment table are obtained. Based on the obtained initial origin address, a segment table entry is obtained which contains a format control and DAT protection fields. If the format control field is enabled, obtaining from the translation table entry a segment-frame absolute address of a large block of data in main storage. The segment-frame absolute address is combined with a page index portion and a byte index portion of the virtual address to form a translated address of the desired block of data. If the DAT protection field is not enabled, fetches and stores are permitted to the desired block of data addressed by the translated virtual address. | 07-23-2009 |
20090193214 | DYNAMIC ADDRESS TRANSLATION WITH FRAME MANAGEMENT - What is disclosed is a frame management function defined for a machine architecture of a computer system. In one embodiment, a machine instruction is obtained containing an opcode for a frame management instruction identifying a first and second general register. Clear frame information is obtained from the first general register having a frame size field indicating whether a storage frame is a small or large block of data. The second general register contains an operand address of a storage frame. If the storage frame is a small block, all bytes of the small block of data are set to zero. If the storage frame is a large block of data, an operand address of an initial first block of data within the large block is obtained from the second general register. All data of all blocks within the large block are cleared starting from the initial first block. | 07-30-2009 |
20090193237 | PARSING-ENHANCEMENT FACILITY - An instruction for parsing a buffer to be utilized within a data processing system including: an operation code field, the operation code field identifies the instruction; a control field, the control field controls operation of the instruction; and one or more general register, wherein a first general register stores an argument address, a second general register stores a function code, a third general register stores length of an argument-character buffer, and the fourth of which contains the address of the function-code data structure. | 07-30-2009 |
20090216963 | SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR PROVIDING A SHARED MEMORY TRANSLATION FACILITY - A system, method and computer program product for providing a shared memory translation facility. The method includes receiving a request for access to a memory address from a requestor at a configuration, the receiving at a shared memory translation mechanism. It is determined if the memory address refers to a shared memory object (SMO), the SMO accessible by a plurality of configurations. In response to determining that the memory address refers to the SMO, it is determined if the configuration has access to the SMO. In response to determining that the configuration has access to the SMO, the requestor is provided a system absolute address for the SMO and access to the SMO. In this manner direct interchange of data between the plurality of configurations is allowed. | 08-27-2009 |
20090216984 | OPTIMIZATIONS OF A PERFORM FRAME MANAGEMENT FUNCTION ISSUED BY PAGEABLE GUESTS - Optimizations are provided for frame management operations, including a clear operation and/or a set storage key operation, requested by pageable guests. The operations are performed, absent host intervention, on frames not resident in host memory. The operations may be specified in an instruction issued by the pageable guests. | 08-27-2009 |
20090216992 | DYNAMIC ADDRESS TRANSLATION WITH TRANSLATION EXCEPTION QUALIFIER - What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. Dynamic address translation of the virtual address proceeds. In response to a translation interruption having occurred during dynamic address translation, bits are stored in a translation exception qualifier (TXQ) field to indicate that the exception was either a host DAT exception having occurred while running a host program or a host DAT exception having occurred while running a guest program. The TXQ is further capable of indicating that the exception was associated with a host virtual address derived from a guest page frame real address or a guest segment frame absolute address. The TXQ is further capable of indicating that a larger or smaller host frame size is preferred to back a guest frame. | 08-27-2009 |
20090216995 | SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR PROVIDING QUIESCE FILTERING FOR SHARED MEMORY - A system, method and computer program product for providing quiesce filtering for shared memory. The method includes receiving a shared-memory quiesce request at a processor. The request includes a donor zone. The processor includes translation look aside buffer one (TLB | 08-27-2009 |
20090217098 | MANAGING USE OF STORAGE BY MULTIPLE PAGEABLE GUESTS OF A COMPUTING ENVIRONMENT - Management of storage used by pageable guests of a computing environment is facilitated. An enhanced suppression-on-protection facility is provided that enables the determination of which level of protection (host or guest) caused a fault condition, in response to an attempted storage access. | 08-27-2009 |
20090259875 | Store Clock and Store Clock Fast Instruction Execution - Two forms of TOD Clock instructions are provided, Store Clock and Store Clock Fast. Execution of the Store Clock Fast instruction may produce a time of day (TOD) result that is exactly the same as a previous TOD result, however execution of Store Clock Fast instructions while the clock is running always produce unique TOD results. | 10-15-2009 |
20090327658 | COMPARE, SWAP AND STORE FACILITY WITH NO EXTERNAL SERIALIZATION - A compare, swap and store facility is provided that does not require external serialization. A compare and swap operation is performed using an interlocked update operation. If the comparison indicates equality, a store operation is performed. The compare, swap and store operations are performed as a single unit of operation. | 12-31-2009 |
20100299506 | ROTATE THEN OPERATE ON SELECTED BITS FACILITY AND INSTRUCTIONS THEREFORE - A rotate then operate instruction having a T bit is fetched and executed wherein a first operand in a first register is rotated by an amount and a Boolean operation is performed on a selected portion of the rotated first operand and a second operand in of a second register. If the T bit is ‘0’ the selected portion of the result of the Boolean operation is inserted into corresponding bits of a second operand of a second register. If the T bit is ‘1’, in addition to the inserted bits, the bits other than the selected portion of the rotated first operand are saved in the second register. | 11-25-2010 |
20100325385 | DETECTION OF ZERO ADDRESS EVENTS IN ADDRESS FORMATION - One or more registers used to form an address usable in accessing storage are examined to determine if a zero address event has occurred in forming the address. In response to an indication that a zero address event has occurred in address formation, an alert is provided to the program using the address to access storage. | 12-23-2010 |
20100325401 | Method of Translating N to N Instructions Employing an Enhanced Extended Translation Facility - A method, article, and system for providing an effective implementation of assembler language translate-n-to-n instructions implemented on 21, 31, and 64-bit architectures, while maintaining backward compatibility with existing systems. The enhanced Extended-Translation Facility 2 (ETF2) instruction set introduces a new operand in an unused field (M | 12-23-2010 |
20110131382 | Extract Cache Attribute Facility and Instruction Therefore - A facility and cache machine instruction of a computer architecture for specifying a target cache cache-level and a target cache attribute of interest for obtaining a cache attribute of one or more target caches. The requested cache attribute of the target cache(s) is saved in a register. | 06-02-2011 |
20110145550 | NON-QUIESCING KEY SETTING FACILITY - A non-quiescing key setting facility is provided that enables manipulation of storage keys to be performed without quiescing operations of other processors of a multiprocessor system. With this facility, a storage key, which is accessible by a plurality of processors of the multiprocessor system, is updated absent a quiesce of operations of the plurality of processors. Since the storage key is updated absent quiescing of other operations, the storage key may be observed by a processor as having one value at the start of an operation performed by the processor and a second value at the end of the operation. A mechanism is provided to enable the operation to continue, avoiding a fatal exception. | 06-16-2011 |
20110271085 | PARSING-ENHACEMENT FACILITY - An instruction for parsing a buffer to be utilized within a data processing system including: an operation code field, the operation code field identifies the instruction; a control field, the control field controls operation of the instruction; and one or more general register, wherein a first general register stores an argument address, a second general register stores a function code, a third general register stores length of an argument-character buffer, and the fourth of which contains the address of the function-code data structure. | 11-03-2011 |
20110314260 | HIGH-WORD FACILITY FOR EXTENDING THE NUMBER OF GENERAL PURPOSE REGISTERS AVAILABLE TO INSTRUCTIONS - A computer employs a set of General Purpose Registers (GPRs). Each GPR comprises a plurality of portions. Programs such as an Operating System and Applications operating in a Large GPR mode, access the full GPR, however programs such as Applications operating in Small GPR mode, only have access to a portion at a time. Instruction Opcodes, in Small GPR mode, may determine which portion is accessed. | 12-22-2011 |
20110314263 | INSTRUCTIONS FOR PERFORMING AN OPERATION ON TWO OPERANDS AND SUBSEQUENTLY STORING AN ORIGINAL VALUE OF OPERAND - An arithmetic/logical instruction is executed having interlocked memory operands. when executed obtains a second operand from a location in memory, and saves a temporary copy of the second operand, the execution performs an arithmetic or logical operation based on the second operand and a third operand and stores the result in the memory location of the second operand, and subsequently stores the temporary copy in a first register. | 12-22-2011 |
20110320638 | ENABLE/DISABLE ADAPTERS OF A COMPUTING ENVIRONMENT - An adapter is enabled for use. The enabling includes assigning one or more address spaces to the adapter, based on a request. For each address space assigned to the adapter, a corresponding device table entry is assigned. When the adapter is no longer needed, it is disabled and the assigned device table entries become available. | 12-29-2011 |
20110320644 | RESIZING ADDRESS SPACES CONCURRENT TO ACCESSING THE ADDRESS SPACES - Address spaces are resized concurrent to accessing those address spaces. The size of an address space can be increased or decreased concurrent to performing read or write operations on the address space. Further, cache entries associated with an address space being decreased in size are purged. | 12-29-2011 |
20110320652 | CONTROLLING ACCESS BY A CONFIGURATION TO AN ADAPTER FUNCTION - Access to an input/output adapter by a configuration is controlled. For each requested access to an adapter, checks are made to determine whether the configuration is authorized to access the adapter. If it is not authorized, then access is denied. If it is authorized, but access should be temporarily blocked, then instruction execution is altered to indicate such. If access is permitted, but should be blocked for another reason (other than temporarily), then access is denied. | 12-29-2011 |
20110320756 | RUNTIME DETERMINATION OF TRANSLATION FORMATS FOR ADAPTER FUNCTIONS - Various address translation formats are available for use in obtaining system memory addresses for use by requestors, such as adapter functions, in accessing system memory. The particular address translation format to be used by a given requestor is pre-registered in a device table entry associated with that requestor. | 12-29-2011 |
20110320757 | STORE/STORE BLOCK INSTRUCTIONS FOR COMMUNICATING WITH ADAPTERS - Communication with adapters of a computing environment is facilitated. Instructions are provided that explicitly target the adapters. Information provided in an instruction is used to steer the instruction to an appropriate location within the adapter. | 12-29-2011 |
20110320758 | TRANSLATION OF INPUT/OUTPUT ADDRESSES TO MEMORY ADDRESSES - An address provided in a request issued by an adapter is converted to an address directly usable in accessing system memory. The address includes a plurality of bits, in which the plurality of bits includes a first portion of bits and a second portion of bits. The second portion of bits is used to index into one or more levels of address translation tables to perform the conversion, while the first portion of bits are ignored for the conversion. The first portion of bits are used to validate the address. | 12-29-2011 |
20110320764 | LOAD INSTRUCTION FOR COMMUNICATING WITH ADAPTERS - Communication with adapters of a computing environment is facilitated. Instructions are provided that explicitly target the adapters. Information provided in an instruction is used to steer the instruction to an appropriate location within the adapter. | 12-29-2011 |
20110320772 | CONTROLLING THE SELECTIVELY SETTING OF OPERATIONAL PARAMETERS FOR AN ADAPTER - An instruction is provided to establish various operational parameters for an adapter. These parameters include adapter interruption parameters, input/output address translation parameters, resetting error indications, setting measurement parameters, and setting an interception control, as examples. The instruction specifies a function information block, which is a program representation of a device table entry used by the adapter, to be used in certain situations in establishing the parameters. A store instruction is also provided that stores the current contents of the function information block. | 12-29-2011 |
20110320773 | FUNCTION VIRTUALIZATION FACILITY FOR BLOCKING INSTRUCTION FUNCTION OF A MULTI-FUNCTION INSTRUCTION OF A VIRTUAL PROCESSOR - In a processor supporting execution of a plurality of functions of an instruction, an instruction blocking value is set for blocking one or more of the plurality of functions, such that an attempt to execute one of the blocked functions, will result in a program exception and the instruction will not execute, however the same instruction will be able to execute any of the functions that are not blocked functions. | 12-29-2011 |
20110320825 | FUNCTION VIRTUALIZATION FACILITY FOR FUNCTION QUERY OF A PROCESSOR - Selected installed function of a multi-function instruction is hidden such that even though a processor is capable of performing the hidden installed function, the availability of the hidden function is hidden such that responsive to the multi-function instruction querying the availability of functions, only functions not hidden are reported as installed. | 12-29-2011 |
20110321158 | GUEST ACCESS TO ADDRESS SPACES OF ADAPTER - An authorization mechanism allows a host executing a guest operating system to grant permission for the guest to directly access an adapter function's address spaces without host intervention. This access is via instructions implemented based on the architecture of the adapter function. The host also has the capability to intervene in the execution of the instruction, if desired. | 12-29-2011 |
20120011341 | Load Page Table Entry Address Instruction Execution Based on an Address Translation Format Control Field - What is provided is a load page table entry address function defined for a machine architecture of a computer system. In one embodiment, a machine instruction is obtained which contains an opcode indicating that a load page table entry address function is to be performed. The machine instruction contains an M field, a first field identifying a first general register, and a second field identifying a second general register. Based on the contents of the M field, an initial origin address of a hierarchy of address translation tables having at least one segment table is obtained. Based on the obtained initial origin address, dynamic address translation is performed until a page table entry is obtained. The page table entry address is saved in the identified first general register. | 01-12-2012 |
20120084488 | Dynamic Address Translation With Translation Exception Qualifier - What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. Dynamic address translation of the virtual address proceeds. In response to a translation interruption having occurred during dynamic address translation, bits are stored in a translation exception qualifier (TXQ) field to indicate that the exception was either a host DAT exception having occurred while running a host program or a host DAT exception having occurred while running a guest program. The TXQ is further capable of indicating that the exception was associated with a host virtual address derived from a guest page frame real address or a guest segment frame absolute address. The TXQ is further capable of indicating that a larger or smaller host frame size is preferred to back a guest frame. | 04-05-2012 |
20120109622 | EXTRACT CPU TIME FACILITY - An efficient facility for determining resource usage, such as a processor time used by tasks. The determination is performed on behalf of user applications that do not require a call to operating system services. The facility includes an instruction that determines elapsed time and reports it to the user as a single unit of operation. | 05-03-2012 |
20120137073 | Extract Cache Attribute Facility and Instruction Therefore - A facility and cache machine instruction of a computer architecture for specifying a target cache cache-level and a target cache attribute of interest for obtaining a cache attribute of one or more target caches. The requested cache attribute of the target cache(s) is saved in a register. | 05-31-2012 |
20120137106 | Dynamic Address Translation With Translation Table Entry Format Control for Identifying Format of the Translation Table Entry - What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. An index portion of the virtual address is used to reference an entry in the translation table. If a format control field contained in the translation table entry is enabled, the table entry contains a frame address of a large block of data of at least 1M byte in size. The frame address is then combined with an offset portion of the virtual address to form the translated address of a small 4K byte block of data in main storage or memory. | 05-31-2012 |
20120144125 | Instruction for Pre-Fetching Data and Releasing Cache Lines - A prefetch data machine instruction having an M field performs a function on a cache line of data specifying an address of an operand. The operation comprises either prefetching a cache line of data from memory to a cache or reducing the access ownership of store and fetch or fetch only of the cache line in the cache or a combination thereof. The address of the operand is either based on a register value or the program counter value pointing to the prefetch data machine instruction. | 06-07-2012 |
20120144153 | Dynamic Address Translation With Change Record Override - A translation table entry contains a change recording override field for controlling whether a change bit is to be set on a store or not. Each 4K byte block of main storage has an associated storage key comprising a change bit. The change recording override field controls whether the change bit of the storage key associated with the desired 4K byte block of main storage is set to 1 for a store operation. | 06-07-2012 |
20120166758 | Executing a Perform Frame Management Instruction - What is disclosed is a frame management function defined for a machine architecture of a computer system. In one embodiment, a frame management instruction is obtained which identifies a first and second general register. The first general register contains a frame management field having a key field with access-protection bits and a block-size indication. If the block-size indication indicates a large block then an operand address of a large block of data is obtained from the second general register. The large block of data has a plurality of small blocks each of which is associated with a corresponding storage key having a plurality of storage key access-protection bits. If the block size indication indicates a large block, the storage key access-protection bits of each corresponding storage key of each small block within the large block is set with the access-protection bits of the key field. | 06-28-2012 |
20120204010 | NON-QUIESCING KEY SETTING FACILITY - A non-quiescing key setting facility is provided that enables manipulation of storage keys to be performed without quiescing operations of other processors of a multiprocessor system. With this facility, a storage key, which is accessible by a plurality of processors of the multiprocessor system, is updated absent a quiesce of operations of the plurality of processors. Since the storage key is updated absent quiescing of other operations, the storage key may be observed by a processor as having one value at the start of an operation performed by the processor and a second value at the end of the operation. A mechanism is provided to enable the operation to continue, avoiding a fatal exception. | 08-09-2012 |
20120216022 | CONTROLLING THE SELECTIVELY SETTING OF OPERATIONAL PARAMETERS FOR AN ADAPTER - An instruction is provided to establish various operational parameters for an adapter. These parameters include adapter interruption parameters, input/output address translation parameters, resetting error indications, setting measurement parameters, and setting an interception control, as examples. The instruction specifies a function information block, which is a program representation of a device table entry used by the adapter, to be used in certain situations in establishing the parameters. A store instruction is also provided that stores the current contents of the function information block. | 08-23-2012 |
20120284477 | EXECUTION OF A PERFORM FRAME MANAGEMENT FUNCTION INSTRUCTION - Optimizations are provided for frame management operations, including a clear operation and/or a set storage key operation, requested by pageable guests. The operations are performed, absent host intervention, on frames not resident in host memory. The operations may be specified in an instruction issued by the pageable guests. | 11-08-2012 |
20130067194 | TRANSLATION OF INPUT/OUTPUT ADDRESSES TO MEMORY ADDRESSES - An address provided in a request issued by an adapter is converted to an address directly usable in accessing system memory. The address includes a plurality of bits, in which the plurality of bits includes a first portion of bits and a second portion of bits. The second portion of bits is used to index into one or more levels of address translation tables to perform the conversion, while the first portion of bits are ignored for the conversion. The first portion of bits are used to validate the address. | 03-14-2013 |
20130117545 | High-Word Facility for Extending the Number of General Purpose Registers Available to Instructions - A computer employs a set of General Purpose Registers (GPRs). Each GPR comprises a plurality of portions. Programs such as an Operating System and Applications operating in a Large GPR mode, access the full GPR, however programs such as Applications operating in Small GPR mode, only have access to a portion at a time. Instruction Opcodes, in Small GPR mode, may determine which portion is accessed. | 05-09-2013 |
20130290671 | Emulating Execution of a Perform Frame Management Instruction - What is disclosed is a frame management function defined for a machine architecture of a computer system. In one embodiment, a frame management instruction is obtained which identifies a first and second general register. The first general register contains a frame management field having a key field with access-protection bits and a block-size indication. If the block-size indication indicates a large block then an operand address of a large block of data is obtained from the second general register. The large block of data has a plurality of small blocks each of which is associated with a corresponding storage key having a plurality of storage key access-protection bits. If the block size indication indicates a large block, the storage key access-protection bits of each corresponding storage key of each small block within the large block is set with the access-protection bits of the key field. | 10-31-2013 |
20130305023 | EXECUTION OF A PERFORM FRAME MANAGEMENT FUNCTION INSTRUCTION - Optimizations are provided for frame management operations, including a clear operation and/or a set storage key operation, requested by pageable guests. The operations are performed, absent host intervention, on frames not resident in host memory. The operations may be specified in an instruction issued by the pageable guests. | 11-14-2013 |
20130311726 | SHARED MEMORY TRANSLATION FACILITY - Aspects include a system, method and computer program product for providing a shared memory translation facility. The method includes receiving a request for access to a memory address from a requestor at a configuration, the receiving at a shared memory translation mechanism. It is determined whether the memory address refers to a shared memory object (SMO), the SMO accessible by a plurality of configurations managed in different zones of memory. Based on determining that the memory address refers to the SMO, it is determined whether the configuration has access to the SMO. Based on determining that the configuration has access to the SMO, the requestor is provided a system absolute address for the SMO and access to the SMO. In this manner direct interchange of data between the configuration and the plurality of configurations is allowed. | 11-21-2013 |
20130311757 | EXTRACT CPU TIME FACILITY - An efficient facility for determining resource usage, such as a processor time used by tasks. The determination is performed on behalf of user applications that do not require a call to operating system services. The facility includes an instruction that determines elapsed time and reports it to the user as a single unit of operation. | 11-21-2013 |
20130339325 | CONSTRAINED TRANSACTION EXECUTION - Constrained transactional processing is provided. A constrained transaction is initiated by execution of a Transaction Begin constrained instruction. The constrained transaction has a number of restrictions associated therewith. Absent violation of a restriction, the constrained transaction is to complete. If an abort condition is encountered, the transaction is re-executed starting at the Transaction Begin instruction. Violation of a restriction may cause an interrupt. | 12-19-2013 |
20130339326 | TRANSACTION BEGIN/END INSTRUCTIONS - A TRANSACTION BEGIN instruction and a TRANSACTION END instruction are provided. The TRANSACTION BEGIN instruction causes either a constrained or nonconstrained transaction to be initiated, depending on a field of the instruction. A constrained transaction has one or more restrictions associated therewith, while a nonconstrained transaction is not limited in the manner of a constrained transaction. The TRANSACTION END instruction ends the transaction started by the TRANSACTION BEGIN instruction. | 12-19-2013 |
20130339328 | SELECTIVELY CONTROLLING INSTRUCTION EXECUTION IN TRANSACTIONAL PROCESSING - Execution of instructions in a transactional environment is selectively controlled. A TRANSACTION BEGIN instruction initiates a transaction and includes controls that selectively indicate whether certain types of instructions are permitted to execute within the transaction. The controls include one or more of an allow access register modification control and an allow floating point operation control. | 12-19-2013 |
20130339329 | TRANSACTIONAL PROCESSING - A transaction is initiated via a transaction begin instruction. During execution of the transaction, the transaction may abort. If the transaction aborts, a determination is made as to the type of transaction. Based on the transaction being a first type of transaction, resuming execution at the transaction begin instruction, and based on the transaction being a second type, resuming execution at an instruction following the transaction begin instruction. Regardless of transaction type, resuming execution includes restoring one or more registers specified in the transaction begin instruction and discarding transactional stores. For one type of transaction, the nonconstrained transaction, the resuming includes storing information in a transaction diagnostic block. | 12-19-2013 |
20130339561 | PROGRAM EVENT RECORDING WITHIN A TRANSACTIONAL ENVIRONMENT - A transaction is initiated within a computing environment, and based on detecting a program event recording event, an interrupt is presented for the transaction. Subsequent to the interrupt, one or more controls are set to inhibit presentation of another interrupt based on detecting another PER event. Thereafter, the transaction is re-executed and PER events detected during execution of the transaction are ignored. | 12-19-2013 |
20130339562 | PROGRAM EVENT RECORDING WITHIN A TRANSACTIONAL ENVIRONMENT - A transaction is initiated within a computing environment, and based on detecting a program event recording event, an interrupt is presented for the transaction. Subsequent to the interrupt, one or more controls are set to inhibit presentation of another interrupt based on detecting another PER event. Thereafter, the transaction is re-executed and PER events detected during execution of the transaction are ignored. | 12-19-2013 |
20130339642 | SAVING/RESTORING SELECTED REGISTERS IN TRANSACTIONAL PROCESSING - A TRANSACTION BEGIN instruction begins execution of a transaction and includes a general register save mask having bits, that when set, indicate registers to be saved in the event the transaction is aborted. At the beginning of the transaction, contents of the registers are saved in memory not accessible to the program, and if the transaction is aborted, the saved contents are copied to the registers. | 12-19-2013 |
20130339656 | Compare and Replace DAT Table Entry - A first and a second operand are compared. If they are equal, the contents of register R | 12-19-2013 |
20130339657 | LOCAL CLEARING CONTROL - A computer implemented instruction is executed. One or more translation table entry locations (TLB) are specified by the instruction. Based on a local-clearing (LC) control specified by the instruction being a first value, the processor selectively clears TLBs in a plurality of the CPUs in a configuration of entries corresponding to the determined translation table entry location. Based on the local-clearing (LC) being a second value, the processor selectively clears only the TLBs of the CPU executing the instruction of entries corresponding to the determined translation table entry location. A computer program product, computer system and computer implemented method are provided. | 12-19-2013 |
20130339669 | NONTRANSACTIONAL STORE INSTRUCTION - A NONTRANSACTIONAL STORE instruction, executed in transactional execution mode, performs stores that are retained, even if a transaction associated with the instruction aborts. The stores include user-specified information that may facilitate debugging of an aborted transaction. | 12-19-2013 |
20130339674 | RESTRICTED INSTRUCTIONS IN TRANSACTIONAL EXECUTION - Restricted instructions are prohibited from execution within a transaction. There are classes of instructions that are restricted regardless of type of transaction: constrained or nonconstrained. There are instructions only restricted in constrained transactions, and there are instructions that are selectively restricted for given transactions based on controls specified on instructions used to initiate the transactions. | 12-19-2013 |
20130339675 | RANDOMIZED TESTING WITHIN TRANSACTIONAL EXECUTION - Task specific diagnostic controls are provided to facilitate the debugging of certain types of abort conditions. The diagnostic controls may be set to cause transactions to be selectively aborted, allowing a transaction to drive its abort handler routine for testing purposes. The controls include, for instance, a transaction diagnostic scope and a transaction diagnostic control. The transaction diagnostic scope indicates when the transaction diagnostic control is to be applied, and the transaction diagnostic control indicates whether transactions are to selectively aborted. | 12-19-2013 |
20130339676 | TRANSACTION ABORT INSTRUCTION - A TRANSACTION ABORT instruction is used to abort a transaction that is executing in a computing environment. The TRANSACTION ABORT instruction includes at least one field used to specify a user-defined abort code that indicates the specific reason for aborting the transaction. Based on executing the TRANSACTION ABORT instruction, a condition code is provided that indicates whether re-execution of the transaction is recommended. | 12-19-2013 |
20130339680 | NONTRANSACTIONAL STORE INSTRUCTION - A NONTRANSACTIONAL STORE instruction, executed in transactional execution mode, performs stores that are retained, even if a transaction associated with the instruction aborts. The stores include user-specified information that may facilitate debugging of an aborted transaction. | 12-19-2013 |
20130339685 | RESTRICTED INSTRUCTIONS IN TRANSACTIONAL EXECUTION - Restricted instructions are prohibited from execution within a transaction. There are classes of instructions that are restricted regardless of type of transaction: constrained or nonconstrained. There are instructions only restricted in constrained transactions, and there are instructions that are selectively restricted for given transactions based on controls specified on instructions used to initiate the transactions. | 12-19-2013 |
20130339687 | PROCESSOR ASSIST FACILITY - An operation is provided to signal a processor that action is to be taken to facilitate execution of a transaction that has aborted one or more times. The operation is specified within an instruction or is itself an instruction. The instruction is executed based on detecting an abort of the transactions, and includes a field indicating how many times the transaction has aborted. The processor uses this information to determine what action is to be taken. | 12-19-2013 |
20130339690 | TRANSACTIONAL EXECUTION BRANCH INDICATIONS - Transactional execution branch indications are placed into one or more transaction diagnostic blocks when a transaction is aborted. Each branch indication specifies whether a branch was taken, as a result of executing a branch instruction within the transaction. As the transaction executes and a branch instruction is encountered, a branch indication is set in a vector indicating whether the branch was taken. Then, if the transaction aborts, the indicators are stored in one or more transaction diagnostic blocks providing a branch history usable in diagnosing the failure. | 12-19-2013 |
20130339702 | PROGRAM INTERRUPTION FILTERING IN TRANSACTIONAL EXECUTION - Program exception conditions cause a transaction to abort and typically result in an interruption in which the operating system obtains control. A program interruption filtering control is provided to selectively present the interrupt. That is, the interrupt from the program exception condition may or may not be presented depending at least on the program interruption filtering control and a transaction class associated with the program exception condition. The program interruption filtering control is provided by a TRANSACTION BEGIN instruction. | 12-19-2013 |
20130339704 | SAVING/RESTORING SELECTED REGISTERS IN TRANSACTIONAL PROCESSING - A TRANSACTION BEGIN instruction begins execution of a transaction and includes a general register save mask having bits, that when set, indicate registers to be saved in the event the transaction is aborted. At the beginning of the transaction, contents of the registers are saved in memory not accessible to the program, and if the transaction is aborted, the saved contents are copied to the registers. | 12-19-2013 |
20130339705 | RANDOMIZED TESTING WITHIN TRANSACTIONAL EXECUTION - Task specific diagnostic controls are provided to facilitate the debugging of certain types of abort conditions. The diagnostic controls may be set to cause transactions to be selectively aborted, allowing a transaction to drive its abort handler routine for testing purposes. The controls include, for instance, a transaction diagnostic scope and a transaction diagnostic control. The transaction diagnostic scope indicates when the transaction diagnostic control is to be applied, and the transaction diagnostic control indicates whether transactions are to selectively aborted. | 12-19-2013 |
20130339706 | PROCESSOR ASSIST FACILITY - An operation is provided to signal a processor that action is to be taken to facilitate execution of a transaction that has aborted one or more times. The operation is specified within an instruction or is itself an instruction. The instruction is executed based on detecting an abort of the transactions, and includes a field indicating how many times the transaction has aborted. The processor uses this information to determine what action is to be taken. | 12-19-2013 |
20130339707 | SELECTIVELY CONTROLLING INSTRUCTION EXECUTION IN TRANSACTIONAL PROCESSING - Execution of instructions in a transactional environment is selectively controlled. A TRANSACTION BEGIN instruction initiates a transaction and includes controls that selectively indicate whether certain types of instructions are permitted to execute within the transaction. The controls include one or more of an allow access register modification control and an allow floating point operation control. | 12-19-2013 |
20130339708 | PROGRAM INTERRUPTION FILTERING IN TRANSACTIONAL EXECUTION - Program exception conditions cause a transaction to abort and typically result in an interruption in which the operating system obtains control. A program interruption filtering control is provided to selectively present the interrupt. That is, the interrupt from the program exception condition may or may not be presented depending at least on the program interruption filtering control and a transaction class associated with the program exception condition. The program interruption filtering control is provided by a TRANSACTION BEGIN instruction. | 12-19-2013 |
20130339709 | TRANSACTION ABORT INSTRUCTION - A TRANSACTION ABORT instruction is used to abort a transaction that is executing in a computing environment. The TRANSACTION ABORT instruction includes at least one field used to specify a user-defined abort code that indicates the specific reason for aborting the transaction. Based on executing the TRANSACTION ABORT instruction, a condition code is provided that indicates whether re-execution of the transaction is recommended. | 12-19-2013 |
20130339796 | TRANSACTIONAL EXECUTION BRANCH INDICATIONS - Transactional execution branch indications are placed into one or more transaction diagnostic blocks when a transaction is aborted. Each branch indication specifies whether a branch was taken, as a result of executing a branch instruction within the transaction. As the transaction executes and a branch instruction is encountered, a branch indication is set in a vector indicating whether the branch was taken. Then, if the transaction aborts, the indicators are stored in one or more transaction diagnostic blocks providing a branch history usable in diagnosing the failure. | 12-19-2013 |
20130339804 | TRANSACTION DIAGNOSTIC BLOCK - When an abort of a transaction occurs, a determination is made as to whether diagnostic information is to be stored in one or more transaction diagnostic blocks (TDBs). There are different types of transaction diagnostic blocks to accept diagnostic information depending on the type of abort and other considerations. As examples, there are a program-specified TDB in which information is stored if a valid TDB address is provided in a transaction begin instruction; a program interruption TDB, which is stored into when the program is aborted due to an interruption; and a program interception TDB, which is stored into when an abort results in an interception. | 12-19-2013 |
20130339806 | TRANSACTION DIAGNOSTIC BLOCK - When an abort of a transaction occurs, a determination is made as to whether diagnostic information is to be stored in one or more transaction diagnostic blocks (TDBs). There are different types of transaction diagnostic blocks to accept diagnostic information depending on the type of abort and other considerations. As examples, there are a program-specified TDB in which information is stored if a valid TDB address is provided in a transaction begin instruction; a program interruption TDB, which is stored into when the program is aborted due to an interruption; and a program interception TDB, which is stored into when an abort results in an interception. | 12-19-2013 |
20130339960 | TRANSACTION BEGIN/END INSTRUCTIONS - A TRANSACTION BEGIN instruction and a TRANSACTION END instruction are provided. The TRANSACTION BEGIN instruction causes either a constrained or nonconstrained transaction to be initiated, depending on a field of the instruction. The TRANSACTION END instruction ends the transaction started by the TRANSACTION BEGIN instruction. | 12-19-2013 |
20130339961 | TRANSACTIONAL PROCESSING - A transaction is initiated via a transaction begin instruction. During execution of the transaction, the transaction may abort. If the transaction aborts, a determination is made as to the type of transaction. Based on the transaction being a first type of transaction, resuming execution at the transaction begin instruction, and based on the transaction being a second type, resuming execution at an instruction following the transaction begin instruction. Regardless of transaction type, resuming execution includes restoring one or more registers specified in the transaction begin instruction and discarding transactional stores. For one type of transaction, the nonconstrained transaction, the resuming includes storing information in a transaction diagnostic block. | 12-19-2013 |
20130339962 | TRANSACTION ABORT PROCESSING - A transaction executing within a computing environment ends prior to completion; i.e., execution is aborted. Pursuant to aborting execution, a hardware transactional execution CPU mode is exited, and one or more of the following is performed: restoring selected registers; committing nontransactional stores on abort; branching to a transaction abort program status word specified location; setting a condition code and/or abort code; and/or preserving diagnostic information. | 12-19-2013 |
20130339963 | TRANSACTION ABORT PROCESSING - A transaction executing within a computing environment ends prior to completion; i.e., execution is aborted. Pursuant to aborting execution, a hardware transactional execution CPU mode is exited, and one or more of the following is performed: restoring selected registers; committing nontransactional stores on abort; branching to a transaction abort program status word specified location; setting a condition code and/or abort code; and/or preserving diagnostic information. | 12-19-2013 |
20130339967 | CONSTRAINED TRANSACTION EXECUTION - Constrained transactional processing is provided. A constrained transaction is initiated by execution of a Transaction Begin constrained instruction. The constrained transaction has a number of restrictions associated therewith. Absent violation of a restriction, the constrained transaction is to complete. If an abort condition is encountered, the transaction is re-executed starting at the Transaction Begin instruction. Violation of a restriction may cause an interrupt. | 12-19-2013 |
20140059321 | Load Page Table Entry Address Instruction Execution Based on an Address Tralsnation Format Control Field - What is provided is a load page table entry address function defined for a machine architecture of a computer system. In one embodiment, a machine instruction is obtained which contains an opcode indicating that a load page table entry address function is to be performed. The machine instruction contains an M field, a first field identifying a first general register, and a second field identifying a second general register. Based on the contents of the M field, an initial origin address of a hierarchy of address translation tables having at least one segment table is obtained. Based on the obtained initial origin address, dynamic address translation is performed until a page table entry is obtained. The page table entry address is saved in the identified first general register. | 02-27-2014 |
20140059330 | PARSING-ENHANCEMENT FACILITY - An instruction for parsing a buffer to be utilized within a data processing system including: an operation code field, the operation code field identifies the instruction; a control field, the control field controls operation of the instruction; and one or more general registers, wherein a first general register stores an argument address, a second general register stores a function code, a third general register stores length of an argument-character buffer, and the fourth of which contains the address of the function-code data structure. | 02-27-2014 |
20140101400 | STORE PERIPHERAL COMPONENT INTERCONNECT (PCI) FUNCTION CONTROLS INSTRUCTION - An instruction is provided that includes an opcode field to identify a store instruction to store in a designated location current values of operational parameters of an adapter function of an adapter; a first field to identify a location, the contents of which include a function handle identifying a handle of the adapter function for which the store instruction is being performed, and an indication of an address space associated with the adapter function identified by the function handle to which the store instruction applies; and a second field to identify the designated location of where a result of the store instruction is to be stored. Execution of the instruction includes obtaining information from a function information block associated with the adapter function; and copying the information from the function information block into the designated location, based on completion of one or more validity checks with one or more predefined results. | 04-10-2014 |
20140115295 | DYNAMIC ADDRESS TRANSLATION WITH FETCH PROTECTION IN AN EMULATED ENVIRONMENT - What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated is first obtained and an initial origin address of a translation table of the hierarchy of translation tables is obtained. Based on the obtained initial origin, a segment table entry is obtained. The segment table entry is configured to contain a format control and access validity fields. If the format control and access validity fields are enabled, the segment table entry further contains an access control field, a fetch protection field, and a segment-frame absolute address. Store operations are permitted only if the access control field matches a program access key provided by any one of a Program Status Word or an operand of a program instruction being emulated. Fetch operations are permitted if the program access key associated with the virtual address is equal to the segment access control field or the fetch protection field is not enabled. | 04-24-2014 |
20140129796 | TRANSLATION OF INPUT/OUTPUT ADDRESSES TO MEMORY ADDRESSES - An address provided in a request issued by an adapter is converted to an address directly usable in accessing system memory. The address includes a plurality of bits, in which the plurality of bits includes a first portion of bits and a second portion of bits. The second portion of bits is used to index into one or more levels of address translation tables to perform the conversion, while the first portion of bits are ignored for the conversion. The first portion of bits are used to validate the address. | 05-08-2014 |
20140164744 | Tracking Multiple Conditions in a General Purpose Register and Instruction Therefor - An operate-and-insert instruction of a program, when executed performs an operation based on one or more operands, results of an instruction specified test of the operation performed are stored in an instruction specified location of an instruction specified general register. The instruction specified general register is therefore able to hold results of many operate-and-insert instructions. The program can then use non-branch type instructions to evaluate conditions saved in the register, thus avoiding the performance penalty of branch instructions. | 06-12-2014 |
20140164746 | Tracking Multiple Conditions in a General Purpose Register and Instruction Therefor - An operate-and-insert instruction of a program, when executed performs an operation based on one or more operands, results of an instruction specified test of the operation performed are stored in an instruction specified location of an instruction specified general register. The instruction specified general register is therefore able to hold results of many operate-and-insert instructions. The program can then use non-branch type instructions to evaluate conditions saved in the register, thus avoiding the performance penalty of branch instructions. | 06-12-2014 |
20140181360 | Creating A Dynamic Address Translation With Translation Exception Qualifier - An enhanced dynamic address translation facility product is created such that, in one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. Dynamic address translation of the virtual address proceeds. In response to a translation interruption having occurred during dynamic address translation, bits are stored in a translation exception qualifier (TXQ) field to indicate that the exception was either a host DAT exception having occurred while running a host program or a host DAT exception having occurred while running a guest program. The TXQ is further capable of indicating that the exception was associated with a host virtual address derived from a guest page frame real address or a guest segment frame absolute address. The TXQ is further capable of indicating that a larger or smaller host frame size is preferred to back a guest frame. | 06-26-2014 |
20140188452 | Emulation of a Dynamic Address Translation With Change Record Override on a Machine of Another Architecture - A translation table entry contains a change recording override field for controlling whether a change bit is to be set on a store or not. Each 4K byte block of main storage has an associated storage key comprising a change bit. The change recording override field controls whether change bit of the storage key associated with the desired 4K byte block of main storage is set to 1 for a store operation. | 07-03-2014 |
20140208040 | Creating a Program Product or System for Executing an Instruction for Pre-Fetching Data and Releasing Cache Lines - Systems and Program Products are created to execute a prefetch data machine instruction having an M field performs a function on a cache line of data specifying an address of an operand. The operation comprises either prefetching a cache line of data from memory to a cache or reducing the access ownership of store and fetch or fetch only of the cache line in the cache or a combination thereof. The address of the operand is either based on a register value or the program counter value pointing to the prefetch data machine instruction. | 07-24-2014 |
20140270162 | INSTRUCTION FOR PERFORMING A PSEUDORANDOM NUMBER GENERATE OPERATION - A machine instruction is provided that includes an opcode field to provide an opcode, the opcode to identify a perform pseudorandom number operation, and a register field to be used to identify a register, the register to specify a location in memory of a first operand to be used. The machine instruction is executed, and execution includes for each block of memory of one or more blocks of memory of the first operand, generating a hash value using a 512 bit secure hash technique and at least one seed value of a parameter block of the machine instruction; and storing at least a portion of the generated hash value in a corresponding block of memory of the first operand, the generated hash value being at least a portion of a pseudorandom number. | 09-18-2014 |
20140280414 | INSTRUCTION FOR PERFORMING A PSEUDORANDOM NUMBER SEED OPERATION - A machine instruction is provided that includes an opcode field to provide an opcode, the opcode to identify a perform pseudorandom number operation, and a register field to be used to identify a register, the register to specify a location in memory of a second operand to be used. The machine instruction is executed, and execution includes obtaining a modifier field of a register associated with the machine instruction; based on the modifier field having a first value, performing a deterministic pseudorandom number seed operation, which includes obtaining seed material based on information stored in the second operand; using a 512 bit secure hash technique and the seed material to provide one or more seed values; and storing the one or more seed values in a parameter block. | 09-18-2014 |
20140380013 | EXECUTION OF A PERFORM FRAME MANAGEMENT FUNCTION INSTRUCTION - Optimizations are provided for frame management operations, including a clear operation and/or a set storage key operation, requested by pageable guests. The operations are performed, absent host intervention, on frames not resident in host memory. The operations may be specified in an instruction issued by the pageable guests. | 12-25-2014 |
20150019814 | Extract Target Cache Attribute Facility and Instruction Therefore - A facility and cache machine instruction of a computer architecture for specifying a target cache cache-level and a target cache attribute of interest for obtaining a cache attribute of one or more target caches. The requested cache attribute of the target cache(s) is saved in a register. | 01-15-2015 |
20150049870 | INSTRUCTION FOR PERFORMING A PSEUDORANDOM NUMBER GENERATE OPERATION - A machine instruction is provided that includes an opcode field to provide an opcode, the opcode to identify a perform pseudorandom number operation, and a register field to be used to identify a register, the register to specify a location in memory of a first operand to be used. The machine instruction is executed, and execution includes for each block of memory of one or more blocks of memory of the first operand, generating a hash value using a 512 bit secure hash technique and at least one seed value of a parameter block of the machine instruction; and storing at least a portion of the generated hash value in a corresponding block of memory of the first operand, the generated hash value being at least a portion of a pseudorandom number. | 02-19-2015 |
20150052336 | SELECTIVELY CONTROLLING INSTRUCTION EXECUTION IN TRANSACTIONAL PROCESSING - Execution of instructions in a transactional environment is selectively controlled. A TRANSACTION BEGIN instruction initiates a transaction and includes controls that selectively indicate whether certain types of instructions are permitted to execute within the transaction. The controls include one or more of an allow access register modification control and an allow floating point operation control. | 02-19-2015 |
20150052337 | SELECTIVELY CONTROLLING INSTRUCTION EXECUTION IN TRANSACTIONAL PROCESSING - Execution of instructions in a transactional environment is selectively controlled. A TRANSACTION BEGIN instruction initiates a transaction and includes controls that selectively indicate whether certain types of instructions are permitted to execute within the transaction. The controls include one or more of an allow access register modification control and an allow floating point operation control. | 02-19-2015 |
20150081751 | INSTRUCTION FOR PERFORMING A PSEUDORANDOM NUMBER SEED OPERATION - A machine instruction is provided that includes an opcode field to provide an opcode, the opcode to identify a perform pseudorandom number operation, and a register field to be used to identify a register, the register to specify a location in memory of a second operand to be used. The machine instruction is executed, and execution includes obtaining a modifier field of a register associated with the machine instruction; based on the modifier field having a first value, performing a deterministic pseudorandom number seed operation, which includes obtaining seed material based on information stored in the second operand; using a 512 bit secure hash technique and the seed material to provide one or more seed values; and storing the one or more seed values in a parameter block. | 03-19-2015 |