Patent application number | Description | Published |
20110027286 | High Affinity Human Antibodies to Human Angiopoietin-2 - The present invention provides antibodies that bind to angiopoietin-2 (Ang-2) and methods of using same. According to certain embodiments of the invention, the antibodies are fully human antibodies that bind to human Ang-2. The antibodies of the invention are useful, inter alia, for the treatment of diseases and disorders associated with one or more Ang-2 biological activities including angiogenesis. | 02-03-2011 |
20120189635 | Methods for Treating or Preventing Malaria by Administering an Antibody that Specifically Binds Angiopoietin-2 (Ang-2) - The present invention provides methods for treating or preventing malaria by administering to a patient in need thereof a pharmaceutical composition comprising an antibody that specifically binds human angiopoietin-2 (Ang-2). | 07-26-2012 |
20130084297 | Anti-ErbB3 Antibodies and Uses Thereof - The present invention provides antibodies that bind to ErbB3 and methods of using same. According to certain embodiments of the invention, the antibodies are fully human antibodies that bind to human ErbB3. In certain embodiments, the antibodies of the present invention block the interaction of ErbB3 with an ErbB3 ligand such as neuregulin 1. The antibodies of the invention are useful for the treatment of various cancers. | 04-04-2013 |
20130129722 | Methods for Treating Cancer by Administering an Anti-Ang-2 Antibody - The present invention provides antibodies that bind to angiopoietin-2 (Ang-2) and methods of using same. According to certain embodiments of the invention, the antibodies are fully human antibodies that bind to human Ang-2. The antibodies of the invention are useful, inter alia, for the treatment of diseases and disorders associated with one or more Ang-2 biological activities including angiogenesis. | 05-23-2013 |
20130344093 | Anti-EGFR Antibodies and Uses Thereof - The present invention provides antibodies that bind to EGFR and methods of using same. According to certain embodiments of the invention, the antibodies are fully human antibodies that bind to human EGFR with high affinity. In certain embodiments, the antibodies of the present invention are capable of inhibiting the growth of tumor cells expressing high levels of EGFR and/or inducing antibody-dependent cell-mediated cytotoxicity (ADCC) of such cells. The antibodies of the invention are useful for the treatment of various cancers as well as other EGFR-related disorders. | 12-26-2013 |
20140072563 | Methods and Compositions Comprising a Combination of an Anti-ErbB3 Antibody and an Anti-EGFR Antibody - The present invention provides pharmaceutical compositions comprising an anti-ErbB3 antibody and an anti-EGFR antibody, and methods of use thereof. The compositions and methods of the present invention are useful for the treatment of various cancers and other diseases and disorders. | 03-13-2014 |
20140112930 | Methods for Treating or Preventing Malaria by Administering an Antibody that Specifically Binds Angiopoietin-2 (Ang-2) - The present invention provides methods for treating or preventing malaria by administering to a patient in need thereof a pharmaceutical composition comprising an antibody that specifically binds human angiopoietin-2 (Ang-2). | 04-24-2014 |
20140308279 | Anti-ErbB3 Antibodies and Uses Thereof - The present invention provides antibodies that bind to ErbB3 and methods of using same. According to certain embodiments of the invention, the antibodies are fully human antibodies that bind to human ErbB3. In certain embodiments, the antibodies of the present invention block the interaction of ErbB3 with an ErbB3 ligand such as neuregulin 1. The antibodies of the invention are useful for the treatment of various cancers. | 10-16-2014 |
Patent application number | Description | Published |
20080222640 | Prediction Based Priority Scheduling - Systems and methods are provided that schedule task requests within a computing system based upon the history of task requests. The history of task requests can be represented by a historical log that monitors the receipt of high priority task request submissions over time. This historical log in combination with other user defined scheduling rules is used to schedule the task requests. Task requests in the computer system are maintained in a list that can be divided into a hierarchy of queues differentiated by the level of priority associated with the task requests contained within that queue. The user-defined scheduling rules give scheduling priority to the higher priority task requests, and the historical log is used to predict subsequent submissions of high priority task requests so that lower priority task requests that would interfere with the higher priority task requests will be delayed or will not be scheduled for processing. | 09-11-2008 |
20110276762 | COORDINATED WRITEBACK OF DIRTY CACHELINES - A data processing system includes a processor core and a cache memory hierarchy coupled to the processor core. The cache memory hierarchy includes at least one upper level cache and a lowest level cache. A memory controller is coupled to the lowest level cache and to a system memory and includes a physical write queue from which the memory controller writes data to the system memory. The memory controller initiates accesses to the lowest level cache to place into the physical write queue selected cachelines having spatial locality with data present in the physical write queue. | 11-10-2011 |
20110276763 | MEMORY BUS WRITE PRIORITIZATION - A data processing system includes a multi-level cache hierarchy including a lowest level cache, a processor core coupled to the multi-level cache hierarchy, and a memory controller coupled to the lowest level cache and to a memory bus of a system memory. The memory controller includes a physical read queue that buffers data read from the system memory via the memory bus and a physical write queue that buffers data to be written to the system memory via the memory bus. The memory controller grants priority to write operations over read operations on the memory bus based upon a number of dirty cachelines in the lowest level cache memory. | 11-10-2011 |
20120180060 | PREDICTION BASED PRIORITY SCHEDULING - Systems and methods are provided that schedule task requests within a computing system based upon the history of task requests. The history of task requests can be represented by a historical log that monitors the receipt of high priority task request submissions over time. This historical log in combination with other user defined scheduling rules is used to schedule the task requests. Task requests in the computer system are maintained in a list that can be divided into a hierarchy of queues differentiated by the level of priority associated with the task requests contained within that queue. The user-defined scheduling rules give scheduling priority to the higher priority task requests, and the historical log is used to predict subsequent submissions of high priority task requests so that lower priority task requests that would interfere with the higher priority task requests will be delayed or will not be scheduled for processing. | 07-12-2012 |
20120203968 | COORDINATED WRITEBACK OF DIRTY CACHELINES - A data processing system includes a processor core and a cache memory hierarchy coupled to the processor core. The cache memory hierarchy includes at least one upper level cache and a lowest level cache. A memory controller is coupled to the lowest level cache and to a system memory and includes a physical write queue from which the memory controller writes data to the system memory. The memory controller initiates accesses to the lowest level cache to place into the physical write queue selected cachelines having spatial locality with data present in the physical write queue. | 08-09-2012 |
20120203969 | MEMORY BUS WRITE PRIORITIZATION - A data processing system includes a multi-level cache hierarchy including a lowest level cache, a processor core coupled to the multi-level cache hierarchy, and a memory controller coupled to the lowest level cache and to a memory bus of a system memory. The memory controller includes a physical read queue that buffers data read from the system memory via the memory bus and a physical write queue that buffers data to be written to the system memory via the memory bus. The memory controller grants priority to write operations over read operations on the memory bus based upon a number of dirty cachelines in the lowest level cache memory. | 08-09-2012 |
20130019083 | Redundant Transactional MemoryAANM Cain, III; Harold W.AACI HartsdaleAAST NYAACO USAAGP Cain, III; Harold W. Hartsdale NY USAANM Daly; David M.AACI Croton on HudsonAAST NYAACO USAAGP Daly; David M. Croton on Hudson NY USAANM Ekanadham; KattamuriAACI Mohegan LakeAAST NYAACO USAAGP Ekanadham; Kattamuri Mohegan Lake NY USAANM Huang; Michael C.AACI RochesterAAST NYAACO USAAGP Huang; Michael C. Rochester NY USAANM Moreira; Jose E.AACI IrvingtonAAST NYAACO USAAGP Moreira; Jose E. Irvington NY USAANM Serrano; Mauricio J.AACI BronxAAST NYAACO USAAGP Serrano; Mauricio J. Bronx NY US - A mechanism is provided for redundant execution of a set of instructions. A redundant execution begin (rbegin) instruction to be executed by a first hardware thread on the first processor is identified in the set of instructions. The set of instructions immediately after the rbegin instruction are executed on the first hardware thread and on a second hardware thread. Responsive to both the first processor and the second processor ending execution of the set of instructions, responsive to a first set of cache lines in a first speculative store matching a second set of cache lines in a second speculative store, and responsive to a first set of register states in a first status register matching a second set of register states in a second status register, dirty lines in the first speculative store are committed thereby committing a redundant transaction state to an architectural state. | 01-17-2013 |
20130019085 | Efficient Recombining for Dual Path ExecutionAANM Cain, III; Harold W.AACI HartsdaleAAST NYAACO USAAGP Cain, III; Harold W. Hartsdale NY USAANM Daly; David M.AACI Croton on HudsonAAST NYAACO USAAGP Daly; David M. Croton on Hudson NY USAANM Huang; Michael C.AACI RochesterAAST NYAACO USAAGP Huang; Michael C. Rochester NY USAANM Moreira; Jose E.AACI IrvingtonAAST NYAACO USAAGP Moreira; Jose E. Irvington NY USAANM Park; ILAACI SeoulAACO KRAAGP Park; IL Seoul KR - A mechanism is provided for reducing a penalty for executing a correct branch of a branch instruction. An execution unit in a processor of a data processing system executes a first branch of the branch instruction from a main thread of a processor and executes a second branch of the branch instruction from an assist thread of the processor. The execution unit determines whether the main thread is a correct branch of the branch instruction or the assist thread is the correct branch of the branch instruction. Responsive to the assist thread being the correct branch of the branch instruction, the execution unit pauses execution of the branch instruction on both the main thread and the assist thread. The execution unit then properly inherits a context of the main thread in order that execution of the second branch may continue. | 01-17-2013 |
20130151777 | Dynamic Inclusive Policy in a Hybrid Cache Hierarchy Using Hit Rate - A mechanism is provided for dynamic cache allocation using a cache hit rate. A first cache hit rate is monitored in a first subset utilizing a first allocation policy of N sets of a lower level cache. A second cache hit rate is also monitored in a second subset utilizing a second allocation policy different from the first allocation policy of the N sets of the lower level cache. A periodic comparison of the first cache hit rate to the second cache hit rate is made to identify a third allocation policy for a third subset of the N-sets of the lower level cache. The third allocation policy for the third subset is then periodically adjusted to at least one of the first allocation policy or the second allocation policy based on the comparison of the first cache hit rate to the second cache hit rate. | 06-13-2013 |
20130151778 | Dynamic Inclusive Policy in a Hybrid Cache Hierarchy Using Bandwidth - A mechanism is provided for dynamic cache allocation using bandwidth. A bandwidth between a higher level cache and a lower level cache is monitored. Responsive to bandwidth usage between the higher level cache and the lower level cache being below a predetermined low bandwidth threshold, the higher level cache and the lower level cache are set to operate in accordance with a first allocation policy. Responsive to bandwidth usage between the higher level cache and the lower level cache being above a predetermined high bandwidth threshold, the higher level cache and the lower level cache are set to operate in accordance with a second allocation policy. | 06-13-2013 |
20130151779 | Weighted History Allocation Predictor Algorithm in a Hybrid Cache - A mechanism is provided for weighted history allocation prediction. For each member in a plurality of members in a lower level cache, an associated reference counter is initialized to an initial value based on an operation type that caused data to be allocated to a member location of the member. For each access to the member in the lower level cache, the associated reference counter is incremented. Responsive to a new allocation of data to the lower level cache and responsive to the new allocation of data requiring the victimization of another member in the lower level cache, a member of the lower level cache is identified that has a lowest reference count value in its associated reference counter. The member with the lowest reference count value in its associated reference counter is then evicted. | 06-13-2013 |
20130151780 | Weighted History Allocation Predictor Algorithm in a Hybrid Cache - A mechanism is provided for weighted history allocation prediction. For each member in a plurality of members in a lower level cache, an associated reference counter is initialized to an initial value based on an operation type that caused data to be allocated to a member location of the member. For each access to the member in the lower level cache, the associated reference counter is incremented. Responsive to a new allocation of data to the lower level cache and responsive to the new allocation of data requiring the victimization of another member in the lower level cache, a member of the lower level cache is identified that has a lowest reference count value in its associated reference counter. The member with the lowest reference count value in its associated reference counter is then evicted. | 06-13-2013 |
20130227582 | Prediction Based Priority Scheduling - Systems and methods are provided that schedule task requests within a computing system based upon the history of task requests. The history of task requests can be represented by a historical log that monitors the receipt of high priority task request submissions over time. This historical log in combination with other user defined scheduling rules is used to schedule the task requests. Task requests in the computer system are maintained in a list that can be divided into a hierarchy of queues differentiated by the level of priority associated with the task requests contained within that queue. The user-defined scheduling rules give scheduling priority to the higher priority task requests, and the historical log is used to predict subsequent submissions of high priority task requests so that lower priority task requests that would interfere with the higher priority task requests will be delayed or will not be scheduled for processing. | 08-29-2013 |
20140063983 | Error Detection And Correction In A Memory System - A method including providing a plurality of random access memories having at least a first region, a second region and a third region; storing protected data on the first region on at least two of the random access memories, where the protected data is stored distributed among the at least two random access memories of the first region; storing parity information for the protected data on the second region on at least a third one of the random access memories; and storing unprotected data on the third region. | 03-06-2014 |
20140068319 | Error Detection And Correction In A Memory System - An apparatus including at least one memory controller; and a plurality of random access memories, where the at least one memory controller is configured to allocate the plurality of random access memories among at least a first portion, a second portion and a third portion. The first portion is configured to store protected data. The second portion is configured to store parity information for the stored protected data. The third portion is configured to store unprotected data. | 03-06-2014 |
20140095716 | MAXIMIZING RESOURCES IN A MULTI-APPLICATION PROCESSING ENVIRONEMENT - Aspects of the present invention provide a solution for maximizing server site resources in a server network. In an embodiment, an application signature is collected for an application. This application signature includes a representation of operating characteristics of the application. The application signature is compared with application signatures collected from other applications in the server network. Based on the comparison, the application is assigned for execution to a server site that hosts a group of applications that have similar application signatures to that of the application. | 04-03-2014 |
20140095718 | MAXIMIZING RESOURCES IN A MULTI-APPLICATION PROCESSING ENVIRONMENT - Aspects of the present invention provide a solution for maximizing server site resources in a server network. In an embodiment, an application signature is collected for an application. This application signature includes a representation of operating characteristics of the application. The application signature is compared with application signatures collected from other applications in the server network. Based on the comparison, the application is assigned for execution to a server site that hosts a group of applications that have similar application signatures to that of the application. | 04-03-2014 |
20140281710 | TRANSACTIONS FOR CHECKPOINTING AND REVERSE EXECUTION - A method of backstepping through a program execution includes dividing the program execution into a plurality of epochs, wherein the program execution is performed by an active core, determining, during a subsequent epoch of the plurality of epochs, that a rollback is to be performed, performing the rollback including re-executing a previous epoch of the plurality of epochs, wherein the previous epoch includes one or more instructions of the program execution stored by a checkpointing core, and adjusting a granularity of the plurality of epochs according to a frequency of the rollback. | 09-18-2014 |
20150046752 | Redundant Transactions for Detection of Timing Sensitive Errors - A method for detecting a software-race condition in a program includes copying a state of a transaction of the program from a first core of a multi-core processor to at least one additional core of the multi-core processor, running the transaction, redundantly, on the first core and the at least one additional core given the state, outputting a result of the first core and the at least one additional core, and detecting a difference in the results between the first core and the at least one additional core, wherein the difference indicates the software-race condition. | 02-12-2015 |
20150046758 | REDUNDANT TRANSACTIONS FOR SYSTEM TEST - A method for detecting errors in hardware including running a transaction on a plurality of cores, wherein each of the cores runs a respective copy of the transaction, synchronizing the transaction on the cores, comparing results of the transaction on the cores, and determining an error in one or more of the cores. | 02-12-2015 |
Patent application number | Description | Published |
20110279902 | SYSTEM AND METHOD FOR REDUCING ENVIRONMENTAL EFFECT ON VERIFYING CONTENT DISPLAYED ON AN ELECTRONIC VISUAL DISPLAY - An electronic display may include a screen including an outer perimeter and front surface. A housing may include a trim ring that surrounds the outer perimeter and extends in front of the front surface of the screen. An optical sensor shield may be is positioned at least in part in front of the front surface of the screen. An optical sensor may be disposed between the optical sensor shield and the screen to reduce the ability for ambient light to illuminate the optical sensor. | 11-17-2011 |
20110286152 | MECHANICAL AND ELECTRICAL SYSTEM FOR POWERING SHELF-EDGE ELECTRONIC DISPLAYS IN A RETAIL ENVIRONMENT - A power bus system and method for providing electrical power to an electronic device at a shelf of a gondola in a retail environment may include a power track including a structure member and at least two electrical conductors. The structure member may be positioned along a bottom surface of the shelf of the gondola. A shuttle may be coupled to the power track, and configured (i) to be positionable along the power track and (ii) to conduct electricity from the at least two electrical conductors to the electronic device. A box holder may be connected to the shuttle, and be configured to physically support the electronic device. | 11-24-2011 |
20110309041 | MULTI-VIEW ELECTRONIC DISPLAYS IN RETAIL ENVIRONMENTS - A system and method configuring an electronic fixture display assembly may include providing a support extension member. At least three extension arms may be supported from the support extension member, where the at least three extension arms may be configured (i) to support respective electronic displays, and (i) to be rotatably positionable relative to the support extension member. | 12-22-2011 |
20120019393 | SYSTEM AND METHOD FOR TRACKING CARTS IN A RETAIL ENVIRONMENT - A system and method for tracking a shopping cart in a retail store may include communicating signals into the pathways from multiple locations, where the signals may include identifiers indicative of location of respective signals. The communicated signals with the identifiers may be received, and the identifiers may be recorded. The recorded data may be processed to determine a path taken by the shopping cart through the retail store. The path of the shopping cart taken through the retail store may be presented to a user. | 01-26-2012 |
20120120497 | APPARATUS FOR COVERING AN OPTICAL SENSOR DISPOSED IN FRONT OF AN ELECTRONIC DISPLAY FOR SENSING A VISUAL VERIFICATION SIGNAL - An electronic display including a screen including an outer perimeter and front surface. A housing including a screen frame may surround the outer perimeter, and extend in front of the front surface of the screen. An optical sensor shield may be positioned at least in part in the screen frame and extend in front of the front surface of the screen. | 05-17-2012 |
20120176733 | POWER OUTLET BOX FOR ELECTRONIC DISPLAYS IN A RETAIL ENVIRONMENT - A power outlet box for housing electronics and powering electronic displays suspended in a retail environment may include a first housing portion including a first set of vertical support features and a second set of vertical support features. A second housing portion may include a third set of vertical support features and a fourth set of vertical support features. The power outlet box may have (i) a closed configuration when the first and third sets of vertical support features are aligned and (ii) an open configuration when the second and fourth set of vertical support features are in contact with one another. The second set of vertical support features may be adapted to support the fourth set of vertical support features when the power outlet box is in the open configuration. A power supply device may be fixedly positioned within the power outlet box when in the closed configuration. | 07-12-2012 |
Patent application number | Description | Published |
20080214038 | CONNECTOR ASSEMBLY - In one exemplary embodiment, an electrical connector includes a D-subminiature connector assembly including a base, a D-subminiature connector mounted to the base, and a terminal block mounted to the base and spaced from the D-subminiature connector. The terminal block has individual terminal openings for receiving wires associated with an electrical cable. Each terminal opening is defined by an axis that intersects a plane containing the base. The electrical connector also includes a hood receiving and holding the D-subminiature connector assembly. | 09-04-2008 |
20090017675 | STEREO CONNECTOR ASSEMBLY WITH REAR TERMINAL BLOCK - In one exemplary embodiment, a miniature stereo jack assembly includes an internal sub-assembly including a printed circuit board, a stereo jack component for receiving a stereo jack, and a terminal block. The stereo jack component is disposed against and in electrical contact with a first surface of the printed circuit board and the terminal block is disposed against and in electrical contact with a second surface of the printed circuit board. The stereo jack assembly also includes a housing that surrounds the internal sub-assembly. The housing has a first portion that has external threads for mating with a fastener that is used to attach the stereo jack assembly to a surface, such as a wall plate, panel, chassis or box. | 01-15-2009 |
20090035987 | CONNECTOR ASSEMBLY - A connector, such as an S-video connector, according to one embodiment includes an internal connector assembly and a housing. The internal connector assembly includes a pin connector that includes a plurality of pin contacts that are surrounded at least in part by a pin housing and a flexible printed circuit board that is electrically connected to the pin contacts. The connector assembly also includes a terminal block that is electrically connected to the pin contacts through the printed circuit board. The terminal block has terminal openings for receiving conductive elements associated with a cable to permit an electrical connection between the cable and the pin contacts. The housing has an inner compartment that receives and holds the internal connector assembly in non-rotatable manner, with the pin housing and pin contacts extending beyond one end of the housing. | 02-05-2009 |
20090186493 | MULTI-POSITION MIXED-CONTACT CONNECTOR WITH SEPARABLE MODULAR RJ-45 COUPLER - A connector system includes a first connector part including at least one first cavity formed therein. The first connector part has at least one first contact. The system includes a second connector part including at least one second cavity formed therein. The second connector part is complementary to the first connector part such that when the first and second connector parts mate together. The first and second cavities are at least partially aligned and the first and second contacts are placed in electrical contact with one another. The system also includes a printed circuit board sub-assembly including a printed circuit board, a plurality of spring contacts that are electrically coupled to the printed circuit board. The sub-assembly has a stabilizing element that includes a plurality of vanes with the spring contacts being disposed between the vanes. The sub-assembly is securely disposed within the first connector part such that the spring contacts are accessible along both a front surface thereof and along an opposite second surface thereof. | 07-23-2009 |
20090221187 | CONNECTOR ASSEMBLY - In one exemplary embodiment, an electrical connector including a D-subminiature connector assembly that includes a base; a D-subminiature connector mounted to the base; and a header mounted to the base. The header has a plurality of internal contacts and an open rear end for receiving a receptacle that includes conductive contacts that are electrically connected to the internal contacts when the receptacle is fully inserted into and engaged with the header. | 09-03-2009 |
20110068259 | APPARATUS AND METHOD FOR SENSING LIGHT PRODUCED BY PIXELS ON AN ELECTRONIC DISPLAY - An optical sensor package may include a chip carrier including a surface having edges defining corners. An optical sensor may be connected to the surface of the chip carrier and be positioned closer to one of the corners than any of the other corners. | 03-24-2011 |
Patent application number | Description | Published |
20080249221 | POLYMERIC ADHESIVE INCLUDING NANOPARTICLE FILLER - Disclosed is a novel polymeric nanoparticle adhesive composite including a nanoparticle filler and method for the production thereof. More particularly, the disclosure describes the use of nanoparticle fillers, including a novel halloysite nanoparticle filler which utilizes generally cylindrical or tubular nanoparticles (e.g. rolled scroll-like shape). The filler is effectively employed in a polymer nanoparticle adhesive composite, containing the halloysite nanoparticle or other equivalent naturally occurring nanotubular filler, in which the advantages of the nanoparticle filler are provided (e.g., reinforcement, flame retardant, etc.) while maintaining or improving mechanical performance of the adhesive composite (e.g., adhesive strength and tack) | 10-09-2008 |
20090005489 | NANOCLAY FILLED FLUOROPOLYMER DISPERSIONS AND METHOD OF FORMING SAME - Disclosed herein is an aqueous dispersion and a method for making said dispersion, and more particularly, a dispersion that comprises a nanoclay such as a tubular clay (e.g. halloysite), a fluoropolymer and the requisite surfactants for dispersion stability. In various embodiments, and applications thereof to substrates and the like, the dispersion improves the manufacturability of articles that include coating fluoropolymer dispersions while retaining the unique properties of the fluoropolymer coating. | 01-01-2009 |
20090326133 | FIRE AND FLAME RETARDANT POLYMER COMPOSITES - Disclosed are materials and processes for obtaining improved resistance to fire and flame for polymer composites, using a flame and fire retardant system comprising a tubular clay. Halloysite is an example of such a clay and it can be used either alone or in combination with other chemicals. The tubular clays are advantaged over common platy clays for this application in that they do not require large amounts of organic compatibilizers, which may degrade the properties of the composite or require tedious process steps. The tubular clay can function alone or synergistically with other flame retardants, particularly organic flame retardants. | 12-31-2009 |
20120129999 | NANOCOMPOSITE INCLUDING HEAT-TREATED CLAY AND POLYMER - Disclosed are systems and methods for producing, and a composite including, a roasted aluminosilicate (e.g., halloysite). A uniform dispersion of an aluminosilicate can be obtained using roasted halloysite clay and subsequently combining it with a polymer in a melt mixing system to produce a composite. | 05-24-2012 |
Patent application number | Description | Published |
20080220004 | Use of VEGF inhibitors for treatment of eye disorders - Modified chimeric polypeptides with improved pharmacokinetics and improved tissue penetration are disclosed useful for treating eye disorders, including age-related macular degeneration and diabetic retinopathy. | 09-11-2008 |
20090062200 | VEGF-Binding Fusion Proteins and Therapeutic Uses Thereof - Nucleic acid molecules encoding fusion proteins which bind and inhibit vascular endothelial growth factor (VEGF). The VEGF-binding fusion proteins are therapeutically useful for treating VEGF-associated conditions and diseases, and are specifically designed for local administration to specific organs, tissues, and/or cells. | 03-05-2009 |
20090069235 | IGF-1 Fusion Polypeptides and Therapeutic Uses Thereof - A fusion protein comprising at least one IGF1 variant component and a fusion component (F), and, optionally, a signal sequence, exhibiting improved stability relative to the native IGF1 or IGF2 polypeptide. The fusion component (F) may be a multimerizing component, a targeting ligand, or another active or therapeutic compound. IGF1 variants were shown to have improved ability to induce skeletal muscle hypertrophy relative to native IGF1. | 03-12-2009 |
20100087632 | VEGF-Binding Fusion Proteins and Therapeutic Uses Thereof - Fusion proteins which bind and inhibit vascular endothelial growth factor (VEGF). The VEGF-binding fusion proteins are therapeutically useful for treating VEGF-associated conditions and diseases, and are specifically designed for local administration to specific organs, tissues, and/or cells. | 04-08-2010 |
20110020342 | IGF-1 FUSION POLYPEPTIDES AND THERAPEUTIC USES THEREOF - A fusion protein comprising at least one IGF1 variant component and a fusion component (F), and, optionally, a signal sequence, exhibits improved stability relative to the native IGF1 or IGF2 polypeptide. The fusion component (F) may be a multimerizing component, such as an immunoglobulin domain, in particular, the Fc domain of IgG or a heavy chain of IgG. IGF1 variants were shown to have improved ability to increase muscle mass in a subject suffering from muscle atrophy caused by cachexia, immobilization, aging, chronic disease, cancer, hereditary condition, an atrophy-causing agent, and the like. IGF1 variants are also effective in decreasing blood glucose in a subject suffering from diabetes or hyperglycemia. | 01-27-2011 |
20120195896 | IGF-1 FUSION POLYPEPTIDES AND THERAPEUTIC USES THEREOF - A fusion protein comprising at least one IGF1 variant component and a fusion component (F), and, optionally, a signal sequence, exhibits improved stability relative to the native IGF1 or IGF2 polypeptide. The fusion component (F) may be a multimerizing component, such as an immunoglobulin domain, in particular, the Fc domain of IgG or a heavy chain of IgG. IGF1 variants were shown to have improved ability to increase muscle mass in a subject suffering from muscle atrophy caused by cachexia, immobilization, aging, chronic disease, cancer, hereditary condition, an atrophy-causing agent, and the like. IGF1 variants are also effective in decreasing blood glucose in a subject suffering from diabetes or hyperglycemia. | 08-02-2012 |