Patent application number | Description | Published |
20090015540 | PORTABLE TERMINAL - Visibility of a transmissive liquid crystal display panel is improved in outside and inside environments. A liquid crystal display | 01-15-2009 |
20090186916 | AMINOINDANE DERIVATIVE OR SALT THEREOF - Provided is a compound that is an NMDA receptor antagonist having a broader safety margin, and is useful as an agent for treating or preventing Alzheimer's disease, cerebrovascular dementia, Parkinson's disease, ischemic apoplexy, or pain. | 07-23-2009 |
20100122108 | ARITHMETIC UNIT AND ARITHMETIC PROCESSING METHOD - There is a need for providing a battery-less integrated circuit (IC) card capable of operating in accordance with a contact usage or a non-contact usage, preventing coprocessor throughput from degrading despite a decreased clock frequency for reduced power consumption under non-contact usage, and ensuring high-speed processing under non-contact usage. A dual interface card is a battery-less IC card capable of operating in accordance with a contact usage or a non-contact usage. The dual interface card operates at a high clock under contact usage and at a low clock under non-contact usage. A targeted operation comprises a plurality of different basic operations. The dual interface card comprises a basic arithmetic circuit group. Under the contact usage, the basic arithmetic circuit group performs one basic operation of the targeted operation at one cycle. Under the non-contact usage, the basic arithmetic circuit group sequentially performs at least two basic operations of the targeted operation at one cycle. | 05-13-2010 |
20100152165 | CARBOXYLIC ACID DERIVATIVES - [Problem] To provide a pharmaceutical, particularly a compound which can be used as an insulin secretion promoter or a preventive or therapeutic agent for diabetes mellitus and the like diseases in which GPR40 is concerned. | 06-17-2010 |
20110194321 | DC POWER SUPPLY APPARATUS - A DC power supply apparatus comprising: a rectifying circuit including, a first rectifying portion, a second rectifying portion, a third rectifying portion and a fourth rectifying portion; a current detection portion; a first switching portion; and a second switching portion; wherein each of the first rectifying portion cooperatively operating with the first switching portion and the second rectifying portion cooperatively operating with the second switching portion is a semiconductor element which is formed by using a Schottky junction formed between silicon carbide or gallium nitride and metal and has a withstanding voltage property with respect to a voltage of an AC power supply. | 08-11-2011 |
20120184520 | GLYCINE COMPOUND | 07-19-2012 |
20120198211 | ARITHMETIC UNIT AND ARITHMETIC PROCESSING METHOD FOR OPERATING WITH HIGHER AND LOWER CLOCK FREQUENCIES - There is a need for providing a battery-less integrated circuit (IC) card capable of operating in accordance with a contact usage or a non-contact usage, preventing coprocessor throughput from degrading despite a decreased clock frequency for reduced power consumption under non-contact usage, and ensuring high-speed processing under non-contact usage. A dual interface card is a battery-less IC card capable of operating in accordance with a contact usage or a non-contact usage. The dual interface card operates at a high clock under contact usage and at a low clock under non-contact usage. A targeted operation comprises a plurality of different basic operations. The dual interface card comprises a basic arithmetic circuit group. Under the contact usage, the basic arithmetic circuit group performs one basic operation of the targeted operation at one cycle. Under the non-contact usage, the basic arithmetic circuit group sequentially performs at least two basic operations of the targeted operation at one cycle. | 08-02-2012 |
20120293354 | BIT SEQUENCE GENERATION APPARATUS AND BIT SEQUENCE GENERATION METHOD - A bit sequence generation apparatus includes a glitch generating circuit that generates a glitch, a sampling circuit that samples the glitch waveform generated by the glitch generating circuit, and a glitch shape determination circuit that generates 1-bit data indicating either 1 or 0, based on the glitch waveform sampled by the sampling circuit, and generates a bit sequence composed of a plurality of generated 1-bit data. The bit sequence generation apparatus can provide a PUF circuit that is able to generate highly randomized secret information even in a device with a low degree of freedom of alignment and wiring and that does not violate the design rules. | 11-22-2012 |
20130071036 | IMAGE PROCESSING DEVICE, IMAGE PROCESSING METHOD, AND IMAGING DEVICE - An image processing device includes an in-plane pattern detector that selects a pixel of interest in a frame image of interest, calculates in-plane correlation index values representing correlations between the pixel of interest and in-plane pixel patterns including the pixel of interest, and selects a most highly correlated pattern as an in-plane addition pattern. A reference pattern detector calculates inter-plane correlation index values representing correlations between the in-plane pixel addition pattern and reference pixel patterns in a reference frame image temporally adjoining the frame of interest, and selects a most highly correlated reference pixel pattern. A pixel adder adds the values of the pixels in the selected in-plane pixel pattern and the selected reference pixel addition pattern to generate a corrected pixel value, thereby achieving high sensitivity and a high signal-to-noise ratio under low illumination, with little loss of resolution. | 03-21-2013 |
20130207597 | CHARGE CIRCUIT - A charge circuit includes a current limiting circuit configured to limit a current input from an input terminal; a first transistor connected between an output terminal of the current limiting circuit and a secondary battery; a charge control circuit configured to turn the first transistor on and off to start and stop supply of a charge current to the secondary battery; a second transistor configured to output a current proportional to the charge current flowing through the first transistor; and a charge timer configured to generate clock pulses according to the current output from the second transistor. The charge control circuit is configured to turn off the first transistor to stop the supply of the charge current to the secondary battery when the number of the clock pulses reaches a predetermined number. | 08-15-2013 |
20130293274 | BIT GENERATION APPARATUS AND BIT GENERATION METHOD - A bit generation apparatus includes a glitch generation circuit that generates glitch signals which include a plurality of pulses, and T-FF bit generation circuits which input the glitch signals, and based on either rising edges or falling edges of the plurality of pulses included in the glitch signals, generate a bit value of either 0 or 1. Each of the T-FF bit generation circuits generates a respective bit value based on either the parity of the number of rising edges or the parity of the number of falling edges of the plurality of pulses. As a result of employment of the T-FF bit generation circuits, circuits that are conventionally required but not essential for the glitch become unnecessary. This serves to prevent expansion in circuit scale and increase in processing time of bit generation for the bit generation circuit. | 11-07-2013 |
20130336596 | IMAGE PROCESSING DEVICE AND METHOD - For each pixel in an image (Din), a contrast correlation value (CT) is detected for peripheral areas centered around the pixel to be corrected ( | 12-19-2013 |
20140012136 | Biological Optical Measuring Apparatus - A biological optical measuring apparatus includes a light source probe and a light receiving probe, one of which is provided with a pressure sensor to detect a contact pressure of a skin of a subject. Pairs of plural values of the contact pressure and light detection signals are previously recorded as calibration data, an estimated value of a false signal is derived from a detection value of the pressure sensor at primary measurement and the calibration data, and a measurement signal waveform in which a noise component due to a movement of the subject is removed is acquired by subtracting the estimated value from a light measurement signal. | 01-09-2014 |
20140089685 | KEY INFORMATION GENERATION DEVICE AND KEY INFORMATION GENERATION METHOD - In initial generation (for example, shipping from the factory), a security device generates an identifier w specific to the security device, with the PUF technology, generates key information k (k=HF(k)) from the identifier w, generates encrypted confidential information x by encrypting (x=Enc(mk, k)) confidential information mk with the key information k, and stores the encrypted confidential information x and an authentication code h (h=HF′(k)) of the key information k, in a nonvolatile memory. In operation, the security device generates the identifier w with the PUF technology, generates the key information k from the identifier w, and decrypts the encrypted confidential information x with the key information k. At a timing where the identifier w is generated in the operation, the security device checks whether the current operating environment has largely changed from the initial generation (S | 03-27-2014 |
20140125254 | ACCELERATING STRUCTURE - The present invention provides an accelerating structure capable of increasing a degree of vacuum at a middle part inside the accelerating structure while confining an alternating electric field to the inside. An accelerating structure | 05-08-2014 |
20150016722 | IMAGE PROCESSING DEVICE AND METHOD - A region determination circuit ( | 01-15-2015 |
20150042872 | IMAGING DEVICE - An imaging device has an intra-plane pixel summation unit and an inter-plane pixel summation unit. In the frame of interest, the intra-plane pixel summation unit sums the signals of the pixel of interest and selected highly correlated neighboring pixels to generate an intra-plane sensitized signal and a code indicating the pattern formed by the pixel of interest and the selected pixels. The inter-plane pixel summation unit selects pixels for summation from among the pixels positioned identically to the pixel of interest and pixels in the neighborhood of the identically positioned pixels in one or more frames neighboring the frame of interest on the basis of the agreement or disagreement of their pixel summing pattern codes and correlation of their intra-plane sensitized signals. In a Bayer array imaging device, enhanced sensitivity is obtained without causing color mixing. | 02-12-2015 |