Patent application number | Description | Published |
20080244029 | DATA PROCESSING SYSTEM - A transmission cancellation section is provided on a bus connecting a master and a slave. During a reset of the master, the transmission cancellation section blocks the bus so that an invalid command flowing on the bus does not reach the slave and executes, instead of the master stopped by the reset operation, generation of data which corresponds to an access request command already output to the slave and is to be sent to the slave and receiving of data from the slave. | 10-02-2008 |
20090031101 | DATA PROCESSING SYSTEM - Before arbitration is performed in an arbitration section, an access from a master is kept in a waiting state until update of a conversion table buffer is performed, and an address conversion section is provided in a subsequent stage of the arbitration section. Without waiting for the completion of buffer update, an access is issued in advance at a time when it is assured that update is completed at the completion of address conversion. Thus, influences of waiting buffer update on another master can be eliminated and access latency can be reduced. | 01-29-2009 |
20090125738 | DATA PROCESSING APPARATUS - An access stop control apparatus is provided in a resource control apparatus so that reception of access from a master apparatus is temporarily stopped during changing of a clock frequency and the clock frequency is changed at safe timing. Thereby, the operation of the master apparatus does not need to be stopped during changing of the clock frequency and a period for which access to a resource is stopped can be suppressed. Therefore, execution of an application requiring real-timeness is not affected. | 05-14-2009 |
20090282270 | MEMORY CONTROL DEVICE - A clock enable (CKE) control circuit ( | 11-12-2009 |
20110055443 | MEMORY CONTROL APPARATUS AND INFORMATION PROCESSING APPARATUS INCLUDING THE SAME - Provided is a memory control apparatus including: a monitoring unit that monitors, for each of the masters, a usable bandwidth indicating an amount of memory access data to be accessed per unit time in response to a corresponding one of the access requests from the master; a holding unit that holds a predetermined request bandwidth for each of the masters; a bandwidth determining unit that determines whether or not the usable bandwidth has reached the predetermined request bandwidth for each of the masters; and a control unit that issues an advanced refresh command to the memory based on a result of the determination by the bandwidth determining unit for each of the masters, regardless of timing of a refresh cycle. | 03-03-2011 |
20110176372 | MEMORY INTERFACE - The memory interface includes: a first data latch unit that delays a strobe signal from a memory device, through a first variable delay unit and reads the strobe signal as a first data signal; and a second data latch unit that delays the same strobe signal through the second variable delay unit and reads the strobe signal as a second data signal. The memory interface uses the data read by the first data latch unit in a normal memory access operation, detects a boundary of the delay amount by comparing the data with the data read by the second data latch unit, and reflects the boundary on the delay amount of the first variable delay unit. Thereby, the delay amount can be corrected without suspending the normal memory access operation. | 07-21-2011 |
20120087469 | X-RAY PHOTOGRAPHY SYSTEM - An X-ray photography device capable of visualizing the operating state or position of a support unit in an image system during examinations with memory switches and enhancing the operability of the memory switches is provided. When a plurality of memory switches | 04-12-2012 |
20120199833 | RADIATION DETECTOR - A radiation detector of this invention has a barrier layer on the upper surface of a high resistance film along the outer edge of a common electrode, which enables prevention of a chemical reaction between an amorphous semiconductor layer and a curable synthetic resin. The barrier layer is adhesive to the curable synthetic resin film, and this can prevent strength being insufficient, such that temperature changes cause separation in interfaces between the barrier layer and curable synthetic resin film, thereby reducing the effect of inhibiting warpage and cracking. The material for the barrier layer is an insulating material not including a substance that would chemically react with the amorphous semiconductor layer. This can prevent components of the material for the barrier layer from chemically reacting with the semiconductor layer. Consequently, creeping discharge at the outer edge of the common electrode where electric fields concentrate can be prevented. | 08-09-2012 |
20130219115 | DELAY CIRCUIT, DELAY CONTROLLER, MEMORY CONTROLLER, AND INFORMATION TERMINAL - A delay circuit of the present disclosure includes a first delay unit and a second delay unit which are connected in series and delay an input signal to generate a delayed signal. The first delay unit includes a first signaling pathway, and changes, based on a first delay control value, a first amount of delay to be provided to the input signal by switching signaling pathways for transmitting the input signal that are within the first pathway. The second delay unit includes a second signaling pathway, and changes, based on a second delay control value, a second amount of delay to be provided to the input signal without switching the second signaling pathway for transmitting the input signal. | 08-22-2013 |