Patent application number | Description | Published |
20090289732 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND FREQUENCY SYNTHESIZER - A semiconductor integrated circuit includes: a resonance circuit configured to determine an oscillation frequency; a first MOS transistor connected to the resonance circuit and configured to constitute an oscillation unit for delivering an oscillation output having the oscillation frequency; a second MOS transistor connected in parallel with the first MOS transistor; and a control unit configured to turn on and off the second MOS transistor according to the oscillation frequency, thereby enabling an equivalent gate width based on the first and second MOS transistors to be increased and decreased. Consequently, there is obtained an oscillation output having reduced phase noise, while an adequate oscillation margin is maintained. | 11-26-2009 |
20100033259 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device includes a plurality of first gates each of which has a first protrusion section protruding from a first active region; a plurality of second gates each of which has a second protrusion section protruding from a second active region adjacent to the first active region in a direction opposite to a protruding direction of the first protrusion section; a second common interconnect which is formed on the first protrusion section of the plurality of first gates and on all drains of the second active region and connects the plurality of first gates and all drains of the second active region; and a third common interconnect which is formed on the second protrusion section of the plurality of second gates and on all drains of the first active region and connects the plurality of second gates and all drains of the first active region. | 02-11-2010 |
20100109781 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device includes: an amplifier circuit which respectively has one or more input terminals and one or more output terminals; a replica circuit which has the same DC characteristics as those of the amplifier circuit; a reference voltage generation circuit which is connected to a bias terminal of the replica circuit, and which generates a predetermined reference voltage at the bias terminal; and a feedback circuit which takes a difference between the reference voltage generated at the bias terminal of the replica circuit and the voltage generated at a bias terminal of the amplifier circuit, and which performs feedback control by providing negative feedback of the difference to the bias terminal of the amplifier circuit so that the voltage generated at the bias terminal of the amplifier circuit is made equal to the reference voltage generated at the bias terminal of the replica circuit. | 05-06-2010 |
20100237956 | BIAS GENERATION CIRCUIT AND VOLTAGE CONTROLLED OSCILLATOR - This invention includes a bias origination section configured to originate an original bias voltage; a comparison section configured to compare the original bias voltage and a comparison voltage, and output a comparison result; a resistive divider section composed by a resistance circuit including a variable resistor section having a resistor and a switch, and configured to generate the comparison voltage; a bias decision control section configured to determine bias decision data for controlling a resistance value of the variable resistor section so as to bring the comparison voltage close to the original bias voltage, based on a comparison result of the comparison section; and a storage section configured to hold the bias decision data and also output the comparison voltage as a bias voltage by controlling a resistance value of the variable resistor section based on the held bias decision data, thereby generating a low-noise bias with a small area. | 09-23-2010 |
20100271106 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a mixer circuit unit having a first single gate mixer configured to receive a first input signal having a first frequency and a second input signal having a second frequency as inputs, a second single gate mixer configured to receive the first input signal and a third input signal of a phase inverted from a phase of the second input signal as inputs, a third single gate mixer configured to receive a fourth input signal of a phase inverted from the phase of the first input signal and the second input signal as inputs, and a fourth single gate mixer configured to receive the third and the fourth input signals as inputs; and a 1/2-frequency divider unit configured to receive output signals from the first to the fourth single gate mixers as inputs and output a desired signal. | 10-28-2010 |
20120062296 | TIME TO DIGITAL CONVERTER AND ALL DIGITAL PHASE-LOCKED-LOOP - According to one embodiment, a multiphase circuit, a flip-flop, and a decoder are provided. The multiphase circuit generates multiphase signals of which phases are different from each other by 180/M degrees by dividing a differential oscillation signal by M (M is an integral number not smaller than 2). The flip-flop captures the multiphase signal in synchronization with an input of a reference signal. The decoder decodes an output signal of the flip-flop. | 03-15-2012 |
20120176165 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a mixer circuit unit having a first single gate mixer configured to receive a first input signal having a first frequency and a second input signal having a second frequency as inputs, a second single gate mixer configured to receive the first input signal and a third input signal of a phase inverted from a phase of the second input signal as inputs, a third single gate mixer configured to receive a fourth input signal of a phase inverted from the phase of the first input signal and the second input signal as inputs, and a fourth single gate mixer configured to receive the third and the fourth input signals as inputs; and a ½-frequency divider unit configured to receive output signals from the first to the fourth single gate mixers as inputs and output a desired signal. | 07-12-2012 |
20140203880 | BIAS CURRENT CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT - A bias current circuit controls an oscillator that generates an oscillation signal of a frequency corresponding to an input current. The circuit includes a part that detects fluctuation of a control current for variably controlling the frequency of the oscillation signal and a part that generates an input current in which a fluctuation component of the control current is canceled using a current for cancelling the detected fluctuation of the control current. | 07-24-2014 |
20140245103 | MEMORY CONTROLLER, STORAGE DEVICE, AND MEMORY CONTROL METHOD - According to one embodiment, a memory controller includes: a first flash encoding unit that performs flash encoding on user data according to a first scheme to generate user data flash codes; an encoding unit that performs an error correction encoding process on the user data flash codes to generate parities; a second flash encoding unit that performs flash encoding on the parities according to a second scheme to generate parity flash codes; and a memory I/F that writes the user data flash codes and the parity flash codes to the nonvolatile memory. | 08-28-2014 |
20150035690 | DELAY CIRCUIT AND DIGITAL TO TIME CONVERTER - A delay circuit includes a first inverter in which a delay time of rising is larger than a delay time of falling, and a second inverter which is connected in series with the first inverter and in which a delay time of falling is larger than a delay time of rising. Transistors for each of the first and second inverters are connected in series between a power supply terminal and a ground terminal. | 02-05-2015 |
Patent application number | Description | Published |
20080303603 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device includes a voltage controlled oscillator which controls a bias current or an oscillation frequency to supply an output signal, a phase-locked loop circuit which supplies a frequency control signal based on the output signal supplied from the voltage controlled oscillator, a peak detection circuit which detects a peak of the frequency control signal supplied from the phase-locked loop circuit, and a bias control circuit which produces a bias current based on the peak detected by the peak detection circuit to supply the bias current. The voltage controlled oscillator controls the bias current supplied from the bias control circuit or the oscillation frequency to supply the output signal based on the frequency control signal supplied from the phase-locked loop circuit. | 12-11-2008 |
20090051455 | MODULATION/DEMODULATION APPARATUS AND MODULATION/DEMODULATION METHOD - A modulation/demodulation apparatus according to an embodiment of the present invention includes a sine wave generating circuit configured to output two sine waves which are orthogonal to each other and have equal amplitude, an orthogonal modulator connected to the sine wave generating circuit and configured to modulate the sine waves to generate a modulated signal, a detecting section configured to detect amplitude fluctuation in the modulated signal, a multiplying section configured to multiply the modulated signal and the amplitude fluctuation detected by the detecting section together, and an orthogonal demodulator configured to demodulate the modulated signal multiplied with the amplitude fluctuation by the multiplying section to generate a demodulated signal. | 02-26-2009 |
20090088123 | FREQUENCY CONVERTING CIRCUIT AND RECEIVER - A frequency converting circuit that outputs an output signal obtained by mixing a first input signal and a second input signal, has: a first input terminal to which the first input signal is input; a second input terminal to which the second input signal is input; an output terminal from which the output signal is output; a frequency converting element that has a first input part connected to the first input terminal and an output part connected to the output terminal, restricts the signal input to the first input part according to a signal input to a second input part and outputs the restricted signal to the output part; and a pulse controlling circuit that receives the second input signal via the second input terminal and outputs a pulse signal obtained by restricting the pulses of the second input signal to the second input part of the frequency converting element. | 04-02-2009 |
20090131099 | AMPLIFYING DEVICE AND RADIO - An amplifying device has an amplifier which amplifies an input signal supplied from an input terminal and outputs the amplified input signal, a feedback loop which has at least one of a resistive element and a capacitance connected between an output terminal of the amplifier and the input terminal, a variable current unit which adjusts a current value in accordance with a controlling signal and supplies an operating current to the amplifier, a signal analyzing unit which generates a time difference signal having a value corresponding to a slew rate of the input signal and outputs the time difference signal, and a controlling unit which generates the controlling signal in accordance with the time difference signal and outputs the controlling signal. | 05-21-2009 |
20090253396 | WIRELESS COMMUNICATION APPARATUS - A wireless communication apparatus includes a local oscillator that generates a plurality of LO (Local Oschillation) signals corresponding to frequencies of a plurality of input RF (Radio Frequency) signals, an accumulator that accumulates the plurality of LO signals generated by the local oscillator to generate an accumulated signal, a mixer that mixes the plurality of RF signals and the accumulated signal generated by the accumulator and to generate a plurality of base band signals, and a first signal processing unit that executes a signal process with respect to the plurality of base band signals generated by the mixer. | 10-08-2009 |
20110181367 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND OSCILLATION FREQUENCY CALIBRATION METHOD - A semiconductor integrated circuit device includes a DCO and a storing unit that stores a temperature coefficient of an oscillation frequency and an absolute value of the oscillation frequency, which should be set in the DCO, corresponding to potential obtained from a voltage source that changes with a monotonic characteristic with respect to temperature. | 07-28-2011 |
20120056682 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND OSCILLATION FREQUENCY CALIBRATION METHOD - A semiconductor integrated circuit device includes a DCO and a storing unit that stores a temperature coefficient of an oscillation frequency and an absolute value of the oscillation frequency, which should be set in the DCO, corresponding to potential obtained from a voltage source that changes with a monotonic characteristic with respect to temperature. | 03-08-2012 |
20120063520 | SEMICONDUCTOR INTEGRATED CIRCUIT, RADIO COMMUNICATION DEVICE AND TIME TO DIGITAL CONVERTER - According to one embodiment, a semiconductor integrated device includes a digitally controlled oscillator, a counter, a time to digital converter, an adder, and a control signal generator. The time to digital converter includes a frequency-divider, a plurality of impedance elements, and a phase difference detector. The frequency-divider is configured to frequency-divide the oscillation signal to generate a plurality of frequency-divided signals. The plurality of impedance elements is configured to voltage-divide the frequency-divided signals to generate a plurality of delay signals of the oscillation signal. The phase difference detector is configured to output the third digital signal corresponding to the phase difference between the reference signal and the oscillation signal by comparing the reference signal with each of the delay signals. | 03-15-2012 |
20120064844 | SEMICONDUCTOR INTEGRATED CIRCUIT AND RADIO COMMUNICATION DEVICE - According to one embodiment, a semiconductor integrated circuit includes a phase shifter, a plurality of phase matching detecting circuits, a output module. The phase shifter is configured to delay an input oscillation signal to generate a plurality of delay signals having phases different from each other. The plurality of phase matching detecting circuits is configured to store a second program for downloading a first program from an outside to the first area. The output module is configured to generate an output oscillation signal based on at least one of the delay signals having the phase difference determined to be within the predetermined range. | 03-15-2012 |
20120135700 | FREQUENCY CONVERTING CIRCUIT AND RECEIVER - A frequency converting circuit that outputs an output signal obtained by mixing a first input signal and a second input signal, has: a first input terminal to which the first input signal is input; a second input terminal to which the second input signal is input; an output terminal from which the output signal is output; a frequency converting element that has a first input part connected to the first input terminal and an output part connected to the output terminal, restricts the signal input to the first input part according to a signal input to a second input part and outputs the restricted signal to the output part; and a pulse controlling circuit that receives the second input signal via the second input terminal and outputs a pulse signal obtained by restricting the pulses of the second input signal to the second input part of the frequency converting element. | 05-31-2012 |
20120142292 | WIRELESS COMMUNICATION APPARATUS - A wireless communication apparatus includes a local oscillator that generates a plurality of LO (Local Oschillation) signals corresponding to frequencies of a plurality of input RF (Radio Frequency) signals, an accumulator that accumulates the plurality of LO signals generated by the local oscillator to generate an accumulated signal, a mixer that mixes the plurality of RF signals and the accumulated signal generated by the accumulator and to generate a plurality of base band signals, and a first signal processing unit that executes a signal process with respect to the plurality of base band signals generated by the mixer. | 06-07-2012 |
20120242314 | DC-DC CONVERTER AND DIGITAL PULSE WIDTH MODULATOR - A DC-DC converter has a switching element, a lowpass filter, an oscillator, an AD converter, an error signal generator, a counter, a comparator, a selector configured to select one of the plurality of clock signals in accordance with a value of a lower side bit of the error signal in sync with a timing when the comparator detects coincidence, and a switching controller configured to control ON/OFF of the switching element in accordance with the clock signal selected by the selector. The selector selects one among the plurality of clock signals and a new clock signal generated by combining two or more clock signals comprising neighboring phases among the plurality of clock signals. | 09-27-2012 |
20130137388 | SEMICONDUCTOR INTEGRATED CIRCUIT AND RADIO RECEIVER - The first control circuit controls the gain of the variable gain amplifier circuit and the cut-off frequency of the first low-pass filter so as to keep constant a product of a transfer function of the variable gain amplifier circuit and a transfer function of the first low-pass filter. The second control circuit compares a level of the second feedback signal and a preset threshold value after completion of gain control of the variable gain amplifier circuit, the second control circuit inputting the signal outputted from the first low-pass filter, as the first feedback signal to the first terminal as long as the level of the second feedback signal is not lower than the threshold value, the second control circuit inputting the signal outputted from the second low-pass filter, as the first feedback signal to the first terminal. | 05-30-2013 |
20140055296 | TIME-TO-DIGITAL CONVERTING CIRCUIT AND DIGITAL-TO-TIME CONVERTING CIRCUIT - A time-to-digital converting circuit includes a first flip-flop and a second flip-flop. The time-to-digital converting circuit a first delay controlling circuit that outputs a first data signal obtained by controlling a delay time of the reference data signal input thereto via the first signal input terminal based on the first output signal and a first clock signal obtained by controlling a delay time of the reference clock signal input thereto via the second signal input terminal based on the first output signal. | 02-27-2014 |
20150074028 | PROCESSING DEVICE AND COMPUTATION DEVICE - According to one embodiment, a processing device is configured to process input data formed of a plurality of input digital values. The processing device has a plurality of computation layers connected in series. Each of the computation layers has a plurality of computation devices. Each of the plurality of computation devices in the computation layer of a first stage is configured to generate a digital value from the input digital values and weight coefficients defined in advance. The weight coefficients are applied to each of the input digital values. Each of the plurality of computation devices of the computation layer of a second or subsequent stage is configured to generate a new digital value from the digital values generated by the computation devices of the computation layer of the previous stage and weight coefficients defined in advance. The weight coefficients are applied to each of the digital values. | 03-12-2015 |