Patent application number | Description | Published |
20150187883 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes: a first n− type epitaxial layer disposed on a first surface of an n+ type silicon carbide substrate; a p type epitaxial layer disposed on the first n− type epitaxial layer; a second n− type epitaxial layer disposed on the p type epitaxial layer; an n+ region disposed on the second n− type epitaxial layer; a trench passing through the second n− type epitaxial layer, the p type epitaxial layer, and the n+ region, and disposed on the first n− type epitaxial layer; a p+ region disposed on the p type epitaxial layer and separated from the trench; and a gate insulating layer positioned in the trench, in which channels are disposed in the second n− type epitaxial layer of both sides of the trench and the p type epitaxial layer of both sides of the trench. | 07-02-2015 |
20150187929 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes: a first n− type epitaxial layer disposed on a first surface of an n+ type silicon carbide substrate including a current carrying region and termination regions positioned at both sides of the current carrying region; a p type epitaxial layer disposed on the first n− type epitaxial layer; a second n− type epitaxial layer disposed on the p type epitaxial layer; a first trench disposed in the current carrying region; a second trench disposed in each termination region; a gate insulating layer disposed in the first trench; a gate electrode disposed on the gate insulating layer; and a termination insulating layer disposed in the second trench, in which a side of the termination insulating layer contacts the p type epitaxial layer and the second n− type epitaxial layer. | 07-02-2015 |
20150187962 | SCHOTTKY BARRIER DIODE AND METHOD OF MANUFACTURING THE SAME - A Schottky barrier diode includes: an n− type epitaxial layer disposed on a first surface of an n+ type silicon carbide substrate; a first p+ region disposed on the n− type epitaxial layer; an n type epitaxial layer disposed on the n− type epitaxial layer and the first p+ region; a second p+ region disposed on the n type epitaxial layer, and being in contact with the first p+ region; a Schottky electrode disposed on the n type epitaxial layer and the second p+ region; and an ohmic electrode disposed on a second surface of the n+ type silicon carbide substrate. Also, the first p+ region has a lattice shape including a plurality of vertical portions and horizontal portions connecting both ends of the respective vertical portions to each other. | 07-02-2015 |
Patent application number | Description | Published |
20140117379 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device includes sequentially forming an n− type epitaxial layer, a p type epitaxial layer, and a first n+ region on a first surface of an n+ type silicon carbide substrate, and forming a trench through the first n+ region and the p type epitaxial layer, wherein the forming of the trench includes forming a photosensitive layer pattern on the first n+ region, etching the first n+ region and the p type epitaxial layer by using the photosensitive layer pattern as a mask, forming a buffer layer by using amorphous carbon on the first n+ region after the photosensitive layer pattern is removed, forming a buffer layer pattern by etching the buffer layer, etching using the buffer layer pattern as the mask, isotropically etching to form a second portion of the trench, and removing the buffer layer pattern. | 05-01-2014 |
20140167071 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes: a plurality of n type pillar regions and an n− type epitaxial layer disposed on a first surface of an n+ type silicon carbide substrate; a p type epitaxial layer and an n+ region disposed on the plurality of n type pillar regions and the n− type epitaxial layer; a trench penetrating the n+ region and the p type epitaxial layer and disposed on the plurality of n type pillar regions and the n− type epitaxial layer; a gate insulating film disposed within the trench; a gate electrode disposed on the gate insulating film; an oxide film disposed on the gate electrode; a source electrode disposed on the p type epitaxial layer, the n+ region, and the oxide film; and a drain electrode disposed on a second surface of the n+ type silicon carbide substrate, wherein each corner portion of the trench is in contact with a corresponding n type pillar region. | 06-19-2014 |
20140167072 | SCHOTTKY BARRIER DIODE AND METHOD OF MANUFACTURING THE SAME - A schottky barrier diode includes an n− type epitaxial layer disposed at a first surface of an n+ type silicon carbide substrate, a plurality of n type pillar areas disposed in the n− type epitaxial layer at a first portion of a first surface of the n+ type silicon carbide substrate, a plurality of p+ areas disposed at a surface of the n− type epitaxial layer and separated from the n type pillar area, a schottky electrode disposed on the n− type epitaxial layer and the p+ area, and an ohmic electrode disposed at a second surface of the n+ type silicon carbide substrate. A doping density of the n type pillar area is larger than a doping density of the n− type epitaxial layer. | 06-19-2014 |
20140170824 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes: sequentially forming an n− type epitaxial layer, a p type epitaxial layer, and a first n+ region on a first surface of an n+ type silicon carbide substrate; forming a trench by penetrating the first n+ region and the p type epitaxial layer, and etching part of the n− type epitaxial layer; forming a buffer layer in the trench and on the first n+ region; etching the buffer layer to form a buffer layer pattern on both sidewalls defined by the trench; forming a first silicon film on the first n+ region, the buffer layer pattern, and a surface of the n− type epitaxial layer exposed by the trench; oxidizing the first silicon film to form a first silicon oxide film; removing the buffer layer pattern by an ashing process to form a first silicon oxide film pattern; forming a second silicon film on the first silicon oxide film pattern and in the trench; oxidizing the second silicon film to form a second silicon oxide film; and etching the second silicon oxide film to form a gate insulating film within the trench, wherein the first silicon oxide film pattern is positioned on the first n+ region and at the bottom of the trench on the surface of the n− type epitaxial layer. | 06-19-2014 |
20140183554 | SCHOTTKY BARRIER DIODE AND METHOD OF MANUFACTURING THE SAME - A Schottky barrier diode includes: an n+ type silicon carbide substrate; an n− type epitaxial layer disposed on a first surface of the n+ type silicon carbide substrate and includes an electrode area and a terminal area positioned outside of the electrode area; a first trench and a second trench disposed on the n− type epitaxial layer in the terminal area; a p area disposed under the first trench and the second trench; a Schottky electrode disposed on the n− type epitaxial layer in the electrode area; and an ohmic electrode disposed on a second surface of the n+ type silicon carbide substrate, wherein the first trench and the second trench are adjacently positioned to form a step. | 07-03-2014 |
20140183556 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - The present inventive concept has been made in an effort to increase the width of a channel in a silicon carbide MOSFET using a trench gate. | 07-03-2014 |
20140183558 | SCHOTTKY BARRIER DIODE AND METHOD OF MANUFACTURING THE SAME - A schottky barrier diode includes: an n− type epitaxial layer that is disposed at a first surface of an n+ type silicon carbide substrate; a plurality of n type pillar areas that are disposed at the inside of the n− type epitaxial layer and that are disposed at a first portion of the first surface of the n+ type silicon carbide substrate; a p type area that is disposed at the inside of the n− type epitaxial layer and that is extended in a direction perpendicular to the n type pillar areas; a plurality of p+ areas in which the n− type epitaxial layer is disposed at a surface thereof and that are separated from the n type pillar areas and the p type area; a schottky electrode that is disposed on the n− type epitaxial layer and the p+ areas; and an ohmic electrode that is disposed at a second surface of the n+ type silicon carbide substrate. | 07-03-2014 |
20140183559 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - The present inventive concept has been made in an effort to improve the breakdown voltage of a silicon carbide MOSFET using a trench gate. | 07-03-2014 |
20140183560 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes an n+ type silicon carbide substrate; a plurality of n type pillar regions, a plurality of p type pillar regions, and an n− type epitaxial layer disposed on a first surface of the n+ type silicon carbide substrate; a p type epitaxial layer and an n+ region sequentially disposed on the n− type epitaxial layer; a trench penetrating the n+ region and the p type epitaxial layer and disposed on the n− type epitaxial layer; a gate insulating film disposed within the trench; a gate electrode disposed on the gate insulating film; an oxide film disposed on the gate electrode; a source electrode disposed on the p type epitaxial layer, the n+ region, and the oxide film; and a drain electrode positioned on a second surface of the n+ type silicon carbide substrate. | 07-03-2014 |
Patent application number | Description | Published |
20110052842 | RECEIVING SHEET FOR DYE-SUBLIMATION HEAT TRANSFER RECORDING AND METHOD FOR MANUFACTURING THE SAME - The present invention relates to a receiving sheet for dye-sublimation thermal transfer recording and a method for manufacturing the same, and more particularly to a receiving sheet for dye-sublimation thermal transfer recording, which includes a base layer, a back coating layer formed on one surface of the base layer, and an ink-receiving layer formed on the surface opposite the surface of the base layer on which the back coating layer is formed, the ink-receiving layer containing porous metal oxide nanoparticles, and a method for manufacturing the same. The inventive receiving sheet for dye-sublimation thermal transfer recording includes the ink-receiving layer containing porous metal oxide nanoparticles. Thus, the resolution of images on the receiving sheet can be maintained, while the resistance to thermal deformation and durability of the receiving sheet can be greatly improved, thus offering many advantages in terms of image quality or cost. | 03-03-2011 |
20110262666 | THERMAL TRANSFER RIBBON CONTAINING EXFOLIATED LAYERED INORGANIC NANOPARTICLES OR EXFOLIATED LAYERED DOUBLE HYDROXIDE NANOPARTICLES AND MANUFACTURING METHOD THEREOF - The present invention relates to a thermal transfer ribbon containing exfoliated layered inorganic nanoparticles or exfoliated layered double hydroxides and a manufacturing method thereof, and more particularly to a sublimation thermal transfer ribbon wherein a second adhesive layer, a transfer ink layer and a transfer protective layer are formed on one surface of a base film having a lubricating heat-resistant layer and a first adhesive layer formed on the other surface thereof, in which the lubricating heat-resistant layer, the transfer ink layer and the transfer protective layer contain exfoliated layered inorganic nanoparticles or exfoliated layered double hydroxide nanoparticles to improve the heat resistance, image uniformity and abrasion resistance of the thermal transfer ribbon. | 10-27-2011 |
20120220647 | NANO-HYBRID OF TARGETABLE SIRNA-LAYERED INORGANIC HYDROXIDE, MANUFACTURING METHOD THEREOF, AND PHARMACEUTICAL COMPOSITION FOR TREATING TUMOR COMPRISING THE NANO-HYBRID - A nanohybrid of the potent gene therapeutic agent siRNA (small interfering RNA) and a target-specific layered inorganic hydroxide, a preparation method thereof, and a pharmaceutical composition for tumor treatment containing the target-specific, siRNA/layered inorganic hydroxide nanohybrid. The nanohybrid increases the in vivo stability of the siRNA, and a target-specific multifunctional ligand, which is bonded to the layered inorganic hydroxide and can bind specifically to a tumor, increases the efficiency of tumor-specific transfer of the siRNA such that the siRNA shows tumor therapeutic activity even at a relatively low dose. Thus, the nanohybrid will be widely useful for target-specific antitumor therapies. | 08-30-2012 |
Patent application number | Description | Published |
20130088663 | METHOD OF MANUFACTURING POLARIZING PLATE, METHOD OF MANUFACTURING DISPLAY APPARATUS HAVING THE SAME AND THE DISPLAY APPARATUS - A method of manufacturing a polarizing plate includes disposing a non-conductive material on a base substrate, pressing the non-conductive material using a mold and forming a resist pattern, the resist pattern including a plurality of protruding portions, and forming a metal layer on the protruding portions of the resist pattern. Accordingly, a luminance of a display apparatus can be improved and a manufacturing process can be simplified. | 04-11-2013 |
20130120698 | LIQUID CRYSTAL DISPLAY INCLUDING WIRE GRID POLARIZER AND MANUFACTURING METHOD THEREOF - A liquid crystal display includes a first substrate. A plurality of fine metal lines is disposed on the first substrate. The plurality of fine metal lines including a plurality of small regions. A second substrate is aligned with the first substrate. A light blocking portion is disposed on the second substrate. The light blocking portion is disposed in a region between the small regions of the plurality of small regions of the plurality of fine metal lines. | 05-16-2013 |
20130270223 | PHOTORESIST COMPOSITION, METHOD OF MANUFACTURING A POLARIZER AND METHOD OF MANUFACTURING A DISPLAY SUBSTRATE USING THE SAME - A photoresist composition includes about 65% by weight to about 80% by weight of a mono-functional monomer, about 5% by weight to about 20% by weight of a di-functional monomer, about 1% by weight to about 10% by weight of a multi-functional monomer including three or more functional groups, about 1% by weight to about 5% by weight of a photoinitiator, and less than about 1% by weight of a surfactant, each based on a total weight of the photoresist composition. | 10-17-2013 |
20140016059 | POLARIZER, DISPLAY PANEL HAVING THE SAME AND METHOD OF MANUFACTURING THE SAME - A polarizer includes a substrate, and a first metal layer and a second metal layer disposed on the substrate. The first metal layer includes a plurality of protrusions of a wire grid pattern. Each protrusion has a first width and adjacent protrusions are spaced apart by a second width. The second metal layer is disposed on each of the protrusions of the first metal layer, and includes molybdenum (Mo) and/or titanium (Ti). | 01-16-2014 |
20140098330 | POLARIZER, LIQUID CRYSTAL DISPLAY, AND MANUFACTURING METHOD THEREOF - A polarizer includes an opening defined in the polarizer and through which light transmits; a non-opening which is adjacent to the opening and blocks the light; a plurality of metal lines elongated in a first direction, and separated from each other in a second direction different than the first direction, in the opening; and a plate-type pattern in the non-opening. A height of the metal lines is smaller than a height of the plate-type pattern, from a same reference; and an interval in the second direction and between adjacent metal lines is smaller than a wavelength of visible light rays. | 04-10-2014 |
20140118656 | LIQUID CRYSTAL DISPLAY AND MANUFACTURING METHOD THEREOF - A liquid crystal display includes a transparent insulation substrate, a first polarizer, and a semiconductor layer, a thin film transistor, and a backlight unit. The first polarizer is disposed on the transparent insulation substrate. The first polarizer includes a light blocking film and metal wires. The semiconductor layer, disposed on the light blocking film, has a perimeter aligned with a perimeter of the light blocking film. The thin film transistor, disposed on the semiconductor layer, includes a source region and a drain region disposed in the semiconductor layer. The backlight unit, disposed under the transparent insulation substrate, provides light to the transparent insulation substrate. The blocking film reflects substantially all of the light. Gaps are disposed between the metal wires. | 05-01-2014 |
20140133027 | REFLECTIVE POLARIZING PLATE, DISPLAY DEVICE INCLUDING THE POLARIZING PLATE AND METHOD OF MANUFACTURING THE POLARIZING PLATE - A reflective polarizing plate is monolithically integrated on a surface of a base layer of a display device. The polarizing plate comprises a polarizing area portion and a reflective/blocking area portion, both having a multi-layered structure. The polarizing area portion is patterned to have a plurality of spaced apart reflective wire grid strips. The reflective/blocking area portion is configured to reflect all light incident thereon from a predetermined direction (where that light would not otherwise be used) and to direct the reflected light back to a light providing source where the light can be recycled for other use. Therefore, a brightness and efficiency of the display device is improved. | 05-15-2014 |
20140146391 | POLARIZER AND METHOD OF MANUFACTURING THE SAME - A polarizer includes a substrate having a first refractive index, a metal pattern disposed on the substrate, and a passivation layer disposed on the metal pattern. The metal pattern includes a plurality of protrusions having widths. The passivation layer has a second refractive index and covers at least one surface of the protrusions. | 05-29-2014 |
20140291622 | ORGANIC LIGHT EMITTING DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - An organic light emitting display device includes a substrate comprising a first side and a second side, a first electrode on the first side of the substrate, an emitting layer on the first electrode, a second electrode on the emitting layer, and a slit-shaped pattern at the second side of the substrate, and comprising a plurality of protrusions spaced apart from each other. | 10-02-2014 |
20140293187 | LIQUID CRYSTAL DISPLAY DEVICE - A liquid crystal display device includes a liquid crystal display panel and a backlight unit providing light to the liquid crystal display panel. The liquid crystal display panel includes a first substrate on which a thin film transistor is disposed, a second substrate facing the first substrate, a liquid crystal layer disposed between the first substrate and the second substrate, and a first polarizer disposed on the second substrate having a plurality of metal patterns spaced apart from each other by an interval. The backlight unit faces the second substrate. | 10-02-2014 |
20140326956 | ORGANIC LIGHT EMITTING DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - An organic light emitting display device and a manufacturing method of an organic light emitting display device. An organic light emitting display device includes a substrate; a first electrode on the substrate; an emitting layer on the first electrode; a second electrode on the emitting layer; and a first slit-shaped pattern on the second electrode and including a plurality of first protrusions spaced apart from each other. | 11-06-2014 |
20140349425 | PHOTORESIST COMPOSITION, METHOD OF MANUFACTURING A POLARIZER AND METHOD OF MANUFACTURING A DISPLAY SUBSTRATE USING THE SAME - A photoresist composition includes about 65% by weight to about 80% by weight of a mono-functional monomer, about 5% by weight to about 20% by weight of a di-functional monomer, about 1% by weight to about 10% by weight of a multi-functional monomer including three or more functional groups, about 1% by weight to about 5% by weight of a photoinitiator, and less than about 1% by weight of a surfactant, each based on a total weight of the photoresist composition. | 11-27-2014 |
20140354910 | WIRE GRID POLARIZER, AND LIQUID CRYSTAL DISPLAY PANEL AND LIQUID CRYSTAL DISPLAY DEVICE INCLUDING THE SAME - A wire grid polarizer includes a substrate, a wire grid layer which is disposed on the substrate and includes a plurality of wire patterns arranged with a predetermined interval, where gaps are defined between the wire patterns, and a passivation layer which is disposed on the wire grid layer and includes first passivation particles which cover a top portion of the gaps. | 12-04-2014 |
Patent application number | Description | Published |
20160026034 | POLARIZER AND DISPLAY PANEL HAVING THE SAME - A polarizer includes a base substrate, a polarizing layer disposed on the base substrate and including a plurality of first linear extensions spaced apart from each other, and an ultraviolet (UV)-blocking layer including a plurality of second linear extensions spaced apart from each other and crossing the first linear extensions. The polarizer may block an external UV light. | 01-28-2016 |
20160114502 | METHOD OF MANUFACTURING MOLD AND METHOD OF MANUFACTURING POLARIZER - Provided are a method of manufacturing a mold, a method of manufacturing a polarizer, and a display apparatus including the polarizer. According to one or more exemplary embodiments, a method of manufacturing a mold, the method including: forming a polymer pattern on a substrate, the polymer pattern including protrusions; forming a wire grid template portion on the substrate by etching, the substrate being etched using protrusions of the polymer pattern as a mask; forming a cover mask covering a portion of the wire grid template portion; forming a recess in the substrate by etching, the substrate being etched using the cover mask, the recess having a bottom surface lower than an upper surface of the wire grid template portion; and removing the cover mask. | 04-28-2016 |
20160116798 | METHOD OF MANUFACTURING A POLARIZER AND A DISPLAY PANEL HAVING THE SAME - A method of manufacturing a polarizer, the method including: forming a metal layer on a substrate; forming a hard mask on the metal layer; forming an adhesion layer on a portion of the hard mask; forming a polymer layer on the hard mask and the adhesion layer; pressing a mold on the polymer layer to form a lattice pattern in association with the polymer layer; removing the mold and a portion of the lattice pattern; and patterning the adhesion layer, the hard mask, and the metal layer using a remaining portion of the lattice pattern as a mask. | 04-28-2016 |
Patent application number | Description | Published |
20080316804 | Multiple level cell phase-change memory devices having controlled resistance drift parameter, memory systems employing such devices and methods of reading memory devices - In a method of controlling resistance drift in a memory cell of a resistance-changeable material memory device, the resistance changeable material in the memory cell is treated so that a drift parameter for the memory cell is less than about 0.18, wherein a change in resistance of a memory cell over the time period is determined according to the relationship: | 12-25-2008 |
20090016099 | Multiple level cell phase-change memory devices having post-programming operation resistance drift saturation, memory systems employing such devices and methods of reading memory devices - In a memory device and in a method of programming the same, a memory device comprises: a plurality of memory cells, each memory cell comprising a resistance-changeable material that has an initial resistance that is determined in response to an applied programming current in a programming operation; and a modification circuit that modifies the resistance of the memory cell following a programming operation of the memory cell to vary the resistance of the memory cell from the initial resistance to a second resistance by applying a saturation current in a saturation operation. Each memory cell is connected to a conduction line of the memory device that is used to apply the programming current to program the resistance of the corresponding memory cell in the programming operation, that is used to apply the saturation current to the corresponding memory cell in the saturation operation and that is used to apply a read current to read the resistance of the corresponding memory cell in a subsequent read operation. | 01-15-2009 |
20090303785 | PHASE CHANGE MEMORY DEVICES AND READ METHODS USING ELAPSED TIME-BASED READ VOLTAGES - A variable resistance memory device includes a memory cell connected to a bit line and a clamp circuit configured to provide either a first read voltage or a second read voltage to the bit line according to an elapsed time from a write operation of the memory cell. Related methods are also described. | 12-10-2009 |
20100181549 | Phase-Changeable Random Access Memory Devices Including Barrier Layers and Metal Silicide Layers - A PRAM device may include an insulating interlayer, a diode, a metal silicide layer, a barrier spacer, an outer spacer, a lower electrode, a phase-changeable layer and an upper electrode. The insulating interlayer may be formed on a substrate. The insulating interlayer may have a contact hole. The diode may be formed in the contact hole. The metal silicide layer may be formed on the diode. The barrier spacer may be formed on an upper surface of the metal silicide layer and a side surface of the contact hole. The outer spacer may be formed on the barrier spacer. The lower electrode may be formed on the barrier spacer. The phase-changeable layer may be formed on the lower electrode. The upper electrode may be formed on the phase-changeable layer. | 07-22-2010 |
20100243981 | Phase-change random access memory device - A phase-change random access memory device includes an isolation layer structure, an insulating interlayer, a spacer, a switching element and a phase-change material (PCM) layer. The isolation layer structure is in a trench on a substrate, defines an active region in the substrate, and has a recess at an upper portion thereof. The insulating interlayer has an opening partially exposing the active region and the isolation layer structure. The spacer is on a sidewall of the opening and fills the recess. The switching element is in the opening on the exposed active region. The PCM layer is electrically connected to the switching element. | 09-30-2010 |
Patent application number | Description | Published |
20100084649 | OXIDE THIN FILM TRANSISTOR AND METHOD OF FABRICATING THE SAME - An oxide thin film transistor (TFT) and its fabrication method are disclosed. In a TFT of a bottom gate structure using amorphous zinc oxide (ZnO)-based semiconductor as an active layer, source and drain electrodes are formed, on which the active layer made of oxide semiconductor is formed to thus prevent degeneration of the oxide semiconductor in etching the source and drain electrodes. The oxide TFT includes: a gate electrode form on a substrate; a gate insulating layer formed on the gate electrode; source and drain electrodes formed on the gate insulating layer and having a multi-layer structure of two or more layers; and an active layer formed on the source and drain electrodes and formed of amorphous zinc oxide-based semiconductor, wherein a metal layer such as indium-tin-oxide, molybdenum, and the like, having good ohmic-contact characteristics with titanium and a titanium alloy having good bonding force with oxygen or the oxide-based semiconductor is formed at an uppermost portion of the source and drain electrodes. In a method for fabricating an oxide TFT, a silicon nitride film is deposited with a sputter equipment without the necessity of H | 04-08-2010 |
20110278565 | OXIDE THIN FILM TRANSISTOR AND METHOD OF FABRICATING THE SAME - An oxide thin film transistor (TFT) and a fabrication method thereof are provided. The method for fabricating an oxide thin film transistor (TFT) comprises: forming a gate electrode on a substrate; forming a gate insulating layer on the substrate with the gate electrode formed thereon; forming an active layer made of oxide semiconductor on the gate insulating layer; forming a contact layer on the substrate with the active layer formed thereon and forming source and drain electrodes, which are electrically connected with source and drain regions of the active layer through the contact layer, on the contact layer; forming a protective layer on the substrate with the source and drain electrodes formed thereon; forming a contact hole by removing the protective layer to expose the drain electrode; and forming a pixel electrode electrically connected with the drain electrode through the contact hole, wherein the contact layer is made of oxide including a different metal or conductivity with that of the source and drain electrodes, to adjust a threshold voltage according to the difference in a work function. | 11-17-2011 |
20120146017 | OXIDE THIN FILM TRANSISTOR AND METHOD OF FABRICATING THE SAME - A method for fabricating an oxide thin film transistor includes sequentially forming a gate insulating film, an oxide semiconductor layer, and a first insulating layer; selectively patterning the oxide semiconductor layer and the first insulating layer to form an active layer and an insulating layer pattern on the gate electrode; forming a second insulating layer on the substrate having the active layer and the insulating layer pattern formed thereon; and selectively patterning the insulating layer pattern and the second insulating layer to form first and second etch stoppers on the active layer. The oxide semiconductor layer may be a ternary system or quaternary system oxide semiconductor comprising a combination of AxByCzO (A, B, C═Zn, Cd, Ga, In, Sn, Hf, Zr; x, y, z≧0). | 06-14-2012 |
20120261660 | OXIDE THIN FILM TRANSISTOR AND METHOD OF FABRICATING THE SAME - An oxide thin film transistor (TFT) and its fabrication method are disclosed. In a TFT of a bottom gate structure using amorphous zinc oxide (ZnO)-based semiconductor as an active layer, source and drain electrodes are formed, on which the active layer made of oxide semiconductor is formed to thus prevent degeneration of the oxide semiconductor in etching the source and drain electrodes. | 10-18-2012 |
20140070210 | OXIDE THIN FILM TRANSISTOR AND METHOD OF FABRICATING THE SAME - An oxide thin film transistor (TFT) and a fabrication method thereof are provided. The method for fabricating an oxide thin film transistor (TFT) comprises: forming a gate electrode on a substrate; forming a gate insulating layer on the substrate with the gate electrode formed thereon; forming an active layer made of oxide semiconductor on the gate insulating layer; forming a contact layer on the substrate with the active layer formed thereon and forming source and drain electrodes, which are electrically connected with source and drain regions of the active layer through the contact layer, on the contact layer; forming a protective layer on the substrate with the source and drain electrodes formed thereon; forming a contact hole by removing the protective layer to expose the drain electrode; and forming a pixel electrode electrically connected with the drain electrode through the contact hole, wherein the contact layer is made of oxide including a different metal or conductivity with that of the source and drain electrodes, to adjust a threshold voltage according to the difference in a work function. | 03-13-2014 |
Patent application number | Description | Published |
20090189905 | Apparatus and method of generating personal fonts - An apparatus and method of generating personal fonts is provided, which can modify a trace of handwriting inputted by a user into an elegant one and generate diverse personal fonts in accordance with user's style of handwriting. The apparatus for generating personal fonts includes a character input unit to receive an input of a character trace from a user, a character recognition unit to recognize a representative character corresponding to an input character from the input character trace, a representative trace generation unit to generate a representative trace expressing a trace of the representative character, and a trace modification unit to modify the trace of the input character by combining a weight value of the generated representative trace with the trace of the input character. | 07-30-2009 |
20140166780 | APPARATUS FOR SUPPLYING WASHER LIQUID OF VEHICLE - An apparatus that supplies washer liquid of a vehicle, in which a washer liquid hose is inserted into a lower end of a pivot shaft by applying a check valve to the lower end of the pivot shaft. In addition, the washer liquid hose is inserted into the pivot shaft and a pipe, to secure a hose route during wiper operation. | 06-19-2014 |
20150123621 | CHARGING METHOD OF SECONDARY BATTERY - Disclosed herein is a charging method of a secondary battery including a first charging step of charging the secondary battery at a first C-rate from an initial charge voltage to a first charge voltage and a second charging step of charging the secondary battery to a target voltage while gradually decreasing a C-rate within a range not exceeding the first C-rate after the voltage of the secondary battery reached the first charge voltage. Consequently, it is possible to prevent deterioration of the battery, thereby improving lifespan characteristics of the battery. | 05-07-2015 |
20150336544 | SPRAY WASHER NOZZLE FOR VEHICLE - A spray washer nozzle for a vehicle may include a nozzle body installed in a hood of a vehicle as a unit for ejecting washer liquid to a windshield, and connected to a hose for supplying the washer liquid and fixedly installed in a hood panel at the same time, and a spray nozzle chip having a passage therein and inserted into a head part of the nozzle body, in which a heat emitter is inserted into and mounted to the passage formed in the interior of the spray nozzle chip such that washer liquid flowing through the passage of the spray nozzle chip is heated while directly contacting the heat emitter. | 11-26-2015 |
Patent application number | Description | Published |
20100020047 | Method of driving a plasma display panel and driver therefor - A method of driving a plasma display panel having a capacitive load formed by a plurality of scan electrodes and a plurality of address electrodes crossing the scan electrodes, using a driver including an address energy recovery circuit (AERC) that applies an address voltage to the address electrodes by an inductor electrically coupled to the address electrodes and resonance of the capacitive load, wherein, during an address period in which one of a scan signal and a non-scan signal is applied to each of the scan electrodes, the method includes applying the scan signal to a current scan electrode, and applying the scan signal to a subsequent scan electrode adjacent the current scan electrode after application of an address signal is complete, the address signal varying from a base state for a period longer than application of the address voltage. | 01-28-2010 |
20140258778 | AUTOMATED TEST EQUIPMENT AND CONTROL METHOD THEREOF - An automated test system for a semiconductor device to concurrently perform multiple device tests is provided. The system may include at least one test client, at least one test site and a test server. The at least one test client is configured to receive a test request of at least one worker and to display a test response. The at least one test site is configured to test at least one device under test (DUT). The test server is configured to communicate with the at least one test client and the at least one test site, divide and/or drive the at least one test site in response to the test request of the at least one test client, and transmit a response of the at least one test site to the at least one test client. | 09-11-2014 |
20140380220 | METHOD AND APPARATUS FOR PROVIDING USER INTERFACE FOR MEDICAL IMAGING - A method for providing a UI for medical imaging of an object includes: generating UIs respectively corresponding to processes for imaging the object; determining a display order of the UIs; receiving a UI completion input of the medical professional regarding the first UI; and displaying the second UI in response to the receiving the UI completion input. The UIs corresponding to the processes for imaging the object may be automatically provided to the medical professional, based on the order. | 12-25-2014 |
20160058397 | MAGNETIC RESONANCE IMAGING (MRI) APPARATUS, METHOD OF CONTROLLING MRI APPARATUS, AND HEAD COIL FOR MRI APPARATUS - Provided is a magnetic resonance imaging (MRI) apparatus including: a display configured to display a three-dimensional (3D) image on an inner wall of a bore within a gantry; a head coil comprising at least one opening formed at a region that corresponds to eyes of a target object and an optical element disposed in the at least one opening; and a controller configured to adjust a perspective of the 3D image based on an input received from the target object or an input received from a user. | 03-03-2016 |
Patent application number | Description | Published |
20110304063 | MULTI-DISC AIR DIFFUSER - A multi-disc air diffuser according to the present invention comprises a bolt having a vent groove formed in a longitudinal direction thereof; a plurality of discs, each of the discs having a bolt joint section to be passed through the bolt, an air room for holding the air supplied through the vent groove, and a nozzle section having a plurality of nozzles which are arranged in an end part of the air room at a regular size and intervals, wherein the lower surface of each of the discs is more than the upper surface thereof and the outer circumference surface of each of the discs is formed to be inclined; and a backflow prevention section for joining to an end part of the bolt to adhere closely the discs to one another, connecting the vent groove to an air supply pipe, and having a check valve to prevent the air flowing backward from the vent groove to the air supply pipe. | 12-15-2011 |
20150246835 | AIR DIFFUSION DEVICE - Disclosed is an air diffusion device including a base coupled to an air supply pipe and having an air discharge hole for discharge of air supplied from the air supply pipe, a perforated cover having a single-layered flat plate shape, and a securing mechanism to secure the perforated cover to the base. The perforated cover having through-holes is coupled to an upper surface of the base to cover the air discharge hole, defining an air guide chamber between the perforated cover and the base. The air diffusion device has ease in assembly/disassembly thereof because the perforated cover is assembled to the base via the securing mechanism separably coupled to the base. Further, through provision of a diaphragm cover to open or close an air discharge hole for discharge of air into the air guide chamber, it is possible to prevent wastewater, sludge, or impurities from entering the air supply pipe. | 09-03-2015 |