Patent application number | Description | Published |
20080225426 | Magnetic recording device including a thermal proximity sensor - A system includes a magnetic device for writing to and reading from a magnetic medium and a sensor disposed adjacent to the magnetic device and proximate to the magnetic medium. The sensor generates signals related to thermal variations in the sensor caused by changes in a distance between the magnetic device and the magnetic medium. | 09-18-2008 |
20090289736 | MAGNETIC SWITCHES FOR SPINWAVE TRANSMISSION - Spinwave transmission systems that include switching devices to direct the transmission of the spinwaves used for data transfer and processing. In one particular embodiment, a system for spinwave transmission has a first magnetic stripe configured for transmission of a spinwave and a second magnetic stripe for transmission of the spinwave, with a gap therebetween. The system includes a coupler that has a first orientation and a second orientation, where in the first orientation, no magnetic connection is made between the magnetic stripes, and in the second orientation, a connection is made between the magnetic stripes. The connection allows transmission of the spinwave from the first magnetic stripe to the second magnetic stripe. The first and second orientation may be the physical position of the coupler, moved by thermal, piezoelectric, or electrostatic forces, or, the first and second orientation may be a magnetic state of the coupler. | 11-26-2009 |
20090302869 | PROBE WITH ELECTROSTATIC ACTUATION AND CAPACITIVE SENSOR - A supported probe device that has a probe tip and probe body, the probe body having a sample facing surface and an opposing surface. The probe tip and a first electrode are on the sample facing surface. A second electrode is present on the probe body opposing surface. A third electrode is spaced from the second electrode, so that the second electrode is between the third electrode and the probe body. A first DC voltage source is electrically coupled to the first electrode, as is a first sensing circuit. A second DC voltage source is electrically coupled to the second electrode, and an AC voltage source electrically coupled to the third electrode. The probe body may be cantilevered. | 12-10-2009 |
20090303076 | WIRELESS AND BATTERY-LESS MONITORING UNIT - A wireless and battery-less sensor device is described. The sensor device includes a mechanical energy harvesting device, a sensor electrically coupled to the mechanical energy harvesting module. The sensor is configured to sense with the power supplied by the mechanical energy harvesting device. Nonvolatile memory is configured to store output from the sensor. A radio frequency energy harvesting module is electrically coupled to a radio frequency transmitter. The radio frequency transmitter is configured to transmit the output from the sensor with the power supplied by the radio frequency energy harvesting device. Systems and methods utilizing the wireless and battery-less sensor device are also described. | 12-10-2009 |
20100032636 | NON-VOLATILE MEMORY CELL WITH ENHANCED FILAMENT FORMATION CHARACTERISTICS - Method and apparatus for constructing a non-volatile memory cell, such as a modified RRAM cell. In some embodiments, a memory cell comprises a resistive storage layer disposed between a first electrode layer and a second electrode layer. Further in some embodiments, the storage layer has a localized region of decreased thickness to facilitate formation of a conductive filament through the storage layer from the first electrode to the second electrode. | 02-11-2010 |
20100037020 | PIPELINED MEMORY ACCESS METHOD AND ARCHITECTURE THEREFORE - A memory array and a method for accessing a memory array including: receiving an address from a host related to relevant data; accessing a first module based on the address received from the host, wherein accessing the first module includes: decoding the address for the first module; enabling a wordline based on the decoded address for the first module and sensing the contents of one or more bits at the decoded address for the first module; and outputting information regarding the first module; and accessing a second module based on the address received from the host, wherein accessing the second module includes: decoding the address for the second module; enabling a wordline based on the decoded address for the second module and sensing the contents of one or more bits at the decoded address for the second module; and outputting information regarding the second module, wherein the step of decoding the address for the second module occurs while the step of enabling a wordline based on the decoded address for the first module and sensing the contents of one or more bits at the decoded address for the first module occurs. | 02-11-2010 |
20100100857 | GENERIC NON-VOLATILE SERVICE LAYER - Method and apparatus for constructing and operating an integrated circuit in an electronic device. In some embodiments, a generic service layer is integrated in a three dimensional integrated circuit and tested using a testing pattern stored in a non-volatile memory. The generic service layer is reconfigured to a permanent non-testing functional component of the integrated circuit. | 04-22-2010 |
20100104115 | MICRO MAGNETIC SPEAKER DEVICE WITH BALANCED MEMBRANE - A micro magnetic device with a micro magnetic speaker unit having a first element, a second element, and a membrane therebetween. Each of the elements comprises a body, a pole of soft magnetic material, an electrically conductive coil positioned around the pole, and a permanent magnet connected to the membrane. The first element and the second element are magnetically identical. A plurality of speaker units can be combined to provide a speaker array. | 04-29-2010 |
20100108978 | PROGRAMMABLE RESISTIVE MEMORY CELL WITH SACRIFICIAL METAL - Programmable metallization memory cells include an electrochemically active electrode and an inert electrode and an ion conductor solid electrolyte material between the electrochemically active electrode and the inert electrode. A sacrificial metal is disposed between the electrochemically active electrode and the inert electrode. The sacrificial metal has a more negative standard electrode potential than the filament forming metal | 05-06-2010 |
20100109153 | HIGH BANDWIDTH PACKAGE - Method and apparatus for constructing and operating a high bandwidth package in an electronic device, such as a data storage device. In some embodiments, a high bandwidth package comprises a first known good die that has channel functions, a second known good die that has a controller function, and a third known good die that has a buffer function. Further in some embodiments, the high bandwidth package has pins that connect to each of the first, second, and third dies. | 05-06-2010 |
20100123470 | PROBE WITH BIDIRECTIONAL ELECTROSTATIC ACTUATION - A probe system that has a probe body comprising at least three arms extending from a central region and a probe tip centrally located on the probe body in the central region. A substrate is proximate the probe body opposite the probe tip. A first electrode is positioned to provide a centrally positioned voltage across the probe body and the substrate and a second electrode set is positioned radially outward from the first electrode, to provide an outer voltage across at least one of the at least three arms and the substrate. The probe structure may have, for example, four arms. Methods of actuating the probe tip are provided. | 05-20-2010 |
20100123534 | MAGNETIC MECHANICAL SWITCH - A method and apparatus for managing data, particularly in regard to non-volatile memory cells. In some embodiments, at least two actuating conductors are at least partially surrounded by a main ferromagnetic core and an adjacent hard magnet. When current is conducted through the actuating conductors, a flexible beam is induced to traverse a first air gap that defines a high resistance position and a low resistance position. | 05-20-2010 |
20100124352 | MICRO MAGNETIC DEVICE WITH MAGNETIC SPRING - A micro magnetic device having a body defining at least part of an enclosed chamber, the body comprising a first sidewall and a second sidewall. A pole comprising a soft magnetic material is within the chamber and an electrically conductive coil is positioned around the pole. A diaphragm is connected to the first sidewall and a permanent dipole magnet is connected to the second sidewall at a first end and to the diaphragm at a second end. The dipole magnet is offset centrally from the pole. The diaphragm may also be offset centrally from the first pole. The micro magnetic device may be made by MEMS or thin film techniques. | 05-20-2010 |
20100140790 | CHIP HAVING THERMAL VIAS AND SPREADERS OF CVD DIAMOND - An integrated circuit chip having a heat spreader comprising CVD diamond extending along the chip support body and thermal vias extending through the support body in regions free of active devices or functional elements. The thermal vias may thermally conductive and electrically conductive or may be thermally conductive and electrically resistive. The integrated circuit chips may be 3D integrated circuit chips. | 06-10-2010 |
20100302849 | NAND FLASH MEMORY WITH INTEGRATED BIT LINE CAPACITANCE - Method and apparatus for outputting data from a memory array having a plurality of non-volatile memory cells arranged into rows and columns. In accordance with various embodiments, charge is stored in a volatile memory cell connected to the memory array, and the stored charge is subsequently discharged from the volatile memory cell through a selected column. In some embodiments, the volatile memory cell is a dynamic random access memory (DRAM) cell from a row of said cells with each DRAM cell along the row coupled to a respective column in the memory array, and each column of non-volatile memory cells comprises Flash memory cells connected in a NAND configuration. | 12-02-2010 |
20100303393 | Microfabricated Fluid Dynamic Bearing - A fluid dynamic bearing formed by a microelectromechanical systems (MEMS) wafer-level batch-fabrication process is provided. The process results in a high performance and high reliability fluid dynamic bearing having features including higher bearing lifetime at high RPM, improved bearing stiffness, durability and thrust/restoring forces capabilities. The present invention is especially useful with small form factor disc drive memory devices having constraints in motor height, such as a 2.5 inch disc drive, requiring high performance including high rotational speed and large areal density. A sacrificial layer is utilized in the process to simultaneously form symmetrical facing surfaces of relatively rotatable components. The facing surfaces define, therebetween, a desired feature, such as a journal bearing, a thrust bearing, a fluid channel, a fluid reservoir, a capillary seal, pressure generating grooves, and other profile geometries. Such geometry control allows for design freedom in obtaining a desired bearing performance and stiffness. | 12-02-2010 |
20110006276 | SCHOTTKY DIODE SWITCH AND MEMORY UNITS CONTAINING THE SAME - A switching element that includes a first semiconductor layer, the first semiconductor layer having a first portion and a second portion; a second semiconductor layer, the second semiconductor layer having a first portion and a second portion; an insulating layer disposed between the first semiconductor layer and the second semiconductor layer; a first metal contact in contact with the first portion of the first semiconductor layer forming a first junction and in contact with the first portion of the second semiconductor layer forming a second junction; a second metal contact in contact with the second portion of the first semiconductor layer forming a third junction and in contact with the second portion of the second semiconductor layer forming a fourth junction, wherein the first junction and the fourth junction are Schottky contacts, and the second junction and the third junction are ohmic contacts. | 01-13-2011 |
20110006377 | Patterning Embedded Control Lines for Vertically Stacked Semiconductor Elements - Various embodiments of the present invention are generally directed to an apparatus with embedded (bottom side) control lines for vertically stacked semiconductor elements, and a method for forming the same. In accordance with various embodiments, a first semiconductor wafer is provided with a first facing surface on which a first conductive layer is formed. The first semiconductor wafer is attached to a second semiconductor wafer to form a multi-wafer structure, the second semiconductor wafer having a second facing surface on which a second conductive wafer is formed. The first conductive layer is contactingly bonded to the second conductive layer to form an embedded combined conductive layer within said structure. Portions of the combined conductive layer are removed to form a plurality of spaced apart control lines that extend in a selected length or width dimension through said structure. | 01-13-2011 |
20110007540 | MAGNETIC SHIELDING FOR INTEGRATED CIRCUIT - A shielded integrated circuit structure including an integrated circuit having a plurality of functional elements thereon, and a tiled array comprising a plurality of shielding elements, each functional element having one of the plurality of shielding elements proximate thereto. The shielding elements comprise a magnetic material having a saturation less than or equal to 20,000 gauss. | 01-13-2011 |
20110007588 | Defective Bit Scheme for Multi-Layer Integrated Memory Device - Various embodiments of the present invention are generally directed to an apparatus and associated method for handling defective bits in a multi-layer integrated memory device. In accordance with some embodiments, the multi-layer integrated memory device is formed from a plurality of vertically stacked semiconductor layers each having a number of storage sub-arrays and redundant sub-arrays. Each semiconductor layer is tested to determine a defect rate for each array, and a defective portion of a first semiconductor layer having a relatively higher defect rate is stored to a redundant sub-array of a second semiconductor layer having a relatively lower defect rate. | 01-13-2011 |
20110007597 | Semiconductor Control Line Address Decoding Circuit - Apparatus and method for decoding addresses of control lines in a semiconductor device, such as a solid state memory (SSM). In accordance with some embodiments, a switching circuit includes an array of switching devices coupled to 2 | 01-13-2011 |
20110008632 | SELF-ALIGNED WAFER BONDING - A wafer article includes a substrate, two or more hydrophilic areas disposed on the substrate, hydrophobic areas surrounding the hydrophilic areas, and a eutectic bonding material disposed on the substrate. A wafer apparatus including two wafers having complimentary hydrophilic regions and eutectic bonding material is disclosed and a method of forming a bonded wafer articles is disclosed. | 01-13-2011 |
20110205830 | Semiconductor Control Line Address Decoding Circuit - Apparatus and method for decoding addresses of control lines in a semiconductor device, such as a solid state memory (SSM). In accordance with some embodiments, a switching circuit includes an array of switching devices coupled to 2 | 08-25-2011 |
20120074466 | 3D MEMORY ARRAY WITH VERTICAL TRANSISTOR - A memory array includes a base circuitry layer and a plurality of memory array layers stacked sequentially to form the memory array. Each memory array layer is electrically coupled to the base circuitry layer. Each memory array layer includes a plurality of memory units. Each memory unit includes a vertical pillar transistor electrically coupled to a memory cell. | 03-29-2012 |
20120074488 | VERTICAL TRANSISTOR WITH HARDENING IMPLATATION - A method includes providing a semiconductor wafer having a plurality of pillar structures extending orthogonally from the semiconductor wafer. Each pillar structure forms a vertical pillar transistor having a top surface and a side surface orthogonal to the top surface. Then a hardening species is implanted into the vertical pillar transistor top surface. Then the vertical pillar transistor side surface is oxidized to form a side surface oxide layer. The side surface oxide layer is removed to form vertical pillar transistor having rounded side surfaces. | 03-29-2012 |
20120080725 | VERTICAL TRANSISTOR MEMORY ARRAY - A method includes providing a semiconductor wafer having a plurality of pillar structures extending orthogonally from the semiconductor wafer. An electrically conducting interconnect element is deposited onto at least selected vertical pillar transistors and a non-volatile variable resistive memory cell is deposited onto the electrically conducting interconnect layer to form a vertical transistor memory array. | 04-05-2012 |
20120099224 | SLIDER FOR A HEAD GIMBAL ASSEMBLY WITH AN INVERTED DIMPLE - Apparatus and method for forming a head gimbal assembly (HGA). In accordance with various embodiments, a slider is formed with opposing first and second side surfaces, an air bearing feature on said first side surface and a dimple extending from said second side surface adapted to facilitate multi-axial rotation of the slider. | 04-26-2012 |
20120104349 | PROGRAMMABLE RESISTIVE MEMORY CELL WITH SACRIFICIAL METAL - Programmable metallization memory cells include an electrochemically active electrode and an inert electrode and an ion conductor solid electrolyte material between the electrochemically active electrode and the inert electrode. A sacrificial metal is disposed between the electrochemically active electrode and the inert electrode. The sacrificial metal has a more negative standard electrode potential than the filament forming metal. | 05-03-2012 |
20120149183 | SCHOTTKY DIODE SWITCH AND MEMORY UNITS CONTAINING THE SAME - A switching element that includes a first semiconductor layer, the first semiconductor layer having a first portion and a second portion; a second semiconductor layer, the second semiconductor layer having a first portion and a second portion; an insulating layer disposed between the first semiconductor layer and the second semiconductor layer; a first metal contact in contact with the first portion of the first semiconductor layer forming a first junction and in contact with the first portion of the second semiconductor layer forming a second junction; a second metal contact in contact with the second portion of the first semiconductor layer forming a third junction and in contact with the second portion of the second semiconductor layer forming a fourth junction, wherein the first junction and the fourth junction are Schottky contacts, and the second junction and the third junction are ohmic contacts. | 06-14-2012 |
20120199915 | Patterning Embedded Control Lines for Vertically Stacked Semiconductor Elements - The present invention is generally directed to an apparatus with embedded (bottom side) control lines for vertically stacked semiconductor elements. In accordance with various embodiments, a first semiconductor wafer is provided with a first facing surface on which a first conductive layer is formed. The first semiconductor wafer is attached to a second semiconductor wafer to form a multi-wafer structure, the second semiconductor wafer having a second facing surface on which a second conductive wafer is formed. The first conductive layer is contactingly bonded to the second conductive layer to form an embedded combined conductive layer within said structure. Portions of the combined conductive layer are removed to form a plurality of spaced apart control lines that extend in a selected length or width dimension through said structure. | 08-09-2012 |
20120199936 | SCHOTTKY DIODE SWITCH AND MEMORY UNITS CONTAINING THE SAME - A switching element that includes a first semiconductor layer, the first semiconductor layer having a first portion and a second portion; a second semiconductor layer, the second semiconductor layer having a first portion and a second portion; an insulating layer disposed between the first semiconductor layer and the second semiconductor layer; a first metal contact in contact with the first portion of the first semiconductor layer forming a first junction and in contact with the first portion of the second semiconductor layer forming a second junction; a second metal contact in contact with the second portion of the first semiconductor layer forming a third junction and in contact with the second portion of the second semiconductor layer forming a fourth junction, wherein the first junction and the fourth junction are Schottky contacts, and the second junction and the third junction are ohmic contacts. | 08-09-2012 |
20120243311 | Non-Sequential Encoding Scheme for Multi-Level Cell (MLC) Memory Cells - Apparatus and method for managing an array of multi-level cell (MLC) memory cells. In accordance with various embodiments, a non-sequential encoding scheme is selected that assigns a different multi-bit logical value to each of a plurality of available physical states of a selected MLC memory cell in relation to write effort associated with each of said plurality of physical states. Data are thereafter written to the selected MLC memory cell in relation to the selected non-sequential encoding scheme. In some embodiments, the MLC memory cell comprises a spin-torque transfer random access memory (STRAM) memory cell. In other embodiments, the MLC memory cell comprises an MLC flash memory cell. | 09-27-2012 |
20130094107 | INDUCED TRANSDUCER HEAD VIBRATION - Vibration of a transducer slider can be used during slider fly height calibration to detect contact of the transducer slider with a disc surface. Amplification of the vibration may cause the transducer slider to tap the disc surface rather than drag across the disc surface when detecting contact with the disc surface. Amplification may be achieved by applying an in-phase AC signal to the transducer slider at the same frequency as the vibration of the slider. Reduced contact between the slider and the disc surface reduces wear on and the possibility of damage to the transducer slider and/or the disc surface. Once the fly height of the transducer slider is calibrated, the AC signal may be shifted out-of-phase with the slider vibration to dampen the slider vibration. | 04-18-2013 |
20130228734 | PROGRAMMABLE RESISTIVE MEMORY CELL WITH SACRIFICIAL METAL - Programmable metallization memory cells include an electrochemically active electrode and an inert electrode and an ion conductor solid electrolyte material between the electrochemically active electrode and the inert electrode. A sacrificial metal is disposed between the electrochemically active electrode and the inert electrode. The sacrificial metal has a more negative standard electrode potential than the filament forming metal | 09-05-2013 |
20130273328 | SELF-ALIGNED WAFER BONDING - A wafer article includes a substrate, two or more hydrophilic areas disposed on the substrate, hydrophobic areas surrounding the hydrophilic areas, and a eutectic bonding material disposed on the substrate. A wafer apparatus including two wafers having complimentary hydrophilic regions and eutectic bonding material is disclosed and a method of forming a bonded wafer articles is disclosed. | 10-17-2013 |
20130277806 | LASER SUBMOUNTS FORMED USING ETCHING PROCESS - A wafer is formed having a plurality of laser-to-slider submount features on a first surface. An etching process is used to form scribe lines between the submounts on the first surface of the wafer. The wafer is separated at the scribe lines to form the submounts. | 10-24-2013 |
20130302948 | 3D ARRAY WITH VERTICAL TRANSISTOR - A memory array includes a base circuitry layer and a plurality of memory array layers stacked sequentially to form the memory array. Each memory array layer is electrically coupled to the base circuitry layer. Each memory array layer includes a plurality of memory units. Each memory unit includes a vertical pillar transistor electrically coupled to a memory cell. | 11-14-2013 |
20140071751 | SOFT ERASURE OF MEMORY CELLS - Apparatus and method for managing data in a memory, such as but not limited to a flash memory array. In accordance with some embodiments, a soft erasure is performed on a block of memory cells by toggling an erasure status value without otherwise affecting a written state of the cells in the block. The memory cells are subsequently overwritten with a set of data using a write polarity direction determined responsive to the toggled erasure status value. | 03-13-2014 |
20140097400 | VERTICAL TRANSISTOR WITH HARDENING IMPLANTATION - A vertical transistor includes a semiconductor wafer having a plurality of pillar structures extending orthogonally from the semiconductor wafer. Each pillar structure forms a vertical pillar transistor having a top surface and a side surface orthogonal to the top surface. Then a hardening ion species is implanted into the vertical pillar transistor top surface. Then the vertical pillar transistor side surface is oxidized to form a side surface oxide layer. The side surface oxide layer is removed to form vertical pillar transistor having rounded side surfaces. | 04-10-2014 |
20140235188 | POWER MANAGEMENT SYSTEM FOR AIRCRAFT CONTAINER TRACKING DEVICE - An RF asset tracking device for cargo containers that has an extended operational life, due to a power management system and multiple power sources. The device has a solar cell and high capacity supercapacitor as a principal power source and a rechargeable battery as an auxiliary power source. Control circuitries manage and regulate the usage of the primary and secondary sources. Together, these power sources provide sufficient power for the tracking device to operate for an extended period of time, thus increasing the period between needed maintenance and decreasing downtime and thus cost. | 08-21-2014 |