| Patent application number | Description | Published |
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| 20090242944 | METHOD OF FORMING A SEMICONDUCTOR DEVICE USING STRESS MEMORIZATION - A stress memorization technique (SMT) film is deposited over a semiconductor device. The SMT film is annealed with a low thermal budget anneal that is sufficient to create and transfer the stress of the SMT film to the semiconductor device. The SMT film is then removed. After the SMT film is removed, a second anneal is applied to the semiconductor device sufficiently long and at a sufficiently high temperature to activate dopants implanted for forming device source/drains. The result of this approach is that there is minimal gate dielectric growth in the channel along the border of the channel. | 10-01-2009 |
| 20090289280 | Method for Making Transistors and the Device Thereof - A semiconductor process and apparatus includes forming <100> channel orientation PMOS transistors ( | 11-26-2009 |
| 20090291540 | CMOS Process with Optimized PMOS and NMOS Transistor Devices - A semiconductor process and apparatus includes forming NMOS and PMOS transistors ( | 11-26-2009 |
| 20100019328 | Semiconductor Resistor Formed in Metal Gate Stack - A semiconductor process and apparatus fabricate a metal gate electrode ( | 01-28-2010 |
| 20100078687 | Method for Transistor Fabrication with Optimized Performance - A semiconductor process and apparatus includes forming <100> channel orientation CMOS transistors ( | 04-01-2010 |
| 20100171180 | METHOD FOR PFET ENHANCEMENT - A semiconductor process and apparatus includes forming PMOS transistors ( | 07-08-2010 |
| 20110169096 | BALANCING NFET AND PFET PERFORMANCE USING STRAINING LAYERS - An integrated circuit structure includes a substrate and at least one pair of complementary transistors on or in the substrate. The pair of complementary transistors comprises a first transistor and a second transistor. The structure also includes a first stress-producing layer on the first transistor and the second transistor, and a second stress-producing layer on the first stress-producing layer over the first transistor and the second transistor. The first stress-producing layer applies tensile strain force on the first transistor and the second transistor. The second stress-producing layer applies compressive strain force on the first stress-producing layer, the first transistor, and the second transistor. | 07-14-2011 |
| 20110180883 | METHOD AND STRUCTURE TO IMPROVE BODY EFFECT AND JUNCTION CAPACITANCE - A method and structure implant a first-type impurity within a substrate to form a channel region within the substrate adjacent a top surface of the substrate; form a gate stack on the top surface of the substrate above the channel region; and implant a second-type impurity within the substrate to form source and drain regions within the substrate adjacent the top surface. The channel region is positioned between the source and drain regions. The second-type impurity has an opposite polarity with respect to the first-type impurity. The method and structure implant a greater concentration of the first-type impurity, relative to a concentration of the first-type impurity within the channel region, to form a primary body doping region within the substrate below (relative to the top surface) the channel region; and to form secondary body doping regions within the substrate below (relative to the top surface) the source and drain regions. | 07-28-2011 |
| 20120196413 | METHOD AND STRUCTURE TO IMPROVE BODY EFFECT AND JUNCTION CAPACITANCE - A method and structure implant a first-type impurity within a substrate to form a channel region within the substrate adjacent a top surface of the substrate; form a gate stack on the top surface of the substrate above the channel region; and implant a second-type impurity within the substrate to form source and drain regions within the substrate adjacent the top surface. The channel region is positioned between the source and drain regions. The second-type impurity has an opposite polarity with respect to the first-type impurity. The method and structure implant a greater concentration of the first-type impurity, relative to a concentration of the first-type impurity within the channel region, to form a primary body doping region within the substrate below (relative to the top surface) the channel region; and to form secondary body doping regions within the substrate below (relative to the top surface) the source and drain regions. | 08-02-2012 |
| Patent application number | Description | Published |
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| 20080197412 | MULTI-LAYER SOURCE/DRAIN STRESSOR - A method for forming a semiconductor device includes forming a recess in a source region and a recess in a drain region of the semiconductor device. The method further includes forming a first semiconductor material layer in the recess in the source region and a second semiconductor material layer in the recess in the drain region, wherein each of the first semiconductor material layer and the second semiconductor material layer are formed using a stressor material having a first ratio of an atomic concentration of a first element and an atomic concentration of a second element, wherein the first element is silicon and a first level of concentration of a doping material. The method further includes forming additional semiconductor material layers overlying the first semiconductor material layer and the second semiconductor material layer that have a different ratio of the atomic concentration of the first element and the second element. | 08-21-2008 |
| 20080203449 | SOURCE/DRAIN STRESSOR AND METHOD THEREFOR - A method for forming a semiconductor device is provided. The method includes forming a gate structure overlying a substrate. The method further includes forming a sidewall spacer adjacent to the gate structure. The method further includes performing an angled implant in a direction of a source side of the semiconductor device. The method further includes annealing the semiconductor device. The method further includes forming recesses adjacent opposite ends of the sidewall spacer in the substrate to expose a first type of semiconductor material. The method further includes epitaxially growing a second type of semiconductor material in the recesses, wherein the second type of semiconductor material has a lattice constant different from a lattice constant of the first type of semiconductor material to create stress in a channel region of the semiconductor device. | 08-28-2008 |
| 20080206940 | FORMING A SEMICONDUCTOR DEVICE HAVING EPITAXIALLY GROWN SOURCE AND DRAIN REGIONS - A semiconductor device structure is made on a semiconductor substrate having a semiconductor layer having isolation regions. A first gate structure is formed over a first region of the semiconductor layer, and a second gate structure is over a second region of the semiconductor layer. A first insulating layer is formed over the first and second regions. The first insulating layer can function as a mask during an etch of the semiconductor layer and can be removed selective to the isolation regions and the sidewall spacers. The first insulating layer is removed from over the first region to leave a remaining portion of the first insulating layer over the second region. The semiconductor layer is recessed in the first region adjacent to the first gate to form recesses. A semiconductor material is epitaxially grown in the recesses. The remaining portion of the first insulating layer is removed. | 08-28-2008 |
| 20080261362 | METHOD OF MAKING A SEMICONDUCTOR DEVICE USING A STRESSOR - A method for forming a semiconductor device includes providing a substrate and forming a p-channel device and an n-channel device, each of the p-channel device and the n-channel device comprising a source, a drain, and a gate, the p-channel device having a first sidewall spacer and the n-channel device having a second sidewall spacer. The method further includes forming a liner and forming a tensile stressor layer over the liner and removing a portion of the tensile stressor layer from a region overlying the p-channel device. The method further includes transferring a stress characteristic of an overlying portion of a remaining portion of the tensile stressor layer to a channel of the n-channel device. The method further includes using the remaining portion of the tensile stressor layer as a hard mask, forming a first recess and a second recess adjacent the gate of the p-channel device. | 10-23-2008 |
| 20080296620 | ELECTRONIC DEVICE INCLUDING A SEMICONDUCTOR FIN AND A PROCESS FOR FORMING THE ELECTRONIC DEVICE - An electronic device can include a semiconductor fin overlying an insulating layer. The electronic device can also include a semiconductor layer overlying the semiconductor fin. The semiconductor layer can have a first portion and a second portion that are spaced-apart from each other. In one aspect, the electronic device can include a conductive member that lies between and spaced-apart from the first and second portions of the semiconductor layer. The electronic device can also include a metal-semiconductor layer overlying the semiconductor layer. In another aspect, the semiconductor layer can abut the semiconductor fin and include a dopant. In a further aspect, a process of forming the electronic device can include reacting a metal-containing layer and a semiconductor layer to form a metal-semiconductor layer. In another aspect, a process can include forming a semiconductor layer, including a dopant, abutting a wall surface of a semiconductor fin. | 12-04-2008 |
| 20110163360 | METHOD FOR FORMING A TRANSISTOR HAVING GATE DIELECTRIC PROTECTION AND STRUCTURE - A transistor structure is formed by providing a semiconductor substrate and providing a gate above the semiconductor substrate. The gate is separated from the semiconductor substrate by a gate insulating layer. A source and a drain are provided adjacent the gate to define a transistor channel underlying the gate and separated from the gate by the gate insulating layer. A barrier layer is formed by applying nitrogen or carbon on opposing outer vertical sides of the transistor channel between the transistor channel and each of the source and the drain. In each of the nitrogen and the carbon embodiments, the vertical channel barrier retards diffusion of the source/drain dopant species into the transistor channel. There are methods for forming the transistor structure. | 07-07-2011 |
| 20130102143 | METHOD OF MAKING A NON-VOLATILE MEMORY CELL HAVING A FLOATING GATE - Forming an NVM structure includes forming a floating gate layer; forming a first dielectric layer over the floating gate layer; forming a plurality of nanocrystals over the first dielectric layer; etching the first dielectric layer using the plurality of nanocrystals as a mask to form dielectric structures, wherein the floating gate layer is exposed between adjacent dielectric structures; etching a first depth into the floating gate layer using the plurality of dielectric structures as a mask to form a plurality of patterned structures, wherein the first depth is less than a thickness of the floating gate layer; patterning the floating gate layer to form a floating gate; forming a second dielectric layer over the floating gate, wherein the second dielectric layer is formed over the patterned structures and on the floating gate layer between adjacent patterned structures; and forming a control gate layer over the second dielectric layer. | 04-25-2013 |
| 20130109141 | TRANSISTORS WITH DIFFERENT THRESHOLD VOLTAGES | 05-02-2013 |
