Patent application number | Description | Published |
20100323635 | Apparatus and methods for minimizing phase interaction between multiple tuner solutions - Embodiments of systems and methods for implementing multi-channel tuners are generally described herein. Other embodiments may be described and claimed. | 12-23-2010 |
20100323636 | Apparatus and methods for implementing multi-channel tuners - Embodiments of systems and methods for implementing multi-channel tuners are generally described herein. Other embodiments may be described and claimed. | 12-23-2010 |
20100330932 | Apparatus and methods for efficient implementation of tuners - Embodiments of systems and methods for the efficient implementation of tuners are generally described herein. Other embodiments may be described and claimed. | 12-30-2010 |
20110019785 | Alignment of channel filters for multiple-tuner apparatuses - Apparatuses, systems, and methods that align channel filters for dual tuners are disclosed. An embodiment may comprise an IC having two tuners. Each tuner may have a low-noise amplifier, a mixer with a local oscillator, and channel filter. To perform a channel filter alignment, a bandwidth controller may cross-couple the local oscillator of each tuner to the input of the mixer of the opposite tuner. The bandwidth controller may adjust the frequencies of the local oscillators to produce different configuration tone frequencies at the outputs of the mixers, which are inputs to the channel filters. The bandwidth controller may then determine an amplitude difference between two separate measurements of a channel filter output and, based on a comparison of the measurements with predicted values, increment or decrement the filter bandwidth for each tuner and store parameters for the channel filters which create the largest signal amplitudes. | 01-27-2011 |
20110244812 | APPARATUS AND METHODS FOR MINIMIZING PERFORMANCE LOSS IN MULTIPLE TUNER SOLUTIONS - Embodiments of systems and methods for implementing multi-channel tuners are generally described herein. Other embodiments may be described and claimed. | 10-06-2011 |
20120076191 | Apparatus and method to process signals from one or more transmission sources - A receiver and a method to process signals from one or more transmission sources. The receives includes a front-end having: an input coupling path to route an analog input signal received from one or more transmission sources; an equalizer to generate an equalized signal from the analog input signal; and an ADC to generate a digitized signal from the equalized signal. The method includes routing the analog input signal through an input coupling path; equalizing the analog input signal to generate an equalized signal therefrom; and digitizing the equalized signal to generate a digitized signal therefrom. | 03-29-2012 |
20140204985 | DIGITAL TRANSCEIVER WITH SWITCHED CAPACITOR SAMPLING MIXERS AND SWITCHED CAPACITOR AMPLIFIERS - Examples of a digital transceiver, a switched-capacitor sampling mixer, and an N-stage switched-capacitor amplifier are generally described herein. The digital transceiver may include a plurality of switched-capacitor sampling mixers and a plurality of N-stage switched-capacitor amplifiers. Each mixer samples a received differential RF signal. The pair of N-stage switched-capacitor amplifiers operates as charge redistribution amplifiers. Each N-stage switched-capacitor amplifier provides a near-constant capacitive load for one of the mixers. | 07-24-2014 |
Patent application number | Description | Published |
20080242234 | Minimizing the noise figure of broadband frequency agile radio receivers - A wireless device includes an impedance transforming network that couples an antenna to a Low Noise Amplifier (LNA) and includes at least one digitally controllable variable capacitor that may be adjusted to maximize an impedance transformation ratio on a desired channel. A tuned response centered on the desired channel provides attenuation to undesired channels. | 10-02-2008 |
20090081975 | REMOVING HARMONIC AND CO-EXISTENCE INTERFERENCE IN RADIO RECEIVERS - A wireless device includes a two-stage filter that separates UHF and VHF transmission bands in such a way as to maximize cross channel isolation, so preventing cross channel signal contamination and additionally protecting all signals from host coexistence blocking transmissions and harmonics of the wanted signals without the requirement for additional or selectable filter arrangements. | 03-26-2009 |
20100164617 | DYNAMIC SIGNAL CONTAMINATION SUPPRESSION - A self-configurable amplifier and method of amplification, including an RF signal level detector having an input connected to an RF signal, and an output configured to produce a control signal responsive to a power level of the RF signal. The control signal is supplied to a parametric adjustment circuit that includes an input connected to the control signal, and an output configured to provide a negative feedback responsive to the control signal. The negative feedback is supplied to an RF amplifier that includes an input forming an input of the self-configurable amplifier, an output forming an output of the self-configurable amplifier, and a control port connected to the output of the parametric adjustment circuit, such that one or more parameters of the RF amplifier is responsive to the negative feedback. | 07-01-2010 |
20110149171 | Efficient tuning and demodulation techniques - Techniques for the reception and processing of wireless signals are disclosed. For instance, an apparatus may include multiple receiving paths, a content stream generation module, and a distribution module. The multiple receiving paths include a first receiving path that generates a first decoded signal from an input RF signal in accordance with a first tuning setting. The content stream generation module has first and second inputs. Based on decoded signals received at the first and second inputs, the content stream generation module may generate first and second content streams, respectively. In situations where both the first and second content streams correspond to the first tuning setting, the distribution module provides the first decoded signal to both the first and second inputs of the content stream generation module. Also, a control module may remove operational power from any of the plurality of receiving paths that are currently being unused. | 06-23-2011 |
20110151818 | CORRECTING QUADRATURE CROSSTALK CONTAMINATION IN RECEIVERS - An apparatus, a method and a system for correcting a phase imbalance are described. Embodiments may measure the phase imbalance inherent in a tuner and use the imbalance measure to correct the output of the tuner. Embodiments may include a tone generator to produce a single frequency tone and a tuner to receive the single frequency tone and output an intermediate frequency. The intermediate frequency may be corrected by a correction loop. Other embodiments are described and claimed. | 06-23-2011 |
20110293043 | DC OFFSET CORRECTION TECHNIQUES - Techniques are disclosed that involve the reduction of DC offsets. For instance, embodiments may receive a baseband signal, and determine a DC characteristic of the baseband signal. When the DC characteristic has a value that is outside of a predetermined range, a correction signal is adjusted. The correction signal is injected into the baseband signal. | 12-01-2011 |
20120249107 | COUPLED INDUCTOR TO FACILITATE INTEGRATED POWER DELIVERY - An embodiment of the present invention provides an apparatus, comprising a surface mounted device (SMD) inductor, the SMD inductor including at least two counter wound aircoils formed on a same SMD former; wherein the at least two counter wound aircoils are connected to three terminals on the SMD former, wherein a single terminal is connected to a common node of both windings with two independent terminals accessing the other winding node. | 10-04-2012 |
20130154732 | POWER MANAGEMENT IN TRANSCEIVERS - Various embodiments are directed to apparatuses and methods to reduce average power dissipation in transceiver stages such as power amplifiers and low noise amplifiers (LNAs) that process signals of varying output amplitudes. Power dissipation may be reduced by varying the supply voltage in sympathy with the amplitude of the signal and/or the stage current density which may also be varied in sympathy with the signal amplitude. | 06-20-2013 |
20140091955 | SYSTEM, APPARATUS AND METHOD TO IMPROVE ANALOG-TO-DIGITAL CONVERTER OUTPUT - According to various embodiments, a system, an apparatus and a method are presented that relate to determining and correcting signal imbalances between output samples of an analog-to-digital (A-D) converter array (that may be implemented as part of a wideband ADC). A statistic module and correction module are associated with the A-D converter array. The statistic module is configured to receive digital samples from the plurality of A-D converters, and generate a statistical sample value for each A-D converter using a set of digital samples received therefrom. The correction module is configured to, for at least one of the plurality of A-D converters, determine an offset value by comparing the statistical sample value for the at least one of the plurality of A-D converters with a reference value, and apply the offset value to a digital sample from that at least one A-D converter to generate a corrected digital sample. | 04-03-2014 |
20140091958 | METHODS AND ARRANGEMENTS FOR HIGH-SPEED DIGITAL-TO-ANALOG CONVERSION - Embodiments may comprise logic such as hardware and/or code for high-speed digital-to-analog conversion of signals. Many embodiments comprise a demultiplexer to distribute sets of bits to digital-to-analog converters, the digital-to-analog converters to receive the sets of bits and the operate concurrently to convert the sets of bits from digital representations of signal segments to output analog signal segments, and an interleaver to interleave the analog signal segments from each of digital-to-analog converters in the sequence to generate an analog signal. In many embodiments, the interleaver is adapted to interleave the analog signal segments by latching magnitudes of each of the analog signal segments to an interleaved output near ends of clock cycles to attenuate non-linearities in the magnitudes of each of the analog signal segments when the magnitudes are output. | 04-03-2014 |
20140091960 | METHODS AND ARRANGEMENTS FOR HIGH-SPEED ANALOG-TO-DIGITAL CONVERSION - Logic such as hardware and/or code for high-speed analog-to-digital conversion of a signal. Logic may receive an analog signal as an input to a sampling receiver. The sampling receiver may implement a successive approximation register (SAR), analog-to-digital converter (ADC) to produce the digital output. Logic may re-task a comparator of the SAR ADC during a sampling mode to generate a digital comparator output that represents a comparison of a voltage of the charge on a capacitance of the DAC against a threshold reference voltage. The digital comparator output may be applied to the input of automatic gain control (AGC) logic. The AGC logic may receive the digital comparator signal which is representative of one sample of a multiple sample, sample cycle, allowing the AGC logic to generate a gain control signal that is responsive to both total composite average and peak amplitudes. | 04-03-2014 |
20140198013 | BACKSIDE REDISTRIBUTION LAYER PATCH ANTENNA - A patch antenna system comprising: an integrated circuit die having an active side including an active layer, and a backside; a dielectric layer formed on the backside; and a redistribution layer formed on the dielectric layer wherein the redistribution layer forms an array of patches. The patch antenna further comprises a plurality of through-silicon vias (TSV), wherein the TSVs electrically connect the array of patches to the active layer. | 07-17-2014 |
20140266439 | METHODS AND SYSTEMS TO PROVIDE LOW NOISE AMPLIFICATION - An amplifier, including a voltage-to-current converter (V2I) to control an output current based on an input voltage, resistive degeneration circuitry to reduce baseband gain of the voltage-to-current converter, capacitive degeneration circuitry to increase passband gain of the voltage-to-current converter, and impedance control circuitry to compensate for negative input impedance of the capacitive degeneration circuitry. The V2I may include series-connected complimentary V2Is. The impedance control circuitry may include resistive negative feedback to provide a real part of input impedance, which may increase a frequency range for which the amplifier is linear. Capacitive degeneration and associated phase compensation may increase a frequency range for which the resistive feedback is negative. The amplifier may be configured as a single-input/single-output system and/or as a differential system. | 09-18-2014 |
20140320102 | VOLTAGE REGULATOR WITH ADAPTIVE CONTROL - Generally, this disclosure describes an apparatus, systems and methods for adaptively controlling a voltage regulator. The apparatus may include a differencing circuit configured to generate an error signal based on a difference between a reference voltage and the output voltage of the voltage regulator; a proportional control circuit coupled to the differencing circuit, the proportional control circuit configured to generate a control signal proportional to the error signal; a derivative control circuit coupled to the differencing circuit, the derivative control circuit configured to generate a control signal based on the derivative of the error signal; a summer circuit coupled to the proportional control circuit and the derivative control circuit, the summer circuit configured to sum the proportional control signal and the derivative control signal; a PWM signal generator circuit coupled to the summer circuit, the PWM generator circuit configured to adjust the PWM modulation based on the summed control signal; and a state monitor circuit configured to monitor the state of the output voltage and perform a gain adjustment on the proportional control signal and the derivative control signal based on the monitored state. | 10-30-2014 |
20140349714 | SYSTEM FOR ANALOG TO DIGITAL CONVERSION WITH IMPROVED SPURIOUS FREE DYNAMIC RANGE - Generally, this disclosure describes an apparatus, systems and methods for analog to digital conversion with improved spurious free dynamic range. The system includes a segmented ADC circuit with a plurality of interleaved ADC segments, the segmented ADC circuit configured to generate a digital signal including a channel with an associated channel frequency; a frequency down-converter circuit coupled to the segmented ADC circuit, the frequency down-converter circuit configured to frequency shift the digital signal by a frequency offset; a spur frequency prediction circuit coupled to the frequency down-converter circuit, the spur frequency prediction circuit configured to predict frequencies of spurs generated by the ADC segments, the prediction based on the number of ADC segments and based on the sampling rate of the digital signal; the spur frequency prediction circuit further configured to generate the frequency offset based on the predicted spur frequencies and based on a frequency band of the channel; and a filter circuit coupled to the frequency down-converter circuit, the filter circuit configured to remove one or more of the spurs from the frequency shifted digital signal to generate a filtered signal. | 11-27-2014 |
20150035507 | DUAL MODE VOLTAGE REGULATOR WITH DYNAMIC RECONFIGURATION CAPABILITY - A dual mode voltage regulator according to one embodiment includes a passive regulator circuit; a switching regulator circuit; and a controller circuit configured to monitor operational parameters of the dual mode voltage regulator and selectively couple either the passive regulator circuit or the switching regulator circuit between an input voltage port and an output load. The selective coupling is based on the monitoring of parameters including current through the output load, voltage at the input voltage port and voltage at the output load as well as the availability of a system clock signal. | 02-05-2015 |
20150042295 | DUAL MODE VOLTAGE REGULATOR WITH RECONFIGURATION CAPABILITY - A dual mode voltage regulator according to one embodiment includes a passive regulator circuit, a switching regulator circuit, and a controller circuit configured to determine parameters of an external select input. The controller is configured to selectively couple, on a cold boot up, either the passive regulator circuit or the switching regulator circuit between an input voltage port and an output load based on the determination of parameters. | 02-12-2015 |