Connelly, CA
Adam Connelly, Berkeley, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20150039423 | Enabling Participation in an Online Community using Visual Machine-Readable Symbols - A facility for coordinating an online discussion is described. The facility receives an indication that a user has captured a machine-readable symbol encoding an identifier that identifies a particular online discussion. In response, the facility incorporates into an online forum that hosts this online discussion an indication that this user captured a symbol encoding an identifier that identifies this online discussion. | 02-05-2015 |
Charles Connelly, Capistrano Beach, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20120204321 | ANTI-ROLL GLOVES AND METHODS OF MANUFACTURE - Gloves and methods of manufacturing gloves that provide structural support elements to prevent or minimize glove roll, and that alternatively or in addition provide protection against blunt force to the back of the hand, including methods of manufacture, specifically including molding or screening the structural support elements and/or protective cushions to the back of the hand side of the glove. | 08-16-2012 |
Daniel Connelly, San Francisco, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20140344772 | SEMI-LOCAL BALLISTIC MOBILITY MODEL - A transistor model defines the carrier mobility as a combination of both drift-diffusion mobility and ballistic mobility. The ballistic mobility is calculated based on the assumption that the kinetic energy of carriers near an injection point is no greater than the potential energy difference of carriers near that injection point. The abruptness of the onset of velocity saturation, as well as the asymptotic velocity associated therewith is made dependent on the degree to which the velocity is ballistically limited. The model further takes into account the inertial effects on the velocity and/or charge flux associated with carriers. The model computes the mobility and hence the velocity of carriers in accordance with their positions in the channel both along the direction of the current flow as well as the direction perpendicular to the current flow. | 11-20-2014 |
Daniel J. Connelly, Redwood City, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090104770 | METHOD FOR DEPINNING THE FERMI LEVEL OF A SEMICONDUCTOR AT AN ELECTRICAL JUNCTION AND DEVICES INCORPORATING SUCH JUNCTIONS - An electrical device in which an interface layer is disposed between and in contact with a metal and a Si-based semiconductor, the interface layer being of a thickness effective to depin of the Fermi level of the semiconductor while still permitting current to flow between the metal and the semiconductor. The interface layer may include a layer of a passivating material (e.g., made from nitrogen, oxygen, oxynitride, arsenic, hydrogen and/or fluorine) and sometimes also includes a separation layer. In some cases, the interface layer may be a monolayer of a semiconductor passivating material. The interface layer thickness corresponds to a minimum specific contact resistance of less than or equal to 10Ω-μm | 04-23-2009 |
| 20110169124 | METHOD FOR DEPINNING THE FERMI LEVEL OF A SEMICONDUCTOR AT AN ELECTRICAL JUNCTION AND DEVICES INCORPORATING SUCH JUNCTIONS - An electrical device in which an interface layer is disposed between and in contact with a metal and a Si-based semiconductor, the interface layer being of a thickness effective to depin of the Fermi level of the semiconductor while still permitting current to flow between the metal and the semiconductor. The interface layer may include a layer of a passivating material (e.g., made from nitrogen, oxygen, oxynitride, arsenic, hydrogen and/or fluorine) and sometimes also includes a separation layer. In some cases, the interface layer may be a monolayer of a semiconductor passivating material. The interface layer thickness corresponds to a minimum specific contact resistance of less than or equal to 10 Ω-μm | 07-14-2011 |
| 20120280294 | METHOD FOR DEPINNING THE FERMI LEVEL OF A SEMICONDUCTOR AT AN ELECTRICAL JUNCTION AND DEVICES INCORPORATING SUCH JUNCTIONS - An electrical device in which an interface layer comprising arsenic is disposed between and in contact with a conductor and a semiconductor. In some cases, the interface layer may be a monolayer of arsenic. | 11-08-2012 |
Daniel J. Connelly, San Francisco, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090101972 | PROCESS FOR FABRICATING A FIELD-EFFECT TRANSISTOR WITH DOPING SEGREGATION USED IN SOURCE AND/OR DRAIN - Source and/or drain regions of a transistor are first doped with an appropriate dopant and a metal is subsequently deposited. After heating, a silicide will displace the dopant, creating an increased density of dopants at the border of the silicided region. The dopants that are adjacent to or in the gate region of the device will form a thin layer. The silicide or other reactant material is then removed and replaced with a desired source/drain material, while leaving the layer of dopant immediately adjacent to the newly deposited source/drain material. | 04-23-2009 |
| 20090104746 | CHANNEL STRAIN INDUCED BY STRAINED METAL IN FET SOURCE OR DRAIN - A process for forming a FET (e.g., an n-FET or a p-FET), in which during formation a metal which makes up a source or drain of the transistor is stressed so that stress is induced in a semiconductor channel of the transistor. | 04-23-2009 |
| 20100065887 | FIELD EFFECT TRANSISTOR SOURCE OR DRAIN WITH A MULTI-FACET SURFACE - FET configurations in which two (or more) facets are exposed on a surface of a semiconductor channel, the facets being angled with respect to the direction of the channel, allow for conformal deposition of a convex or concave S/D. A convex tip of the S/D enhances electric fields at the interface, reducing the resistance between the S/D and the channel. In contrast, a S/D having a concave tip yields a dual-gate FET that emphasizes reduced short-channel effects rather than electric field enhancement. The use of self-limiting, selective wet etches to expose the facets facilitates process control, control of interface chemistry, and manufacturability. | 03-18-2010 |
| 20110008953 | METHOD FOR MAKING SEMICONDUCTOR INSULATED-GATE FIELD-EFFECT TRANSISTOR HAVING MULTILAYER DEPOSITED METAL SOURCE(S) AND/OR DRAIN(S) - A metal source/drain field effect transistor is fabricated such that the source/drain regions are deposited, multilayer structures, with at least a second metal deposited on exposed surfaces of a first metal. | 01-13-2011 |
| 20110092047 | Strained Semiconductor Using Elastic Edge Relaxation, a Buried Stressor Layer and a Sacrificial Stressor Layer - The present invention relates to creating an active layer of strained semiconductor using a combination of buried and sacrificial stressors. That is, a process can strain an active semiconductor layer by transferring strain from a stressor layer buried below the active semiconductor layer and by transferring strain from a sacrificial stressor layer formed above the active semiconductor layer. As an example, the substrate may be silicon, the buried stressor layer may be silicon germanium, the active semiconductor layer may be silicon and the sacrificial stressor layer may be silicon germanium. Elastic edge relaxation is preferably used to efficiently transfer strain to the active layer. | 04-21-2011 |
| 20110124170 | PROCESS FOR FABRICATING A SELF-ALIGNED DEPOSITED SOURCE/DRAIN INSULATED GATE FIELD-EFFECT TRANSISTOR - Processes for forming self-aligned, deposited source/drain, insulated gate, transistors and, in particular, FETs. By depositing a source/drain in a recess such that it remains only in the recess, the source/drain can be formed self-aligned to a gate and/or a channel of such a device. For example, in one such process a gate structure of a transistor may be formed and, in a material surrounding the gate structure, a recess created so as to be aligned to an edge of the gate structure. Subsequently, a source/drain conducting material may be deposited in the recess. Such a source/drain conducting material may be deposited, in some cases, as layers, with one or more such layers being planarized following its deposition. In this way, the conducting material is kept within the boundaries of the recess. | 05-26-2011 |
| 20110210376 | INSULATED GATE FIELD EFFECT TRANSISTOR HAVING PASSIVATED SCHOTTKY BARRIERS TO THE CHANNEL - A transistor includes a semiconductor channel disposed nearby a gate and in an electrical path between a source and a drain, wherein the channel and at least one of the source or the drain are separated by an interface layer so as to form a channel-interface layer-source/drain junction in which a Fermi level of the semiconductor channel is depinned in a region near the junction and the junction has a specific contact resistance of less than approximately 1000 Ω-μm | 09-01-2011 |
| 20130119446 | METHOD FOR DEPINNING THE FERMI LEVEL OF A SEMICONDUCTOR AT AN ELECTRICAL JUNCTION AND DEVICES INCORPORATING SUCH JUNCTIONS - An electrical device in which an interface layer comprising arsenic is disposed between and in contact with a conductor and a semiconductor. In some cases, the interface layer may be a monolayer of arsenic. | 05-16-2013 |
| 20130140629 | INSULATED GATE FIELD EFFECT TRANSISTOR HAVING PASSIVATED SCHOTTKY BARRIERS TO THE CHANNEL - A transistor having at least one passivated Schottky barrier to a channel includes an insulated gate structure on a p-type substrate in which the channel is located beneath the insulated gate structure. The channel and the insulated gate structure define a first and second undercut void regions that extend underneath the insulated gate structure toward the channel from a first and a second side of the insulated gate structure, respectively. A passivation layer is included on at least one exposed sidewall surface of the channel, and metal source and drain terminals are located on respective first and second sides of the channel, including on the passivation layer and within the undercut void regions beneath the insulated gate structure. At least one of the metal source and drain terminals comprises a metal that has a work function near a valence band of the p-type substrate. | 06-06-2013 |
| 20140284666 | INSULATED GATE FIELD EFFECT TRANSISTOR HAVING PASSIVATED SCHOTTKY BARRIERS TO THE CHANNEL - A transistor having at least one passivated Schottky barrier to a channel includes an insulated gate structure on a p-type substrate in which the channel is located beneath the insulated gate structure. The channel and the insulated gate structure define a first and second undercut void regions that extend underneath the insulated gate structure toward the channel from a first and a second side of the insulated gate structure, respectively. A passivation layer is included on at least one exposed sidewall surface of the channel and metal source and drain terminals are located on respective first and second sides of the channel, including on the passivation layer and within the undercut void regions beneath the insulated gate structure. At least one of the metal source and drain terminals comprises a metal that has a work function near a valence band of the p-type substrate. | 09-25-2014 |
David Connelly, San Francisco, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100205263 | SIP SERVER ARCHITECTURE FOR IMPROVING LATENCY DURING MESSAGE PROCESSING - Systems and methods are provided for improving latency during message processing in a network environment via the use of SIP server architecture. The SIP server can be comprised of an engine tier and a state tier distributed on a cluster network. The engine tier can send and receive messages and execute various processes. The state tier can maintain in-memory state data associated with various SIP sessions. The state tier can store various long lived data objects and the engine tier can contain short lived data objects. The state data can be maintained in partitions comprised of state replicas. When processing messages, the engine can pull state data objects from the state tier, use the objects and push them back to the state tier after processing is complete. If one state replica is unavailable, such as during garbage collection, the engine can retrieve the objects from another replica in the partition. | 08-12-2010 |
Jeffrey A. Connelly, San Jose, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20130326220 | RECIPIENT BLIND CRYPTOGRAPHIC ACCESS CONTROL FOR PUBLICLY HOSTED MESSAGE AND DATA STREAMS - Private message system, method, and apparatus are described. A private message that includes encrypted data and identifying information indicating a recipient client device authorized to read the private message is stored at a server computer. Since the client devices perform all encryption and decryption processing, the server computer stores the private message in a platform agnostic manner and without performing any encryption/decryption related processes. Although any number of recipient devices can receive the private message, only a recipient client device authorized in accordance with the identifying information can read the private message. | 12-05-2013 |
John Patrick Connelly, Santa Cruz, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110106616 | FILTER FOR USER INFORMATION BASED ON ENABLEMENT OF PERSISTENT IDENTIFICATION - A method, system, apparatus, and storage medium for determining that a client device is enabled for persistent identification, and that may operate as a filter for user information based on whether the client is enabled for persistent identification. A first communication is received regarding a request by the client for a web page. At least one application level data structure is then provided for storage by the client, that persistently identifies at least one characteristic of the client. A second communication is then received that includes a representation of the application level data structures provided, and a comparison is made between the data structures provided and the representation received to determine whether the client is enabled for persistent identification. If persistent identification is enabled, the client may then be provided with advertisements or other content related to the client interests or characteristics. | 05-05-2011 |
John Patrick Connelly, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20120047005 | Real Time Audience Forecasting - A system, method, apparatus and processor readable media are described for real-time prediction of an advertising audience volume through analysis of historical audience data, and tuning of the predicted audience volume. Embodiments enable a user to specify a query for audience volume prediction. Such a query may be a Boolean combination of various audience categories. A time range may be determined that indicates the amount of historical data that is to be analyzed to make the audience volume prediction in real time. Employing the user-specified query, an audience volume prediction may be provided for a future time period, based on an analysis of retrieved historical audience data for the time range. Embodiments may also enable a user to tune the predicted audience volume through modification of the query through one or more iterations. | 02-23-2012 |
Kyler Mikhail Connelly, Castro Valley, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20150126988 | SECURE CRYOSURGICAL TREATMENT SYSTEM - A method for cryogenically treating tissue. A connection is detected between a probe having a disposable secure processor (DSP) to a handpiece having a master control unit (MCU) and a handpiece secure processor (HSP), the probe having at least one cryogenic treatment applicator. The probe is fluidly coupled to a closed coolant supply system within the handpiece via the connection. An authentication process is initiated between the DSP and the HSP using the MCU. As a result of the authentication process, one of at least two predetermined results is determined, the at least two predetermined results being that the probe is authorized and non-authorized. | 05-07-2015 |
Mariah Connelly, Sacramento, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100323448 | Methods For Producing Biological Substances In Enzyme-Deficient Mutants Of Aspergillus niger - The present invention relates to methods of producing a heterologous biological substance, comprising: (a) cultivating a mutant of a parent | 12-23-2010 |
Michael V. Connelly, Palos Verde Estates, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080265098 | Configuration and method of use of optimized cooperative space vehicles - A spacecraft system that includes a primary space vehicle and a secondary space vehicle, both of which are designed to optimize payload capacity and launch weight of the primary space vehicle. The primary and secondary space vehicles combine to form an on-orbit space vehicle capable of performing functions and maneuvers that exceed the physical capabilities of the primary space vehicle at the time of its launch. The spacecraft system is designed to minimize propellant containment-related disturbances while maintaining a standard level of functionality. The primary space vehicle is designed to be incapable of independently performing a propellant-intensive orbit change maneuver. Instead the primary space vehicle is designed to couple to a secondary space vehicle having propellant and thrust capability sufficient to perform an orbit change maneuver when the primary and secondary space vehicles are coupled. The secondary space vehicle may also be designed to deliver additional payload to the primary space vehicle. | 10-30-2008 |
Scott Connelly, Corona Del Mar, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090169675 | Milk Derived Composition and Use to Enhance Muscle Mass or Muscle Strength - The invention relates to the production of compositions containing milk products for use as a nutritional supplement. More specifically, it relates to compositions containing whey growth factor extract, as well as methods for supplementing the nutritional needs of individuals undertaking resistance exercise training. According to one aspect of the invention, there is provided the use of a composition comprising whey growth factor extract, isolated from a milk product by cation exchange chromatography, to increase skeletal muscle strength. | 07-02-2009 |
| 20130078313 | MILK DERIVED COMPOSITION AND USE TO ENHANCE MUSCLE MASS OR MUSCLE STRENGTH - The invention relates to the production of compositions containing milk products for use as a nutritional supplement. More specifically, it relates to compositions containing whey growth factor extract, as well as methods for supplementing the nutritional needs of individuals undertaking resistance exercise training. According to one aspect of the invention, there is provided the use of a composition comprising whey growth factor extract, isolated from a milk product by cation exchange chromatography, to increase skeletal muscle strength. | 03-28-2013 |
Sharon R. Connelly, San Anselmo, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20120197781 | ADVANCE BLOCKING AND PAYMENT HOLDING STRATEGIES - Embodiments of the invention are directed to systems, methods and computer program products for identifying risk patterns for accounts based on a plurality of rules, and executing risk mitigation routines for those accounts for which risk patterns have been identified. If an advance block risk pattern is identified for an account, an advance block routine is executed for the account. If a payment hold risk pattern is identified for an account, a payment hold routine is executed for the account. | 08-02-2012 |
| 20120209760 | RISK IDENTIFICATION SYSTEM AND JUDGMENTAL REVIEW INTERFACE - Embodiments of the invention are directed to systems, methods and computer program products for identifying one or more risk patterns for an account based on a plurality of rules, determining whether to add an account on to a judgmental review queue based at least in part on the one or more risk patterns identified for the account, and allowing a user to execute one or more risk mitigation actions for the account in order to curb possible financial losses that may result from the identified risk patterns. | 08-16-2012 |