| Patent application number | Description | Published |
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| 20110038083 | GUARDED ELECTRICAL OVERSTRESS PROTECTION CIRCUIT - Disclosed embodiments are directed to an electrical overstress protection circuit. The electrical overstress protection circuit may include an intermediate node receiving a reference voltage, a first pair of clamp devices, having opposite polarity, clamping an input signal line to the intermediate node, and a second pair of clamp devices, each clamping the intermediate node to one of two reference potentials. The electrical overstress protection circuit may also include a filter connected to the intermediate node to reduce noise at the intermediate node. | 02-17-2011 |
| 20110043251 | Opportunistic Timing Control in Mixed-Signal System-On-Chip Designs - An integrated circuit may include a plurality of circuit sub-systems that include at least one converter circuit operating in respective critical phases and non-critical phases of operation, a clock distribution circuit that has an input for an externally-supplied clock signal that is active during the non-critical phases and inactive during the critical phases, and a clock generator to generate an internal clock signal to the converter circuit that is active when the external-supplied clock signal is inactive. | 02-24-2011 |
| 20110304488 | FILTER FOR THE SUPPRESSION OF NOISE IN RESOLVER-TO-DIGITAL CONVERTERS - A system and method for reducing noise in resolver-to-digital converters (RDC) using a cascaded tracking loop filter. In some embodiments, one or more tracking loop filters may be implemented in a cascade to attenuate carrier harmonic frequencies in the digitized output of an RDC. Where a plurality of tracking loop filters are implemented, the output of one tracking loop filter may be input into a successive tracking loop filter. | 12-15-2011 |
| 20120013492 | PROGRAMMABLE LINEARITY CORRECTION CIRCUIT FOR DIGITAL-TO- ANALOG CONVERTER - The invention provides a systematic error correction network coupled to a converter. The converter may display a systematic non-linearity error, and the systematic error correction network shapes a correction transform function that acts like counter distortion function for the non-linearity error. The systematic error correction network then scales the correction transform function according to a reference variable, where the magnitude of non-linearity error is related to the reference variable. The scaled correction transform function is then applied to the converter path in order to generate a corrected analog output signal. | 01-19-2012 |
| 20120200350 | RESET AND RESETTABLE CIRCUITS - An amplifier system can include a feedback amplifier circuit having an amplifier, a feedback capacitor connected between an input terminal and an output terminal of the amplifier by at least one first switch, and a reset capacitor connected across the feedback capacitor by at least one second switch and between a pair of reference voltages by at least one third switch. During an input-signal processing phase of operation, a control circuit may close the at least one first switch and open the at least one second switch to electrically connect the feedback capacitor between the input and output terminals to engage feedback processing by the feedback amplifier circuit, and close the third switch to electrically connect the reset capacitor between the first and second voltages to charge the reset capacitor to a selectable voltage difference. During a reset phase of operation, the control circuit may open the at least one third switch, close the at least one second switch and open the at least one first switch to electrically connect the reset capacitor across the feedback capacitor to reset the feedback capacitor using the reset capacitor. The amplifier system can optionally include a plurality of the feedback amplifier circuits. | 08-09-2012 |
| 20130070805 | ON-CHIP TEMPERATURE SENSOR USING INTERCONNECT METAL - An accurate, cost-efficient temperature sensor may be integrated into an integrated circuit (IC) using common materials as the IC's interconnect metallization. The temperature sensor may include an impedance element having a length of metal made of the interconnect metal, a current source connected between a first set of contacts at opposite ends of the impedance element, and an analog-to-digital converter connected between a second set of contacts at opposite ends of the impedance element. The temperature sensor may exploits the proportional relationship between the metal's resistance and temperature to measure ambient temperature. Alternatively, such a temperature sensor may be used on disposable chemical sensors where the impedance element is made of a common metal as conductors that connect a sensor reactant to sensor contacts. In either case, because the impedance element is formed of a common metal as other interconnect, it is expected to incur low manufacturing costs. | 03-21-2013 |
| 20130119502 | ELECTRICAL OVERSTRESS PROTECTION USING THROUGH-SILICON-VIA (TSV) - A semiconductor device formed on a substrate includes a first diode junction formation, a second diode junction formation, and at least one through-silicon-via (TSV), in which a cathode and an anode of the first diode are cross-connected to an anode and cathode of the second diode through the at least one TSV for achieving electrical robustness in through-silicon-via based integrated circuits, including photosensitive devices and circuits for signal processing applications. | 05-16-2013 |
| 20130175669 | ELECTRICAL OVERSTRESS PROTECTION USING THROUGH-SILICON-VIA (TSV) - A semiconductor device formed on a substrate includes a first diode junction formation, a second diode junction formation, and at least one through-silicon-via (TSV), in which a cathode and an anode of the first diode are cross-connected to an anode and cathode of the second diode through the at least one TSV for achieving electrical robustness in through-silicon-via based integrated circuits, including photosensitive devices and circuits for signal processing applications. | 07-11-2013 |
| 20130194118 | CORRELATED DOUBLE-SAMPLE DIFFERENCING WITHIN AN ADC - A circuit system for performing correlated double sampling may include a signal sampling stage having an amplifier with a feedback capacitor and a pair of storage capacitors coupled to an output of the amplifier, and a differential analog to digital converter (ADC) having a pair of inputs coupled respectively to storage capacitors of the signal sampling stage. The signal sampling stage may receive reset and signal values from a sensor device and may store processed versions of those signals on respective storage capacitors. The differential ADC may generate a digital value representing a signal captured by the sensor device from a differential digitization operation performed on the processed versions of the reset and signal values. In this manner, the system may correct for any signal errors introduced by components of the sampling stage. | 08-01-2013 |
| 20130329853 | REDUCED-NOISE INTEGRATOR, DETECTOR AND CT CIRCUITS - A detector circuit can include an integrator having an amplifier, a first feedback capacitor connected between an input and output of the amplifier, one or more additional feedback capacitors connected by at least one switch between the input and output of the amplifier, and a shunt capacitor connected to the output of the amplifier. The shunt capacitor can be selected to have a capacitance value greater than that of a minimum but less than that of a maximum feedback capacitance. The detector circuit can further include a sampling circuit having a sampling capacitor connected to the output of the integrator amplifier through at least one switch, wherein the sampling capacitor is separate from the shunt capacitor. A computed tomography imaging apparatus can include the detector circuit. | 12-12-2013 |
| 20140333463 | SPLIT-PATH DATA ACQUISITION SIGNAL CHAIN - The present disclosure provides for split-path data acquisition chains and associated signal processing methods. An exemplary integrated circuit for providing a split-path data acquisition signal chain includes an input terminal for receiving an analog signal; an output terminal for outputting a digital signal; and at least two frequency circuit paths coupled with the input terminal and the output terminal, wherein the at least two frequency circuit paths are configured to process different frequency components of the analog signal and recombine the processed, different frequency components, thereby providing the digital signal. | 11-13-2014 |
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| 20090309036 | SILICON DETECTOR AND METHOD FOR CONSTRUCTING SILICON DETECTORS - Disclosed is a die having photodetectors provided on a first surface thereof. The die includes an insulative shell member, a conductive shell member and a photodetector conductor. The insulative shell member extends around a periphery of the photodetector receptors and extending through a depth of the semiconductor die. The conductive shell member bridges the insulative shell member and extends through the depth of the semiconductor die. The photodetector conductors are provided on the first surface of the semiconductor die and electrically couple respective photodetectors with a corresponding conductive shell member. Also disclosed is a process for making a semiconductor die and an integrated circuit structure. | 12-17-2009 |
| 20130015322 | APPARATUS AND METHOD FOR REDUCING COMMON-MODE ERRORAANM KUSUDA; YoshinoriAACI San JoseAAST CAAACO USAAGP KUSUDA; Yoshinori San Jose CA USAANM CARREAU; Gary RobertAACI PlaistowAAST NHAACO USAAGP CARREAU; Gary Robert Plaistow NH USAANM COLN; Michael C.AACI LexingtonAAST MAAACO USAAGP COLN; Michael C. Lexington MA US - Apparatus and methods reduce common-mode error. An integrated circuit includes a plurality of signal channels, a first proxy channel, and a subtraction block. The signal channels are configured to receive a plurality of input signals and to generate a plurality of output signals, and each of the signal channels has a substantially similar circuit topology. The first proxy channel has a substantially similar circuit topology as the plurality of signal channels, and includes an output that can vary in relation to a common-mode error of the signal channels. The subtraction block is configured to generate a plurality of modified output signals by using the output of the first proxy channel to reduce the common-mode error of the plurality of output signal channels. | 01-17-2013 |
| 20140193090 | APPARATUS AND METHODS FOR REDUCING COMMON-MODE NOISE IN AN IMAGING SYSTEM - Apparatus and methods reduce common-mode error. An integrated circuit includes a plurality of signal channels, a first proxy channel, and a subtraction block. The signal channels are configured to receive a plurality of input signals and to generate a plurality of output signals, and each of the signal channels has a substantially similar circuit topology. The first proxy channel has a substantially similar circuit topology as the plurality of signal channels, and includes an output that can vary in relation to a common-mode error of the signal channels. The subtraction block is configured to generate a plurality of modified output signals by using the output of the first proxy channel to reduce the common-mode error of the plurality of output signal channels. | 07-10-2014 |
