Patent application number | Description | Published |
20100183961 | INTEGRATED CIRCUIT LAYOUT DESIGN - Provided is a method including layout design of an integrated circuit. A first pattern is provided. The first pattern includes an array of dummy line features and a plurality of spacer elements abutting the dummy line features. A second pattern is provided. The second pattern defines an active region of an integrated circuit device. An edge spacer element of the active region is determined. A dummy line feature of the array of dummy line features is biased (e.g., increased in width), the dummy line feature is adjacent an edge spacer element. | 07-22-2010 |
20100252816 | High-Mobility Multiple-Gate Transistor with Improved On-to-Off Current Ratio - A multi-gate transistor includes a semiconductor fin over a substrate. The semiconductor fin includes a central fin formed of a first semiconductor material; and a semiconductor layer having a first portion and a second portion on opposite sidewalls of the central fin. The semiconductor layer includes a second semiconductor material different from the first semiconductor material. The multi-gate transistor further includes a gate electrode wrapping around sidewalls of the semiconductor fin; and a source region and a drain region on opposite ends of the semiconductor fin. Each of the central fin and the semiconductor layer extends from the source region to the drain region. | 10-07-2010 |
20100252862 | Source/Drain Engineering of Devices with High-Mobility Channels - An integrated circuit structure includes a substrate, and a channel over the substrate. The channel includes a first III-V compound semiconductor material formed of group III and group V elements. A gate structure is over the channel. A source/drain region is adjacent the channel and includes a group-IV region formed of a doped group-IV semiconductor material selected from the group consisting essentially of silicon, germanium, and combinations thereof. | 10-07-2010 |
20100276668 | Reducing Source/Drain Resistance of III-V Based Transistors - An integrated circuit structure includes a substrate; a channel layer over the substrate, wherein the channel layer is formed of a first III-V compound semiconductor material; a highly doped semiconductor layer over the channel layer; a gate dielectric penetrating through and contacting a sidewall of the highly doped semiconductor layer; and a gate electrode on a bottom portion of the gate dielectric. The gate dielectric includes a sidewall portion on a sidewall of the gate electrode. | 11-04-2010 |
20100301390 | Gradient Ternary or Quaternary Multiple-Gate Transistor - An integrated circuit structure includes a semiconductor substrate; insulation regions over the semiconductor substrate; and an epitaxy region over the semiconductor substrate and having at least a portion in a space between the insulation regions. The epitaxy region includes a III-V compound semiconductor material. The epitaxy region also includes a lower portion and an upper portion over the lower portion. The lower portion and the semiconductor substrate have a first lattice mismatch. The upper portion and the semiconductor substrate have a second lattice mismatch different from the first lattice mismatch. | 12-02-2010 |
20100301392 | Source/Drain Re-Growth for Manufacturing III-V Based Transistors - A method of forming an integrated circuit structure includes providing a substrate, and epitaxially growing a first semiconductor layer over the substrate. The first semiconductor layer includes a first III-V compound semiconductor material formed of group III and group V elements. The method further includes forming a gate structure on the first semiconductor layer, and forming a gate spacer on at least one sidewall of the gate structure. After the step of forming the gate structure, a second semiconductor layer including a second III-V compound semiconductor material is epitaxially grown on the first semiconductor layer. | 12-02-2010 |
20100317184 | METHOD FOR REDUCING INTERFACIAL LAYER THICKNESS FOR HIGH-K AND METAL GATE STACK - A method for reducing interfacial layer (IL) thickness for high-k dielectrics and metal gate stack is provided. In one embodiment, the method includes forming an interfacial layer on a semiconductor substrate, etching back the interfacial layer, depositing a high-k dielectric material over the interfacial layer, and forming a metal gate over the high-k dielectric material. The IL can be chemical oxide, ozonated oxide, thermal oxide, or formed by ultraviolet ozone (UVO) oxidation process from chemical oxide, etc. The etching back of IL can be performed by a Diluted HF (DHF) process, a vapor HF process, or any other suitable process. The method can further include performing UV curing or low thermal budget annealing on the interfacial layer before depositing the high-k dielectric material. | 12-16-2010 |
20110008956 | SELF-ASSEMBLY PATTERN FOR SEMICONDUCTOR INTEGRATED CIRCUIT - A method of fabricating a semiconductor device is provided which includes providing a substrate. A material layer is formed over the substrate. A polymer layer is formed over the material layer. A nano-sized feature is self-assembled using a portion of the polymer layer. The substrate is patterned using the nano-sized feature. | 01-13-2011 |
20110024794 | FIN STRUCTURE FOR HIGH MOBILITY MULTIPLE-GATE TRANSISTOR - A vertical fin structure for a semiconductor transistor includes a semiconductor substrate, a fin layer on top of the substrate, a capping layer overlaying the fin layer, wherein the substrate comprises group IV semiconductor material, the fin layer comprises group IV semiconductor material, the capping layer comprises semiconductor compound from group III-V. The fin layer can comprise Ge, SiGe, SiC, or any combinations thereof. The semiconductor substrate can comprise Si, Ge, SiGe, or SiC. The capping layer can comprise GaAs, InGaAs, InAs, InSb, GaSb, GaN, InP, or any combinations thereof. The capping layer can provide more than a 4 percent lattice mismatch with the semiconductor substrate. The fin layer can be located in between shallow trench insulation (STI) layers that provide isolation from adjacent devices. The vertical fin structure can further include a high-k dielectric layer overlaying the capping layer and a metal gate layer overlaying the high-k dielectric layer. | 02-03-2011 |
20110049613 | ACCUMULATION TYPE FINFET, CIRCUITS AND FABRICATION METHOD THEREOF - A FinFET includes a substrate and a fin structure on the substrate. The fin structure includes a channel between a source and a drain, wherein the source, the drain, and the channel have the first type dopant. The channel includes a Ge, SiGe, or III-V semiconductor. A gate dielectric layer is located over the channel and a gate is located over the gate dielectric layer. | 03-03-2011 |
20110054658 | Method for Constant Power Density Scaling - A method for constant power density scaling in MOSFETs is provided. A method for manufacturing an integrated circuit includes computing fixed scaling factors for a first fabrication process based on a second fabrication process, computing settable scaling factors for the integrated circuit to be fabricated using the first fabrication process, determining parameters of the integrated circuit based on the settable scaling factors, and manufacturing the integrated circuit using the determined parameters. The first fabrication process creates devices having a smaller device dimension than the second fabrication process and the settable scaling factors are set based on the fixed scaling factors. | 03-03-2011 |
20110062492 | High-Quality Hetero-Epitaxy by Using Nano-Scale Epitaxy Technology - An integrated circuit structure includes a semiconductor substrate formed of a first semiconductor material; two insulators in the semiconductor substrate; and a semiconductor region between and adjoining sidewalls of the two insulators. The semiconductor region is formed of a second semiconductor material different from the first semiconductor material, and has a width less than about 50 nm. | 03-17-2011 |
20110068405 | FIN FIELD EFFECT TRANSISTOR - An exemplary structure for the fin field effect transistor comprises a substrate comprising a major surface; a plurality of fin structures protruding from the major surface of the substrate, wherein each fin structure comprises an upper portion and a lower portion separated at a transition location at where the sidewall of the fin structure is at an angle of 85 degrees to the major surface of the substrate, wherein the upper portion has sidewalls that are substantially perpendicular to the major surface of the substrate and a top surface having a first width, wherein the lower portion has tapered sidewalls on opposite sides of the upper portion and a base having a second width larger than the first width; and a plurality of isolation structures between the fin structures, wherein each isolation structure extends from the major surface of the substrate to a point above the transition location. | 03-24-2011 |
20110068407 | Germanium FinFETs with Metal Gates and Stressors - An integrated circuit structure includes an n-type fin field effect transistor (FinFET) and a p-type FinFET. The n-type FinFET includes a first germanium fin over a substrate; a first gate dielectric on a top surface and sidewalls of the first germanium fin; and a first gate electrode on the first gate dielectric. The p-type FinFET includes a second germanium fin over the substrate; a second gate dielectric on a top surface and sidewalls of the second germanium fin; and a second gate electrode on the second gate dielectric. The first gate electrode and the second gate electrode are formed of a same material having a work function close to an intrinsic energy level of germanium. | 03-24-2011 |
20110079829 | FINFETS AND METHODS FOR FORMING THE SAME - A Fin field effect transistor (FinFET) includes a fin-channel body over a substrate. A gate electrode is disposed over the fin-channel body. At least one source/drain (S/D) region is disposed adjacent to the fin-channel body. The at least one S/D region is substantially free from including any fin structure. | 04-07-2011 |
20110086491 | Growing a III-V Layer on Silicon using Aligned Nano-Scale Patterns - A method of forming an integrated circuit structure includes providing a wafer having a silicon substrate; forming a plurality of shallow trench isolation (STI) regions in the silicon substrate; and forming recesses by removing top portions of the silicon substrate between opposite sidewalls of the plurality of STI regions. Substantially all long sides of all recesses in the silicon substrate extend in a same direction. A III-V compound semiconductor material is then epitaxially grown in the recesses. | 04-14-2011 |
20110117730 | Growing III-V Compound Semiconductors from Trenches Filled with Intermediate Layers - A method of forming an integrated circuit structure includes forming an insulation layer over at least a portion of a substrate; forming a plurality of semiconductor pillars over a top surface of the insulation layer. The plurality of semiconductor pillars is horizontally spaced apart by portions of the insulation layer. The plurality of semiconductor pillars is allocated in a periodic pattern. The method further includes epitaxially growing a III-V compound semiconductor film from top surfaces and sidewalls of the semiconductor pillars. | 05-19-2011 |
20110151359 | INTEGRATED CIRCUIT LAYOUT DESIGN - Provided is a photolithography apparatus including a photomask. The photomask includes a pattern having a plurality, of features, in an example, dummy line features. The pattern includes a first region being in the form of a localized on-grid array and a second region where at least one of the features has an increased width. The apparatus may include a second photomask which may define an active region. The feature with an increased width may be adjacent, and outside, the defined active region. | 06-23-2011 |
20110180846 | Method for Forming Antimony-Based FETs Monolithically - An integrated circuit structure includes a substrate and a first and a second plurality of III-V semiconductor layers. The first plurality of III-V semiconductor layers includes a first bottom barrier over the substrate; a first channel layer over the first bottom barrier; and a first top barrier over the first channel layer. A first field-effect transistor (FET) includes a first channel region, which includes a portion of the first channel layer. The second plurality of III-V semiconductor layers is over the first plurality of III-V semiconductor layers and includes a second bottom barrier; a second channel layer over the second bottom barrier; and a second top barrier over the second channel layer. A second FET includes a second channel region, which includes a portion of the second channel layer. | 07-28-2011 |
20110304021 | Epitaxial Growth of III-V Compound Semiconductors on Silicon Surfaces - A device includes a silicon substrate, and a III-V compound semiconductor region over and contacting the silicon substrate. The III-V compound semiconductor region has a U shaped interface with the silicon substrate, with radii of the U shaped interface being smaller than about 1,000 nm. | 12-15-2011 |
20110306179 | MOCVD for Growing III-V Compound Semiconductors on Silicon Substrates - A device includes providing a silicon substrate; annealing the silicon substrate at a first temperature higher than about 900° C.; and lowering a temperature of the silicon substrate from the first temperature to a second temperature. A temperature lowering rate during the step of lowering the temperature is greater than about 1° C./second. A III-V compound semiconductor region is epitaxially grown on a surface of the silicon substrate using metal organic chemical vapor deposition (MOCVD). | 12-15-2011 |
20120001239 | Formation of III-V Based Devices on Semiconductor Substrates - A device includes a semiconductor substrate, and insulation regions in the semiconductor substrate. Opposite sidewalls of the insulation regions have a spacing between about 70 nm and about 300 nm. A III-V compound semiconductor region is formed between the opposite sidewalls of the insulation regions. | 01-05-2012 |
20120009690 | IN-SITU SPECTROMETRY - The present disclosure provides a system for in-situ spectrometry. The system includes a wafer-cleaning machine that cleans a surface of a semiconductor wafer using a cleaning solution. The system also includes a spectrometry machine that is coupled to the wafer-cleaning machine. The spectrometry machine receives a portion of the cleaning solution from the wafer-cleaning machine. The portion of the cleaning solution collects particles from the wafer during the cleaning. The spectrometry machine is operable to analyze a particle composition of a portion of the wafer based on the portion of the cleaning solution, while the wafer remains in the wafer-cleaning machine during the particle composition analysis. | 01-12-2012 |
20120015503 | METHOD OF FORMING SEMICONDUCTOR STRUCTURE - A method of forming a semiconductor device includes chemically cleaning a surface of a substrate to form a chemical oxide material on the surface. At least a portion of the chemical oxide material is removed at a removing rate of about 2 nanometer/minute (nm/min) or less. Thereafter, a gate dielectric layer is formed over the surface of the substrate. | 01-19-2012 |
20120021589 | METHOD OF FABRICATION OF A SEMICONDUCTOR DEVICE HAVING REDUCED PITCH - Provided is a photolithography apparatus including a photomask. The photomask includes a pattern having a plurality of features, in an example, dummy line features. The pattern includes a first region being in the form of a localized on-grid array and a second region where at least one of the features has an increased width. The apparatus may include a second photomask which may define an active region. The feature with an increased width may be adjacent, and outside, the defined active region. | 01-26-2012 |
20120025201 | Inverted Trapezoidal Recess for Epitaxial Growth - A semiconductor device having an epitaxial layer a method of manufacture thereof is provided. The semiconductor device has a substrate with a trench formed therein and a recess formed below the trench. The recess has sidewalls with a (111) crystal orientation. The depth of the trench is such that the depth is greater than or equal to one-half a length of sidewalls of the recess. An epitaxial layer is formed in the recess and the trench. The depth of the trench is sufficient to cause dislocations formed between the interface of the semiconductor substrate and the epitaxial layer to terminate along sidewalls of the trench. | 02-02-2012 |
20120028477 | Self-Assembly Pattern for Semiconductor Integrated Circuit - A method of fabricating a semiconductor device is provided which includes providing a substrate. A material layer is formed over the substrate. A polymer layer is formed over the material layer. A nano-sized feature is self-assembled using a portion of the polymer layer. The substrate is patterned using the nano-sized feature. | 02-02-2012 |
20120094467 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD WITH IMPROVED EPITAXIAL QUALITY OF III-V COMPOUND ON SILICON SURFACES - Stacking faults are reduced or eliminated by epitaxially growing a III-V compound semiconductor region in a trench followed by capping and annealing the region. The capping layer limits the escape of atoms from the region and enables the reduction or elimination of stacking faults along with the annealing. | 04-19-2012 |
20120094504 | METHODS OF FORMING GATE DIELECTRIC MATERIAL - A method of forming gate dielectric material includes forming a silicon oxide gate layer over a substrate. The silicon oxide gate layer is treated with a first ozone-containing gas. After treating the silicon oxide gate layer, a high dielectric constant (high-k) gate dielectric layer is formed over the treated silicon oxide gate layer. | 04-19-2012 |
20120211803 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD WITH IMPROVED EPITAXIAL QUALITY OF III-V COMPOUND ON SILICON SURFACES - Stacking faults are reduced or eliminated by epitaxially growing a III-V compound semiconductor region in a trench followed by capping and annealing the region. The capping layer limits the escape of atoms from the region and enables the reduction or elimination of stacking faults along with the annealing. | 08-23-2012 |
20120273899 | SYSTEM AND METHODS FOR CONVERTING PLANAR DESIGN TO FINFET DESIGN - A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET structures are generated in a matching fashion. The resulting FinFET structures are then optimized. Dummy patterns and a new metal layer may be generated before the FinFET layout is verified and outputted. | 11-01-2012 |
20120278776 | SYSTEM AND METHODS FOR CONVERTING PLANAR DESIGN TO FINFET DESIGN - A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET structures are generated. | 11-01-2012 |
20120278777 | SYSTEM AND METHODS FOR CONVERTING PLANAR DESIGN TO FINFET DESIGN - A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET structures are generated in a matching fashion. The resulting FinFET structures are then optimized. Dummy patterns and a new metal layer may be generated before the FinFET layout is verified and outputted. | 11-01-2012 |
20120278781 | SYSTEM AND METHODS FOR CONVERTING PLANAR DESIGN TO FINFET DESIGN - A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET structures are generated in a matching fashion. The resulting FinFET structures are then optimized. Dummy patterns and a new metal layer may be generated before the FinFET layout is verified and outputted. | 11-01-2012 |
20120306002 | ACCUMULATION TYPE FINFET, CIRCUITS AND FABRICATION METHOD THEREOF - This description relates to a fin field-effect-transistor (FinFET) including a substrate and a fin structure on the substrate. The fin structure includes a channel between a source and a drain, wherein the source, the drain, and the channel have a first type dopant, and the channel comprises at least one of a Ge, SiGe, or III-V semiconductor. The FinFET further includes a gate dielectric layer over the channel and a gate over the gate dielectric layer. The FinFET further includes a nitride spacer on the substrate adjacent the gate and an oxide layer between the nitride spacer and the gate and between the nitride spacer and the substrate. | 12-06-2012 |
20120322253 | METHOD FOR REDUCING INTERFACIAL LAYER THICKNESS FOR HIGH-K AND METAL GATE STACK - This description relates to a method including forming an interfacial layer over a semiconductor substrate. The method further includes etching back the interfacial layer. The method further includes performing an ultraviolet (UV) curing process on the interfacial layer. The UV curing process includes supplying a gas flow rate ranging from 10 standard cubic centimeters per minute (sccm) to 5 standard liters per minute (slm), wherein the gas comprises inert gas, and heating the interfacial layer at a temperature less than or equal to 700° C. The method further includes depositing a high-k dielectric material over the interfacial layer. | 12-20-2012 |
20120329254 | Method for Forming Antimony-Based FETs Monolithically - An integrated circuit structure includes a substrate and a first and a second plurality of III-V semiconductor layers. The first plurality of III-V semiconductor layers includes a first bottom barrier over the substrate; a first channel layer over the first bottom barrier; and a first top barrier over the first channel layer. A first field-effect transistor (FET) includes a first channel region, which includes a portion of the first channel layer. The second plurality of III-V semiconductor layers is over the first plurality of III-V semiconductor layers and includes a second bottom barrier; a second channel layer over the second bottom barrier; and a second top barrier over the second channel layer. A second FET includes a second channel region, which includes a portion of the second channel layer. | 12-27-2012 |
20130001591 | FINFET DESIGN AND METHOD OF FABRICATING SAME - An integrated circuit device and method for manufacturing the same are disclosed. An exemplary device includes a semiconductor substrate having a substrate surface and a trench isolation structure disposed in the semiconductor substrate for isolating an NMOS region of the device and from a PMOS region of the device. The device further includes a first fin structure comprising silicon or SiGe disposed over a layer of III-V semiconductor material having a high band gap energy and a lattice constant greater than that of Ge; a second fin structure comprising silicon or SiGe disposed over a layer of III-V semiconductor material having a high band gap energy and a lattice constant smaller than that of Ge; and a gate structure disposed over and arranged perpendicular to the first and second fin structures. | 01-03-2013 |
20130011983 | In-Situ Doping of Arsenic for Source and Drain Epitaxy - A method includes forming a gate stack over a semiconductor region, and recessing the semiconductor region to form a recess adjacent the gate stack. A silicon-containing semiconductor region is epitaxially grown in the recess to form a source/drain stressor. Arsenic is in-situ doped during the step of epitaxially growing the silicon-containing semiconductor region. | 01-10-2013 |
20130011984 | Using Hexachlorodisilane as a Silicon Precursor for Source/Drain Epitaxy - A method includes forming a gate stack over a semiconductor region, and recessing the semiconductor region to form a recess adjacent the gate stack. A silicon-containing semiconductor region is epitaxially grown in the recess to form a source/drain region, wherein the step of epitaxially growing is performed using hexachlorodisilane as a precursor. | 01-10-2013 |
20130020612 | Re-growing Source/Drain Regions from Un-Relaxed Silicon Layer - A method of forming an n-type metal-oxide-semiconductor (NMOS) field-effect transistor (FET) includes forming a silicon germanium layer, and forming a silicon layer over the silicon germanium layer. A gate stack is formed over the silicon layer. The silicon layer is recessed to form a recess adjacent the gate stack. A silicon-containing semiconductor region is epitaxially grown in the recess to form a source/drain stressor, wherein the silicon-containing semiconductor region forms a source/drain region the NMOS FET. | 01-24-2013 |
20130034948 | Method of Manufacturing a Semiconductor Device - A method for fabricating a semiconductor device is disclosed. An exemplary method includes a providing substrate. A dielectric layer is formed over the semiconductor substrate and a stop layer is formed over the dielectric layer. The stop layer and the dielectric layer comprise a different material. The method further includes forming a patterned hard mask layer over the stop layer and etching the semiconductor substrate through the patterned hard mask layer to form a plurality of trenches. The method also includes depositing an isolation material on the semiconductor substrate and substantially filling the plurality of trenches. Thereafter, performing a CMP process on the semiconductor substrate, wherein the CMP process stops on the stop layer. | 02-07-2013 |
20130043512 | Semiconductor Device Manufacturing Methods and Methods of Forming Insulating Material Layers - Semiconductor device manufacturing methods and methods of forming insulating material layers are disclosed. In one embodiment, a method of forming a composite insulating material layer of a semiconductor device includes providing a workpiece and forming a first sub-layer of the insulating material layer over the workpiece using a first plasma power level. A second sub-layer of the insulating material layer is formed over the first sub-layer of the insulating material layer using a second plasma power level, and the workpiece is annealed. | 02-21-2013 |
20130043545 | SEMICONDUCTOR DEVICE HAVING HIGH-K GATE DIELECTRIC LAYER AND MANUFACTURING METHOD THEREOF - The disclosure relates to integrated circuit fabrication and, more particularly, to a semiconductor device with a high-k gate dielectric layer. An exemplary structure for a semiconductor device comprises a substrate and a gate structure disposed over the substrate. The gate structure comprises a dielectric portion and an electrode portion that is disposed over the dielectric portion, and the dielectric portion comprises a carbon-doped high-k dielectric layer on the substrate and a carbon-free high-k dielectric layer adjacent to the electrode portion. | 02-21-2013 |
20130049068 | FINFET DEVICE HAVING A CHANNEL DEFINED IN A DIAMOND-LIKE SHAPE SEMICONDUCTOR STRUCTURE - The present disclosure provides a FinFET device. The FinFET device comprises a semiconductor substrate of a first semiconductor material; a fin structure of the first semiconductor material overlying the semiconductor substrate, wherein the fin structure has a top surface of a first crystal plane orientation; a diamond-like shape structure of a second semiconductor material disposed over the top surface of the fin structure, wherein the diamond-like shape structure has at least one surface of a second crystal plane orientation; a gate structure disposed over the diamond-like shape structure, wherein the gate structure separates a source region and a drain region; and a channel region defined in the diamond-like shape structure between the source and drain regions. | 02-28-2013 |
20130075818 | 3D Semiconductor Device and Method of Manufacturing Same - A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate and a 3D structure disposed over the substrate. The semiconductor device further includes a dielectric layer disposed over the 3D structure, a WFMG layer disposed over the dielectric layer, and a gate structure disposed over the WFMG layer. The gate structure traverses the 3D structure and separates a source region and a drain region of the 3D structure. The source and drain region define a channel region therebetween. The gate structure induces a stress in the channel region. | 03-28-2013 |
20130075833 | MULTI-LAYER SCAVENGING METAL GATE STACK FOR ULTRA-THIN INTERFACIAL DIELCTRIC LAYER - A multi-layer scavenging metal gate stack, and methods of manufacturing the same, are disclosed. In an example, a gate stack disposed over a semiconductor substrate includes an interfacial dielectric layer disposed over the semiconductor substrate, a high-k dielectric layer disposed over the interfacial dielectric layer, a first conductive layer disposed over the high-k dielectric layer, and a second conductive layer disposed over the first conductive layer. The first conductive layer includes a first metal layer disposed over the high-k dielectric layer, a second metal layer disposed over the first metal layer, and a third metal layer disposed over the second metal layer. The first metal layer includes a material that scavenges oxygen impurities from the interfacial dielectric layer, and the second metal layer includes a material that adsorbs oxygen impurities from the third metal layer and prevents oxygen impurities from diffusing into the first metal layer. | 03-28-2013 |
20130078772 | Tilt Implantation for Forming FinFETs - In a method for forming FinFETs, a photo resist is formed to cover a first semiconductor fin in a wafer, wherein a second semiconductor fin adjacent to the first semiconductor fin is not covered by the photo resist. An edge of the photo resist between and parallel to the first and the second semiconductor fins is closer to the first semiconductor fin than to the second semiconductor fin. A tilt implantation is performed to form a lightly-doped source/drain region in the second semiconductor fin, wherein the first tilt implantation is tilted from the second semiconductor fin toward the first semiconductor fin. | 03-28-2013 |
20130093026 | SELECTIVE FIN-SHAPING PROCESS USING PLASMA DOPING AND ETCHING FOR 3-DIMENSIONAL TRANSISTOR APPLICATIONS - A semiconductor apparatus includes fin field-effect transistor (FinFETs) having shaped fins and regular fins. Shaped fins have top portions that may be smaller, larger, thinner, or shorter than top portions of regular fins. The bottom portions of shaped fins and regular fins are the same. FinFETs may have only one or more shaped fins, one or more regular fins, or a mixture of shaped fins and regular fins. A semiconductor manufacturing process to shape one fin includes forming a photolithographic opening of one fin, optionally doping a portion of the fin, and etching a portion of the fin. | 04-18-2013 |
20130113026 | FIN FIELD EFFECT TRANSISTOR GATE OXIDE - The present disclosure provides for methods of fabricating a semiconductor device and such a device. A method includes providing a substrate including at least two isolation features, forming a fin substrate above the substrate and between the at least two isolation features, forming a silicon liner over the fin substrate, and oxidizing the silicon liner to form a silicon oxide liner over the fin substrate. | 05-09-2013 |
20130119370 | STRAINED STRUCTURES OF SEMICONDUCTOR DEVICES - A strained structure of a semiconductor device is disclosed. An exemplary structure for a semiconductor device comprises a substrate comprising a major surface; a gate stack on the major surface of the substrate; a shallow trench isolation (STI) disposed on one side of the gate stack, wherein the STI is within the substrate; and a cavity filled with a strained structure distributed between the gate stack and the STI, wherein the cavity comprises one sidewall formed by the STI, one sidewall formed by the substrate, and a bottom surface formed by the substrate, wherein the strained structure comprises a SiGe layer and a first strained film adjoining the sidewall of the STI. | 05-16-2013 |
20130119405 | SEMICONDUCTOR DEVICE WITH ENHANCED STRAIN - The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate. The semiconductor device includes a gate that is disposed over the substrate. The substrate has a recess. The semiconductor device includes a trench liner that is coated along the recess. The trench liner contains a semiconductor crystal material. The trench liner directly abuts the source/drain stressor device. The semiconductor device also includes a dielectric trench component that is disposed on the trench liner and filling the recess. The semiconductor device includes a source/drain stressor device that is disposed in the substrate. The source/drain stressor device is disposed between the gate and the trench liner. | 05-16-2013 |
20130119482 | FIN FIELD EFFECT TRANSISTORS AND METHODS FOR FABRICATING THE SAME - The disclosure relates to a Fin field effect transistor (FinFET). An exemplary structure for a FinFET comprises a substrate comprising a top surface; a first fin and a second fin extending above the substrate top surface, wherein each of the fins has a top surface and sidewalls; an insulation layer between the first and second fins extending part way up the fins from the substrate top surface; a first gate dielectric covering the top surface and sidewalls of the first fin having a first thickness and a second gate dielectric covering the top surface and sidewalls of the second fin having a second thickness less than the first thickness; and a conductive gate strip traversing over both the first gate dielectric and second gate dielectric. | 05-16-2013 |
20130122686 | Reverse Tone STI Formation - A method includes forming a hard mask over a substrate, patterning the hard mask to form a first plurality of trenches, and filling a dielectric material into the first plurality of trenches to form a plurality of dielectric regions. The hard mask is removed from between the plurality of dielectric regions, wherein a second plurality of trenches is left by the removed hard mask. An epitaxy step is performed to grow a semiconductor material in the second plurality of trenches. | 05-16-2013 |
20130132923 | Method for Constant Power Density Scaling - A method for constant power density scaling in MOSFETs is provided. A method for manufacturing an integrated circuit includes computing fixed scaling factors for a first fabrication process based on a second fabrication process, computing settable scaling factors for the integrated circuit to be fabricated using the first fabrication process, determining parameters of the integrated circuit based on the settable scaling factors, and manufacturing the integrated circuit using the determined parameters. The first fabrication process creates devices having a smaller device dimension than the second fabrication process and the settable scaling factors are set based on the fixed scaling factors. | 05-23-2013 |
20130168771 | Method of Forming CMOS FinFET Device - A CMOS FinFET device and method for fabricating a CMOS FinFET device is disclosed. An exemplary CMOS FinFET device includes a substrate including a first region and a second region. The CMOS FinFET further includes a fin structure disposed over the substrate including a first fin in the first region and a second fin in the second region. The CMOS FinFET further includes a first portion of the first fin comprising a material that is the same material as the substrate and a second portion of the first fin comprising a III-V semiconductor material deposited over the first portion of the first fin. The CMOS FinFET further includes a first portion of the second fin comprising a material that is the same material as the substrate and a second portion of the second fin comprising a germanium (Ge) material deposited over the first portion of the second fin. | 07-04-2013 |
20130171792 | Methods for Semiconductor Regrowth - A treatment is performed on a surface of a first semiconductor region, wherein the treatment is performed using process gases including an oxygen-containing gas and an etching gas for etching the semiconductor material. An epitaxy is performed to grow a second semiconductor region on the surface of the first semiconductor region. | 07-04-2013 |
20130210212 | Semiconductor Device Manufacturing Methods - Methods of manufacturing semiconductor devices are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes providing a workpiece, and forming a protective material over a bottom surface and edges of the workpiece. A top surface of the workpiece is processed. The protective material protects the edges and the bottom surface of the workpiece during the processing of the top surface of the workpiece. | 08-15-2013 |
20130221491 | FIN FIELD-EFFECT TRANSISTORS HAVING CONTROLLED FIN HEIGHT AND METHOD OF MAKING - A semiconductor apparatus includes fin field-effect transistor (FinFETs) having controlled fin heights. The apparatus includes a high fin density area and a low fin density area. Each fin density area includes fins and dielectric material between the fins. The dielectric material includes different dopant concentrations for different fin density areas and is the same material as deposited. | 08-29-2013 |
20130224952 | Curved Wafer Processing on Method and Apparatus - An apparatus for and a method of forming a semiconductor structure is provided. The apparatus includes a substrate holder that maintains a substrate such that the processing surface is curved, such as a convex or a concave shape. The substrate is held in place using point contacts, a plurality of continuous contacts extending partially around the substrate, and/or a continuous ring extending completely around the substrate. The processing may include, for example, forming source/drain regions, channel regions, silicides, stress memorization layers, or the like. | 08-29-2013 |
20130234147 | Semiconductor Structures and Methods with High Mobility and High Energy Bandgap Materials - An embodiment is a structure comprising a substrate, a high energy bandgap material, and a high carrier mobility material. The substrate comprises a first isolation region and a second isolation region. Each of first and second isolation regions extends below a first surface of the substrate between the first and second isolation regions. The high energy bandgap material is over the first surface of the substrate and is disposed between the first and second isolation regions. The high carrier mobility material is over the high energy bandgap material. The high carrier mobility material extends higher than respective top surfaces of the first and second isolation regions to form a fin. | 09-12-2013 |
20130234203 | Semiconductor Devices and Methods of Manufacture Thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a channel region in a workpiece, and forming a source or drain region proximate the channel region. The source or drain region includes a contact resistance-lowering material layer comprising SiP, SiAs, or a silicide. The source or drain region also includes a channel-stressing material layer comprising SiCP or SiCAs. | 09-12-2013 |
20130248927 | CONTACT STRUCTURE OF SEMICONDUCTOR DEVICE - A contact structure for a semiconductor device includes a substrate comprising a major surface and a cavity. A bottom surface of the cavity is lower than the major surface. The contact structure also includes a strained material in the cavity, and a lattice constant of the strained material is different from lattice constant of the substrate. The contact structure also includes a first metal layer over the strained material, a dielectric layer over the first metal layer, and a second metal layer over the dielectric layer. The dielectric layer has a thickness ranging from 1 nm to 10 nm. | 09-26-2013 |
20130248929 | Reducing Source/Drain Resistance of III-V Based Transistors - An integrated circuit structure includes a substrate; a channel layer over the substrate, wherein the channel layer is formed of a first III-V compound semiconductor material; a highly doped semiconductor layer over the channel layer; a gate dielectric penetrating through and contacting a sidewall of the highly doped semiconductor layer; and a gate electrode on a bottom portion of the gate dielectric. The gate dielectric includes a sidewall portion on a sidewall of the gate electrode. | 09-26-2013 |
20130248948 | Source/Drain Profile for FinFET - An embodiment is a FinFET device. The FinFET device comprises a fin, a first source/drain region, a second source/drain region, and a channel region. The fin is raised above a substrate. The first source/drain region and the second source/drain region are in the fin. The channel region is laterally between the first and second source/drain regions. The channel region has facets that are not parallel and not perpendicular to a top surface of the substrate. | 09-26-2013 |
20130256812 | METHOD FOR REDUCING INTERFACIAL LAYER THICKNESS FOR HIGH-K AND METAL GATE STACK - A method of performing an ultraviolet (UV) curing process on an interfacial layer over a semiconductor substrate, the method includes supplying a gas flow rate ranging from 10 standard cubic centimeters per minute (sccm) to 5 standard liters per minute (slm), wherein the gas comprises inert gas. The method further includes heating the interfacial layer at a temperature less than or equal to 700° C. Another method of performing an annealing process on an interfacial layer over a semiconductor substrate, the second method includes supplying a gas flow rate ranging from 10 sccm to 5 slm, wherein the gas comprises inert gas. The method further includes heating the interfacial layer at a temperature less than or equal to 600° C. | 10-03-2013 |
20130285153 | STRAINED STRUCTURE OF SEMICONDUCTOR DEVICE AND METHOD OF MAKING THE STRAINED STRUCTURE - An exemplary structure for a field effect transistor (FET) comprises a silicon substrate comprising a first surface; a channel portion over the first surface, wherein the channel portion has a second surface at a first height above the first surface, and a length parallel to first surface; and two source/drain (S/D) regions on the first surface and surrounding the channel portion along the length of the channel portion, wherein the two S/D regions comprise SiGe, Ge, Si, SiC, GeSn, SiGeSn, SiSn, or III-V material. | 10-31-2013 |
20130320452 | Semiconductor Device and Method of Forming the Same - A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a semiconductor substrate including an active region including a plurality of device regions. The semiconductor device further includes a first device disposed in a first device region of the plurality of device regions, the first device including a first gate structure, first gate spacers disposed on sidewalls of the first gate structure, and first source and drain features. The semiconductor device further includes a second device disposed in a second device region of the plurality of device regions, the second device including a second gate structure, second gate spacers disposed on sidewalls of the second gate structure, and second source and drain features. The second and first source and drain features having a source and drain feature and a contact feature in common. The common contact feature being a self-aligned contact. | 12-05-2013 |
20140033981 | MOCVD for Growing III-V Compound Semiconductors on Silicon Substrates - A device includes providing a silicon substrate; annealing the silicon substrate at a first temperature higher than about 900° C.; and lowering a temperature of the silicon substrate from the first temperature to a second temperature. A temperature lowering rate during the step of lowering the temperature is greater than about 1° C./second. A III-V compound semiconductor region is epitaxially grown on a surface of the silicon substrate using metal organic chemical vapor deposition (MOCVD). | 02-06-2014 |
20140042491 | GATE ELECTRODE OF FIELD EFFECT TRANSISTOR - This description relates to a gate electrode of a field effect transistor. An exemplary structure for a field effect transistor includes a substrate; a gate electrode over the substrate including a first top surface and a sidewall; a source/drain (S/D) region at least partially disposed in the substrate on one side of the gate electrode; a spacer on the sidewall distributed between the gate electrode and the S/D region; and a contact etch stop layer (CESL) adjacent to the spacer and further comprising a portion extending over the S/D region, wherein the portion has a second top surface substantially coplanar with the first top surface. | 02-13-2014 |
20140042500 | CONTACT STRUCTURE OF SEMICONDUCTOR DEVICE - The disclosure relates to a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a cavity below the major surface; a strained material in the cavity, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; a Ge-containing dielectric layer over the strained material; and a metal layer over the Ge-containing dielectric layer. | 02-13-2014 |
20140048888 | Strained Structure of a Semiconductor Device - A semiconductor device comprises a substrate comprising a major surface; a p-type Field Effect Transistor (pFET) comprising: a P-gate stack over the major surface, a P-strained region in the substrate adjacent to one side of the P-gate stack, wherein a lattice constant of the P-strained region is different from a lattice constant of the substrate, wherein the P-strained region has a first top surface higher than the major surface; and a P-silicide region on the P-strained region; and an n-type Field Effect Transistor (nFET) comprising: an N-gate stack over the major surface, an N-strained region in the substrate adjacent to one side of the N-gate stack, wherein a lattice constant of the N-strained region is different from a lattice constant of the substrate, wherein the N-strained region has a second top surface lower than the major surface and a N-silicide region on the N-strained region. | 02-20-2014 |
20140070276 | Source/Drain Re-Growth for Manufacturing III-V Based Transistors - A method of forming an integrated circuit structure includes providing a substrate, and epitaxially growing a first semiconductor layer over the substrate. The first semiconductor layer includes a first III-V compound semiconductor material formed of group III and group V elements. The method further includes forming a gate structure on the first semiconductor layer, and forming a gate spacer on at least one sidewall of the gate structure. After the step of forming the gate structure, a second semiconductor layer including a second III-V compound semiconductor material is epitaxially grown on the first semiconductor layer. | 03-13-2014 |
20140080316 | METHODS OF FORMING GATE DIELECTRIC MATERIAL - A method of fabricating a semiconductor device includes contacting water with a silicon oxide layer. The method further includes diffusing an ozone-containing gas through water to treat the silicon oxide layer. The method further includes forming a dielectric layer over the treated silicon oxide layer. | 03-20-2014 |
20140084340 | Contact Structure Of Semiconductor Device - The invention relates to a contact structure of a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a trench below the major surface; a strained material filling the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; an inter-layer dielectric (ILD) layer having an opening over the strained material, wherein the opening comprises dielectric sidewalls and a strained material bottom; a dielectric layer coating the sidewalls and bottom of the opening, wherein the dielectric layer has a thickness ranging from 1 nm to 10 nm; and a metal layer filling a coated opening of the dielectric layer. | 03-27-2014 |
20140084351 | REPLACEMENT CHANNELS FOR SEMICONDUCTOR DEVICES AND METHODS FOR FORMING THE SAME USING DOPANT CONCENTRATION BOOST - A replacement channel and a method for forming the same in a semiconductor device are provided. A channel area is defined in a substrate which is a surface of a semiconductor wafer or a structure such as a fin formed over the wafer. Portions of the channel region are removed and are replaced with a replacement channel material formed by an epitaxial growth/deposition process to include a first dopant concentration level less than a first dopant concentration level. A subsequent doping operation or operations is then used to boost the average dopant concentration to a level greater than the first dopant concentration level. The replacement channel material is formed to include a gradient in which the upper portion of the replacement channel material has a greater dopant concentration than the lower portion of replacement channel material. | 03-27-2014 |
20140099771 | Reverse Tone STI Formation - A method includes forming a hard mask over a substrate, patterning the hard mask to form a first plurality of trenches, and filling a dielectric material into the first plurality of trenches to form a plurality of dielectric regions. The hard mask is removed from between the plurality of dielectric regions, wherein a second plurality of trenches is left by the removed hard mask. An epitaxy step is performed to grow a semiconductor material in the second plurality of trenches. | 04-10-2014 |
20140099779 | Reverse Tone STI Formation - A method includes forming a hard mask over a substrate, patterning the hard mask to form a first plurality of trenches, and filling a dielectric material into the first plurality of trenches to form a plurality of dielectric regions. The hard mask is removed from between the plurality of dielectric regions, wherein a second plurality of trenches is left by the removed hard mask. An epitaxy step is performed to grow a semiconductor material in the second plurality of trenches. | 04-10-2014 |
20140134815 | High-Mobility Multiple-Gate Transistor with Improved On-to-Off Current Ratio - A multi-gate transistor includes a semiconductor fin over a substrate. The semiconductor fin includes a central fin formed of a first semiconductor material; and a semiconductor layer having a first portion and a second portion on opposite sidewalls of the central fin. The semiconductor layer includes a second semiconductor material different from the first semiconductor material. The multi-gate transistor further includes a gate electrode wrapping around sidewalls of the semiconductor fin; and a source region and a drain region on opposite ends of the semiconductor fin. Each of the central fin and the semiconductor layer extends from the source region to the drain region. | 05-15-2014 |
20140138742 | Device Having Source/Drain Regions Regrown from Un-Relaxed Silicon Layer - A device including a silicon substrate, a silicon germanium layer, a silicon layer, a gate stack, and silicon-containing stressors is provided. In an embodiment, the silicon germanium layer is disposed over a silicon substrate and relaxed while the silicon layer is disposed over the silicon germanium layer and un-relaxed. The silicon layer may be free from germanium. The gate stack is of an n-type metal-oxide-semiconductor (NMOS) field-effect transistor (FET) and disposed over the silicon layer and the silicon germanium layer. A portion of the silicon layer forms a channel region of the NMOS FET. The silicon-containing stressors are formed in recesses in the silicon layer and have a lattice constant smaller than a lattice constant of the silicon germanium layer. | 05-22-2014 |
20140145242 | Fin-Last FinFET and Methods of Forming Same - Embodiments of the present disclosure are a FinFET device, and methods of forming a FinFET device. An embodiment is a method for forming a FinFET device, the method comprising forming a semiconductor strip over a semiconductor substrate, wherein the semiconductor strip is disposed in a dielectric layer, forming a gate over the semiconductor strip and the dielectric layer, and forming a first recess and a second recess in the semiconductor strip, wherein the first recess is on an opposite side of the gate from the second recess. The method further comprises forming a source region in the first recess and a drain region in the second recess, and recessing the dielectric layer, wherein a first portion of the semiconductor strip extends above a top surface of the dielectric layer forming a semiconductor fin. | 05-29-2014 |
20140147943 | Method for Determining Carrier Concentrations in Semiconductor Fins - A method includes probing at least one semiconductor fin using a four-point probe head, with four probe pins of the four-point probe head contacting the at least one semiconductor fin. A resistance of the at least one semiconductor fin is calculated. A carrier concentration of the semiconductor fin is calculated from the resistance. | 05-29-2014 |
20140147978 | Strained Structure of a Semiconductor Device - A semiconductor device comprises a substrate comprising a major surface; a p-type Field Effect Transistor (pFET) comprising: a P-gate stack over the major surface, a P-strained region in the substrate adjacent to one side of the P-gate stack, wherein a lattice constant of the P-strained region is different from a lattice constant of the substrate, wherein the P-strained region has a first top surface higher than the major surface; and a P-silicide region on the P-strained region; and an n-type Field Effect Transistor (nFET) comprising: an N-gate stack over the major surface, an N-strained region in the substrate adjacent to one side of the N-gate stack, wherein a lattice constant of the N-strained region is different from a lattice constant of the substrate, wherein the N-strained region has a second top surface lower than the major surface and a N-silicide region on the N-strained region. | 05-29-2014 |
20140151819 | Semiconductor Device Having SiGe Substrate, Interfacial Layer and High K Dielectric Layer - The invention relates to integrated circuit fabrication, and more particularly to a semiconductor device with an interfacial layer. An exemplary structure for a semiconductor device comprises a Si | 06-05-2014 |
20140162446 | METHOD FOR REMOVING HARD MASK OXIDE AND MAKING GATE STRUCTURE OF SEMICONDUCTOR DEVICES - A method includes forming a first gate above a semiconductor substrate, forming a hard mask on the first gate, and forming a contact etch stop layer (CESL) on the hard mask. No hard mask is removed between the step of forming the hard mask and the step of forming the CESL. The method further includes forming an interlayer dielectric (ILD) layer over the CESL, and performing one or more CMP processes to planarize the ILD layer, remove the CESL on the hard mask, and remove at least one portion of the hard mask. | 06-12-2014 |
20140183600 | NOVEL FIN STRUCTURE OF FINFET - A fin structure disposed over a substrate and a method of forming a fin structure are disclosed. The fin structure includes a mesa, a channel disposed over the mesa, and a convex-shaped feature disposed between the channel and the mesa. The mesa has a first semiconductor material, and the channel has a second semiconductor material different from the first semiconductor material. The convex-shaped feature is stepped-shaped, stair-shaped, or ladder-shaped. The convex-shaped feature includes a first isolation feature disposed between the channel and the mesa, and a second isolation feature disposed between the channel and the first isolation feature. The first isolation feature is U-shaped, and the second isolation feature is rectangular-shaped. A portion of the second isolation feature is surrounded by the channel and another portion of the second isolation feature is surrounded by the first isolation feature. | 07-03-2014 |
20140183645 | Complimentary Metal-Oxide-Semiconductor (CMOS) With Low Contact Resistivity and Method of Forming Same - An embodiment complimentary metal-oxide-semiconductor (CMOS) device and an embodiment method of forming the same are provided. The embodiment CMOS device includes an n-type metal-oxide-semiconductor (NMOS) having a titanium-containing layer interposed between a first metal contact and an NMOS source and a second metal contact and an NMOS drain and a p-type metal-oxide-semiconductor (PMOS) having a PMOS source and a PMOS drain, the PMOS source having a first titanium-containing region facing a third metal contact, the PMOS drain including a second titanium-containing region facing a fourth metal contact. | 07-03-2014 |
20140191333 | METHOD OF PROTECTING AN INTERLAYER DIELECTRIC LAYER AND STRUCTURE FORMED THEREBY - This description relates to a method including forming an interlayer dielectric (ILD) layer and a dummy gate structure over a substrate and forming a cavity in a top portion of the ILD layer. The method further includes forming a protective layer to fill the cavity. The method further includes planarizing the protective layer. A top surface of the planarized protective layer is level with a top surface of the dummy gate structure. This description also relates to a semiconductor device including first and second gate structures and an ILD layer formed on a substrate. The semiconductor device further includes a protective layer formed on the ILD layer, the protective layer having a different etch selectivity than the ILD layer, where a top surface of the protective layer is level with the top surfaces of the first and second gate structures. | 07-10-2014 |
20140197499 | Self Aligned Contact Formation - The present disclosure relates to methods of forming a self-aligned contact and related apparatus. In some embodiments, the method forms a plurality of gate lines interspersed between a plurality of dielectric lines, wherein the gate lines and the dielectric lines extend in a first direction over an active area. One or more of the plurality of gate lines are into a plurality of gate line sections aligned in the first direction. One or more of the plurality of dielectric lines are cut into a plurality of dielectric lines sections aligned in the first direction. A dummy isolation material is deposited between adjacent dielectric sections in the first direction and between adjacent gate line sections in the first direction. One or more self-aligned metal contacts are then formed by replacing a part of one or more of the plurality of dielectric lines over the active area with a contact metal. | 07-17-2014 |
20140203333 | SEMICONDUCTOR DEVICE HAVING MODIFIED PROFILE METAL GATE - In one embodiment, a method includes providing a semiconductor substrate having a trench disposed thereon and forming a plurality of layers in the trench. The plurality of layers formed in the trench is etched thereby providing at least one etched layer having a top surface that lies below a top surface of the trench. In a further embodiment, this may provide for a substantially v-shaped opening or entry to the trench for the formation of further layers. Further, a device having a modified profile metal gate for example having at least one layer of the metal. | 07-24-2014 |
20140206167 | CONTACT STRUCTURE OF SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device comprises epitaxially-growing a strained material in a cavity of a substrate comprising a major surface and the cavity, the cavity being below the major surface. A lattice constant of the strained material is different from a lattice constant of the substrate. The method also comprises forming a first metal layer over the strained material, and forming a dielectric layer over the first metal layer, wherein the dielectric layer has a thickness ranging from 1 nm to 10 nm. The method further comprises forming a dummy poly-silicon over the dielectric layer, and forming an interlayered dielectric layer (ILD) surrounding the dummy poly-silicon. The method additionally comprises removing the dummy poly-silicon over the dielectric layer, and forming a second metal layer over the dielectric layer. | 07-24-2014 |
20140213048 | Method of Making a FinFET Device - A FinFET device is fabricated by first receiving a FinFET precursor. The FinFET precursor includes a substrate, fins on the substrate, isolation regions on sides of the fins and dummy gate stacks on the substrate including wrapping a portion of the fin, which is referred to as a gate channel region. The dummy gate stacks is removed to form a gate trench and a gate dielectric layer is deposited in the gate trench. A metal stressor layer (MSL) is conformably deposited on the gate dielectric layer. A capping layer is deposited on the MSL. A thermal treatment is applied to the MSL to achieve a volume expansion. Then the capping layer is removed and a metal gate (MG) is formed on the MSL. | 07-31-2014 |
20140215420 | SYSTEM AND METHODS FOR CONVERTING PLANAR DESIGN TO FINFET DESIGN - A method and layout generating machine for generating a layout for a device having FinFETs from a first layout for a device having planar transistors are disclosed. A planar layout with a plurality of FinFET active areas is received and corresponding FinFET active areas are generated with active area widths. Mandrels are generated according to the active area widths and adjusted such that a beta ratio of a beta number for each FinFET active area to a beta number for each corresponding planar active area is within a predetermined beta ratio range. | 07-31-2014 |
20140217499 | Methods for Forming Semiconductor Regions in Trenches - A structure includes a semiconductor substrate including a first semiconductor material. A portion of the semiconductor substrate extends between insulation regions in the semiconductor substrate. The portion of the semiconductor substrate has a (111) surface and a bottom surface. The (111) surface is slanted and has a top edge and a bottom edge. The bottom surface is parallel to a top surface of the insulation regions, and is connected to the bottom edge. A semiconductor region overlaps the portion of the semiconductor substrate, wherein the semiconductor region includes a second semiconductor material different from the first semiconductor material. The top edge and the bottom edge of the (111) surface are at a first depth and a second depth, respectively, relative to a top surface of the semiconductor region. A ratio of the first depth to the second depth is smaller than about 0.6. | 08-07-2014 |
20140220751 | Methods for Forming Semiconductor Regions in Trenches - A method includes recessing a portion of a semiconductor substrate between opposite isolation regions to form a recess. After the step of recessing, the portion of the semiconductor substrate includes a top surface. The top surface includes a flat surface, and a slant surface having a (111) surface plane. The slant surface has a bottom edge connected to the flat surface, and a top edge connected to one of the isolation regions. The method further includes performing an epitaxy to grow a semiconductor material in the recess, wherein the semiconductor material is grown from the flat surface and the slant surface, and performing an annealing on the semiconductor material. | 08-07-2014 |
20140235040 | Growing III-V Compound Semiconductors from Trenches Filled with Intermediate Layers - A method of forming an integrated circuit structure includes forming an insulation layer over at least a portion of a substrate; forming a plurality of semiconductor pillars over a top surface of the insulation layer. The plurality of semiconductor pillars is horizontally spaced apart by portions of the insulation layer. The plurality of semiconductor pillars is allocated in a periodic pattern. The method further includes epitaxially growing a III-V compound semiconductor film from top surfaces and sidewalls of the semiconductor pillars. | 08-21-2014 |
20140235051 | Structure and Method for High Performance Interconnect - The present disclosure provides an integrated circuit structure. The integrated circuit structure includes a substrate having an IC device formed therein; a first dielectric material layer disposed on the substrate and having a first trench formed therein; and a first composite interconnect feature disposed in the first trench and electrically coupled with the IC device. The first composite interconnect feature includes a first barrier layer disposed on sidewalls of the first trench; a first metal layer disposed on the first barrier layer; and a first graphene layer disposed on the metal layer. | 08-21-2014 |
20140239354 | FinFETs and Methods for Forming the Same - A finFET and methods for forming a finFET are disclosed. A structure comprises a substrate, a fin, a gate dielectric, and a gate electrode. The substrate comprises the fin. The fin has a major surface portion of a sidewall, and the major surface portion comprises at least one lattice shift. The at least one lattice shift comprises an inward or outward shift relative to a center of the fin. The gate dielectric is on the major surface portion of the sidewall. The gate electrode is on the gate dielectric. | 08-28-2014 |
20140239402 | FinFETs with Strained Well Regions - A device includes a substrate and insulation regions over a portion of the substrate. A first semiconductor region is between the insulation regions and having a first conduction band. A second semiconductor region is over and adjoining the first semiconductor region, wherein the second semiconductor region includes an upper portion higher than top surfaces of the insulation regions to form a semiconductor fin. The semiconductor fin has a tensile strain and has a second conduction band lower than the first conduction band. A third semiconductor region is over and adjoining a top surface and sidewalls of the semiconductor fin, wherein the third semiconductor region has a third conduction band higher than the second conduction band. | 08-28-2014 |
20140246695 | ISOLATION STRUCTURE OF SEMICONDUCTOR DEVICE - The invention relates to an isolation structure of a semiconductor device. An exemplary isolation structure for a semiconductor device comprises a substrate comprising a trench; a strained material in the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; an oxide layer of the strained material over the strained material; a high-k dielectric layer over the oxide layer; and a dielectric layer over the high-k dielectric layer filling the trench. | 09-04-2014 |
20140252469 | FinFETs with Strained Well Regions - A device includes a substrate and insulation regions over a portion of the substrate. A first semiconductor region is between the insulation regions and having a first conduction band. A second semiconductor region is over and adjoining the first semiconductor region, wherein the second semiconductor region includes an upper portion higher than top surfaces of the insulation regions to form a semiconductor fin. The second semiconductor region also includes a wide portion and a narrow portion over the wide portion, wherein the narrow portion is narrower than the wide portion. The semiconductor fin has a tensile strain and has a second conduction band lower than the first conduction band. A third semiconductor region is over and adjoining a top surface and sidewalls of the semiconductor fin, wherein the third semiconductor region has a third conduction band higher than the second conduction band. | 09-11-2014 |
20140252488 | Channel Epitaxial Regrowth Flow (CRF) - A Fin-FET fabrication approach and structure are provided using channel epitaxial regrowth flow (CRF). The method includes forming a Fin-FET structure including a Si line on a substrate, shallow trench isolation (STI) oxide on both sides of the Si line on the substrate, and a poly wall on top of and across the STI oxide and the Si line, wherein the Si line is higher than the STI oxide from the substrate. The method further includes thinning the STI oxide and the Si line while maintaining about the same height ratio of the Si line and the STI oxide, and forming a spacer wall adjacent to both sides of the poly wall and further adjacent to Si and STI oxide side walls under the poly wall uncovered due thinning the STI oxide and the Si line. | 09-11-2014 |
20140256105 | Self-Aligned Passivation of Active Regions - A method includes forming a semiconductor fin, performing a first passivation step on a top surface of the semiconductor fin using a first passivation species, and performing a second passivation step on sidewalls of the semiconductor fin using a second passivation species different from the first passivation species. A gate stack is formed on a middle portion of the semiconductor fin. A source or a drain region is formed on a side of the gate stack, wherein the source or drain region and the gate stack form a Fin Field-Effect Transistor (FinFET). | 09-11-2014 |
20140256124 | IN-SITU METAL GATE RECESS PROCESS FOR SELF-ALIGNED CONTACT APPLICATION - A method of producing a metal gate structure. The method includes forming a gate structure above a semiconductor substrate and performing one or more chemical metal planarization (CMP) processes to planarize the formed gate structure using a CMP tool. An in situ gate etching process is performed in a CMP cleaner of the CMP tool to form a gate recess. A contact etch stop layer (CESL) can then be deposited in the formed gate recess and one or more CMP processes performed to planarize the CESL. | 09-11-2014 |
20140315360 | Method of Scavenging Impurities in Forming a Gate Stack Having an Interfacial Layer - A multi-layer scavenging metal gate stack, and methods of manufacturing the same, are disclosed. In an example, a gate stack disposed over a semiconductor substrate includes an interfacial dielectric layer disposed over the semiconductor substrate, a high-k dielectric layer disposed over the interfacial dielectric layer, a first conductive layer disposed over the high-k dielectric layer, and a second conductive layer disposed over the first conductive layer. The first conductive layer includes a first metal layer disposed over the high-k dielectric layer, a second metal layer disposed over the first metal layer, and a third metal layer disposed over the second metal layer. The first metal layer includes a material that scavenges oxygen impurities from the interfacial dielectric layer, and the second metal layer includes a material that adsorbs oxygen impurities from the third metal layer and prevents oxygen impurities from diffusing into the first metal layer. | 10-23-2014 |
20140327046 | Fin-Last FinFET and Methods of Forming Same - Embodiments of the present disclosure are a FinFET device, and methods of forming a FinFET device. An embodiment is a method for forming a FinFET device, the method comprising forming a semiconductor strip over a semiconductor substrate, wherein the semiconductor strip is disposed in a dielectric layer, forming a gate over the semiconductor strip and the dielectric layer, and forming a first recess and a second recess in the semiconductor strip, wherein the first recess is on an opposite side of the gate from the second recess. The method further comprises forming a source region in the first recess and a drain region in the second recess, and recessing the dielectric layer, wherein a first portion of the semiconductor strip extends above a top surface of the dielectric layer forming a semiconductor fin. | 11-06-2014 |
20140332904 | SYSTEM AND METHODS FOR CONVERTING PLANAR DESIGN TO FINFET DESIGN - A FinFET structure layout includes a semiconductor substrate comprising a plurality of FinFET active areas, and a plurality of fins within each FinFET active area of the plurality of FinFET active areas. The FinFET structure layout further includes a gate having a gate length parallel to the semiconductor substrate and perpendicular to length of the plurality of fins within each FinFET active area of the plurality of FinFET active areas. The FinFET structure layout further includes a plurality of metal features connecting a source region or a drain region of a portion of the plurality of FinFET active areas to a plurality of contacts. The plurality of metal features includes a plurality of metal lines parallel to a FinFET channel direction and a plurality of metal lines parallel to a FinFET channel width direction. | 11-13-2014 |
20140357049 | Semiconductor Structures and Methods with High Mobility and High Energy Bandgap Materials - An embodiment is a structure comprising a substrate, a high energy bandgap material, and a high carrier mobility material. The substrate comprises a first isolation region and a second isolation region. Each of first and second isolation regions extends below a first surface of the substrate between the first and second isolation regions. The high energy bandgap material is over the first surface of the substrate and is disposed between the first and second isolation regions. The high carrier mobility material is over the high energy bandgap material. The high carrier mobility material extends higher than respective top surfaces of the first and second isolation regions to form a fin. | 12-04-2014 |
20140363943 | Contact Structure of Semiconductor Device Priority Claim - The invention relates to a contact structure of a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a trench below the major surface; a strained material filling the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; an inter-layer dielectric (ILD) layer having an opening over the strained material, wherein the opening comprises dielectric sidewalls and a strained material bottom; a semiconductor layer on the sidewalls and bottom of the opening; a dielectric layer on the semiconductor layer; and a metal layer filling an opening of the dielectric layer. | 12-11-2014 |
20140374838 | FinFETs with Nitride Liners and Methods of Forming the Same - An integrated circuit structure includes a semiconductor substrate, which includes a semiconductor strip. A Shallow Trench Isolation (STI) region is on a side of the semiconductor strip. The STI region includes a first portion comprising an oxide and a second portion free from oxide. The second portion separates the first portion from the semiconductor substrate. A semiconductor fin is over and aligned to the semiconductor strip, wherein the semiconductor fin is higher than a top surface of the STI region. | 12-25-2014 |
20150017768 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a semiconductor substrate including an active region including a plurality of device regions. The semiconductor device further includes a first device disposed in a first device region of the plurality of device regions, the first device including a first gate structure, first gate spacers disposed on sidewalls of the first gate structure, and first source and drain features. The semiconductor device further includes a second device disposed in a second device region of the plurality of device regions, the second device including a second gate structure, second gate spacers disposed on sidewalls of the second gate structure, and second source and drain features. The second and first source and drain features having a source and drain feature and a contact feature in common. The common contact feature being a self-aligned contact. | 01-15-2015 |
20150035017 | Contact Structure of Semiconductor Device - The disclosure relates to a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface; a fin structure extending upward from the substrate major surface, wherein the fin structure comprises a first fin, a second fin, and a third fin between the first fin and second fin; a first germanide over the first fin, wherein a first bottom surface of the first germanide has a first acute angle to the major surface; a second germanide over the second fin on a side of the third fin opposite to first germanide substantially mirror-symmetrical to each other; and a third germanide over the third fin, wherein a third bottom surface of the third germanide has a third acute angle to the major surface less than the first acute angle. | 02-05-2015 |
20150041918 | Self-Aligned Dual-Metal Silicide and Germanide Formation - A method includes growing an epitaxy semiconductor region at a major surface of a wafer. The epitaxy semiconductor region has an upward facing facet facing upwardly and a downward facing facet facing downwardly. The method further includes forming a first metal silicide layer contacting the upward facing facet, and forming a second metal silicide layer contacting the downward facing facet. The first metal silicide layer and the second metal silicide layer comprise different metals. | 02-12-2015 |
20150060959 | Eliminating Fin Mismatch Using Isolation Last - An embodiment fin field-effect transistor (FinFET) includes an inner fin, and outer fin spaced apart from the inner fin by a shallow trench isolation (STI) region, an isolation fin spaced apart from the outer fin by the STI region, the isolation fin including a body portion, an isolation oxide, and an etch stop layer, the etch stop layer interposed between the body portion and the isolation oxide and between the STI region and the isolation oxide, and a gate formed over the inner fin, the outer fin, and the isolation fin. | 03-05-2015 |
20150062561 | Stress Analysis of 3-D Structures Using Tip-Enhanced Raman Scattering Technology - A method includes performing a first probing on a sample integrated circuit structure to generate a first Raman spectrum. During the first probing, a first laser beam having a first wavelength is projected on the sample integrated circuit structure. The method further includes performing a second probing on the sample integrated circuit structure to generate a second Raman spectrum, wherein a Tip-Enhanced Raman Scattering (TERS) method is used to probe the sample integrated circuit structure. During the second probing, a second laser beam having a second wavelength different from the first wavelength is projected on the sample integrated circuit structure. A stress in a first probed region of the sample integrated circuit structure is then from the first Raman spectrum and the second Raman spectrum. | 03-05-2015 |
20150072495 | High-Mobility Multiple-Gate Transistor with Improved On-to-Off Current Ratio - A multi-gate transistor includes a semiconductor fin over a substrate. The semiconductor fin includes a central fin formed of a first semiconductor material; and a semiconductor layer having a first portion and a second portion on opposite sidewalls of the central fin. The semiconductor layer includes a second semiconductor material different from the first semiconductor material. The multi-gate transistor further includes a gate electrode wrapping around sidewalls of the semiconductor fin; and a source region and a drain region on opposite ends of the semiconductor fin. Each of the central fin and the semiconductor layer extends from the source region to the drain region. | 03-12-2015 |
20150076499 | System and Method for Test Key Characterizing Wafer Processing State - Disclosed herein is a method for forming a test key system for characterizing wafer processing states, the method comprising forming a plurality of shallow trench isolation structures (STIs) on a substrate of a wafer and in a scribe line of the wafer and forming a test key on the substrate of a wafer and in the scribe line of the wafer. Forming the test key comprises forming at least one test key group having a plurality of test key series, each of the plurality of test key series having a plurality of test pads, each one of the plurality of test key series having a first physical characteristic different from the first physical characteristic of other test key series the at least one first test key group. | 03-19-2015 |
20150076558 | SEMICONDUCTOR STRUCTURE AND THE MANUFACTURING METHOD THEREOF - The present disclosure provides a FinFET. The FinFET includes a silicon-on-insulator (SOI) with an insulator; a plurality of fin structures on the insulator; an isolation on the insulator, and between two adjacent fin structures in the plurality of fin structures; and an oxide layer between each of the plurality of fin structures and the insulator, wherein the insulator comprises silicon germanium oxide. A method for manufacturing the FinFET includes forming a plurality of fin structures on a layer having a larger lattice constant than that of the fin structure by a patterning operation; oxidizing the fin structure and the layer to transform the layer into a first oxide layer; filling insulating material between adjacent fin structures; and etching the insulating material to expose a top surface and at least a portion of a sidewall of the fin structure. | 03-19-2015 |