Clauter
Peter Clauter, Pfungstadt DE
Patent application number | Description | Published |
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20130288024 | PROCESS FOR CREATING THREE-DIMENSIONAL PATTERNS IN COATINGS - The present invention relates to a process for the production of three-dimensional patterns in coatings which comprise flake-form effect pigments, to patterened coatings produced thereby and to the use thereof in decoration and security products. | 10-31-2013 |
Steve Clauter, Tempe, AZ US
Patent application number | Description | Published |
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20080290882 | PROBE NEEDLE PROTECTION METHOD FOR HIGH CURRENT PROBE TESTING OF POWER DEVICES - A test system, apparatus and method for applying high current test stimuli to a semiconductor device in wafer or chip form includes a plurality of probes for electrically coupling to respective contact points on the semiconductor device, a plurality of current limiters electrically coupled to respective ones of the plurality of probes, and a current sensor electrically coupled to the plurality of probes. The current limiters are operative to limit current flow passing through a respective probe, and the current sensor is operative to provide a signal when detected current in any contact of the plurality of probes exceeds a threshold level. | 11-27-2008 |
20110309847 | High Current Kelvin Connections and Contact Resistance Verification Method - A method and circuit is provided for implementing high current capability Kelvin connections and measuring the resistance of the contacts and connections to verify that the conducting path is capable of carrying the high current without damage or degraded performance. Included as well is the means and circuit for efficiently dividing a high current test stimulus current into 2 or more paths with low losses and voltage drops. | 12-22-2011 |
20130027067 | DAMAGE REDUCTION METHOD AND APPARATUS FOR DESTRUCTIVE TESTING OF POWER SEMICONDUCTORS - A device and method for limiting damage to a semiconductor device under test when the semiconductor device fails during a high current, or high power test is provided. The occurrence of a failure of the device under test is detected, and power applied to the semiconductor device is diverted through a parallel path element upon detection of failure of the semiconductor device. | 01-31-2013 |
Steven Clauter, Goodyear, AZ US
Patent application number | Description | Published |
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20140354319 | HIGH CURRENT KELVIN CONNECTION AND VERIFICATION METHOD - A method and circuit for implementing high current capability Kelvin connections and measuring the resistance of the contacts and connections to verify that the conducting path is capable of carrying the high current without damage or degraded performance. Included as well is the means and circuit for efficiently dividing a high current test stimulus current into 2 paths with low losses and voltage drops. | 12-04-2014 |