Patent application number | Description | Published |
20090080242 | Programming a multilevel phase change memory cell - Multilevel phase change memory cells may be programmed forming amorphous regions of amorphous phase change material in a storage region of the phase change memory cell. Crystalline paths of crystalline phase change material are formed through the amorphous regions of amorphous phase change material. Lengths of the crystalline paths are controlled so that at least a first crystalline path has a first length in a first programming state and a second crystalline path has a second length, different from the first length, in a second programming state. | 03-26-2009 |
20090080267 | Generating reference currents compensated for process variation in non-volatile memories - In a current reference generator device, a voltage reference generator stage generates a reference voltage (V | 03-26-2009 |
20090091988 | Writing bit alterable memories - A bit alterable memory may include current generators in a periphery outside the main memory core. Current may be generated in the periphery and driven into the core. As a result, the capacitance of the memory cells has a lowered effect. The current may be generated using the chip supply voltage and then mirrored using a pump voltage. In some embodiments, the mirroring may be ratioed at the partition level and multiplied at the plane level. A delay may be provided before applying the currents to the cell to accommodate for transients. | 04-09-2009 |
20090116281 | Reading Phase Change Memories - A read current high enough to threshold a phase change memory element may be used to read the element without thresholding the memory element. The higher current may improve performance in some cases. The memory element does not threshold because the element is read and the current stopped prior to triggering the memory element. | 05-07-2009 |
20100128517 | PHASE-CHANGE MEMORY DEVICE WITH DISCHARGE OF LEAKAGE CURRENTS IN DESELECTED BITLINES AND METHOD FOR DISCHARGING LEAKAGE CURRENTS IN DESELECTED BITLINES OF A PHASE-CHANGE MEMORY DEVICE - A phase change memory device includes a bitline biasing unit; and a bitline selection unit connecting a selected bitline to the bitline biasing unit and disconnecting deselected bitlines from the bitline biasing unit in an operative condition. A bitline discharge unit is connected to the bitlines to discharge leakage currents in the bitlines. The bitline discharge unit has a voltage regulation unit and a plurality of bitline discharge switches coupled between the voltage regulation unit and a respective bitline. The bitline discharge switches are controlled to connect the deselected bitlines to the voltage regulation unit and to disconnect the selected bitline from the voltage regulation unit. The voltage regulation unit comprises a PMOS transistor coupled between a regulated voltage bus and a reference potential line. The regulated voltage bus is connected to the bitline discharge switches and the control terminal of the PMOS transistor is biased to a constant voltage. | 05-27-2010 |
20100141335 | CURRENT MIRROR CIRCUIT, IN PARTICULAR FOR A NON-VOLATILE MEMORY DEVICE - A current mirror circuit is provided with a first current mirror including a first and a second mirror transistors sharing a common control terminal; the first mirror transistor has a conduction terminal for receiving, during a first operating condition, a first reference current, and the second mirror transistor has a respective conduction terminal for providing, during the first operating condition, a mirrored current based on the first reference current. The current mirror circuit is provided with a switching stage operable to connect the control terminal to the conduction terminal of the first mirror transistor during the first operating condition, and to disconnect the control terminal from the same conduction terminal of the first mirror transistor, and either letting it substantially floating or connecting it to a reference voltage, during a second operating condition, in particular a condition of stand-by. | 06-10-2010 |
20100165712 | METHOD FOR LOW-STRESS MULTILEVEL READING OF PHASE CHANGE MEMORY CELLS AND MULTILEVEL PHASE CHANGE MEMORY - According to a method for multilevel reading of a phase change memory cell a bit line ( | 07-01-2010 |
20100165713 | METHOD FOR LOW POWER ACCESSING A PHASE CHANGE MEMORY DEVICE - A method for accessing a phase change memory device, wherein a first sub-plurality of bitlines is grouped in a first group and a second sub-plurality of bitlines is grouped in a second group. At least a bitline in the first and second groups are selected; currents are supplied to the selected bitlines; and a selected wordline is biased. The bitlines are selected by selecting a first bitline in the first group and, while the first bitline is selected, selecting a second bitline in the second group which is arranged on the selected wordline symmetrically to the first bitline in the first group. | 07-01-2010 |
20100284212 | METHOD FOR MULTILEVEL PROGRAMMING OF PHASE CHANGE CELLS USING ADAPTIVE RESET PULSES - A method for programming multilevel PCM cells envisages: forming an amorphous region of amorphous phase change material in a storage element of a PCM cell by applying one or more reset pulse; and forming a conductive path of crystalline phase change material through the amorphous region by applying one or more set pulse, a size of the conductive path defining a programmed state of the PCM cell and an output electrical quantity associated thereto, and being controlled by the value of the reset pulse and set pulse. The step of forming an amorphous region envisages adaptively and iteratively determining, during the programming operations, a value of the reset pulse optimized for electrical and/or physical properties of the PCM cell, and in particular determining a minimum amplitude value of the reset pulse, which allows programming a desired programmed state and a desired value of the output electrical quantity. | 11-11-2010 |
20110176358 | Reading Phase Change Memories - A read current high enough to threshold a phase change memory element may be used to read the element without thresholding the memory element. The higher current may improve performance in some cases. The memory element does not threshold because the element is read and the current stopped prior to triggering the memory element. | 07-21-2011 |
20120113711 | Using A Bit Specific Reference Level To Read A Memory - A voltage derived from accessing a selected bit using one read current may be utilized to read a selected bit of an untriggered phase change memory after the read current is changed. As a result, different reference voltages may be used to sense the state of more resistive versus a less resistive selected cells. The resulting read window or margin may be improved in some embodiments, | 05-10-2012 |
20120287698 | Using a Bit Specific Reference Level to Read a Memory - A voltage derived from accessing a selected bit using one read current may be utilized to read a selected bit of an untriggered phase change memory after the read current is changed. As a result, different reference voltages may be used to sense the state of more resistive versus a less resistive selected cells. The resulting read. window or margin may be improved in some embodiments. | 11-15-2012 |
20140376306 | METHODS FOR A PHASE-CHANGE MEMORY ARRAY - Methods of operating phase-change memory arrays are described. A method includes determining a pattern to be written to a phase-change memory array and executing, according to the pattern, two or more proper reset sequences on the phase-change memory array to write the pattern to the phase-change memory array. Another method includes executing a set sequence on a phase-change memory array and performing a proper read of the phase-change memory array to obtain a pattern derived from executing the set sequence. | 12-25-2014 |