Ciacci
Massimo Ciacci, Eindhoven NL
Patent application number | Description | Published |
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20080232213 | Feedback Control Loop for Bit Detection in an N-Dimensional Data Block - On existing DVD and CD players a control loop is required for the adaptation and timing recovery. For Two-Dimensional Optical Storage such a control loop has drawbacks because PRML detection in the form of a stripe-wise Viterbi detector is used. Such a detector introduces an increasing detection delay when going from the outer rows towards the center of the broad spiral. A feedback loop is arranged to determining an error signal from a first area of the data block where the first area is that area where the error signal can be determined within the shortest period of time. This reduces the duration of the detection step and thus increases the stability of the control loop. | 09-25-2008 |
20140192934 | RECEIVER FILTER FOR DC-WANDER REMOVAL IN A CONTACTLESS SMARTCARD - Embodiments of a method for processing a baseband signal in a Direct Current (DC)-suppressed system, a system for processing a baseband signal in a DC-suppressed system, and a smart card are described. In one embodiment, a method for processing a baseband signal in a DC-suppressed system involves processing the baseband signal in the analog domain with a first high pass filter (HPF), converting the processed baseband signal to a digital signal, and processing the digital signal in the digital domain with a second HPF to provide a discrete-time differentiation of the baseband signal. Other embodiments are also described. | 07-10-2014 |
Massimo Ciacci, 'S-Hertogenbosch NL
Patent application number | Description | Published |
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20120080529 | SMART CARD - The invention proposes a smart card which comprises a digital signal processing receiver that can automatically identify the type of a smart card reader based on the error vector magnitude of signals received from the reader. The digital signal processing receiver is able to reconfigure itself at runtime in order to optimally minimize its power consumption in dependence on the type of reader it is communicating with. Furthermore, the invention proposes a new preamble structure that comprises a basic part and an optional additional part. | 04-05-2012 |
20120269304 | Symbol Clock Recovery Circuit - A symbol clock recovery circuit is provided for a data communication system using coherent demodulation. The symbol clock recovery circuit comprises an analog-to-digital converter comprising a first input for receiving a coherent-detected baseband analog signal derived from a carrier signal, a second input for receiving an adapted symbol clock signal, and an output for outputting a digital signal comprising a frame having a preamble with at least two symbols. The symbol clock recovery circuit comprises further a phase shifting unit comprising a first input for receiving a symbol clock signal derived from the carrier signal, and a timing detector, comprising a first input for receiving the digital signal from the analog-to-digital converter and an output for providing a signal comprising information about an optimum sample phase to the phase shifting unit. | 10-25-2012 |
Massimo Ciacci, Des Bosch NL
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20130064271 | ADAPTIVE EQUALIZER AND/OR ANTENNA TUNING - Equalization circuits and methods are implemented for a variety of applications. According to one such application, a transmitting device wirelessly communicates using an antenna. The device has a transmission circuit that is configured and arranged to transmit a first wireless signal using magnetic coupling between the antenna and a remote device, the coupling occurring over a wireless medium. A receiver circuit of the transmitting device is configured and arranged to receive a second wireless signal that is from the antenna and that represents the first wireless signal as modified by the coupling occurring over the wireless medium. An error circuit of the device is configured and arranged to generate an error signal by comparing the first wireless signal to the second wireless signal. An equalizer circuit of the device is configured and arranged to pre-code the first wireless signal with coding that compensates for inter-symbol interference by compensating for the error signal. | 03-14-2013 |
Massimo Ciacci, Den Bosch NL
Patent application number | Description | Published |
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20140003484 | PRE-EQUALIZER FOR A DIGITALLY MODULATED RF SIGNAL AND METHOD | 01-02-2014 |
20140038534 | HARMONIC SUPPRESSION IN SWITCHING AMPLIFIERS - Configurable suppression of harmonics in a radio frequency (RF) transmitter circuit having two class-D switching amplifiers that produce a differential output signal having introduced harmonics is contemplated. A selected harmonic is used to determine a time duration. A harmonic suppression circuit modifies a radio frequency polar modulated data signal that is encoded using an amplitude component and a phase component. The modification is responsive to the determined time duration. The switching power amplifiers amplify the modified polar modulated data signal to produce an amplified signal. The amplified signal includes three signal levels, a high signal level, a middle signal level and a low signal level. The timing of transitions between the high and low signal levels represents the phase component, and the transitions include the middle signal level for the time duration, thereby suppressing the selected harmonic. | 02-06-2014 |
20140145787 | AMPLIFIER WITH FILTERING - Signals are processed to facilitate the mitigation and/or cancellation of undesirable components within the signal. As consistent with one or more embodiments, input/delay circuits offset the phase of an input signal, as presented to respective amplifiers. The phase offset is used, upon combination of the outputs of the respective amplifiers, to cancel the undesirable components of the signal. Such an approach may, for example, involve phase offset in a digital domain, with correction upon combination of the signals as presented in an analog domain. | 05-29-2014 |
20140192931 | RECEIVER AND METHOD FOR NEAR FIELD COMMUNICATION - In one embodiment, an apparatus is provided that includes a first circuit configured and arranged to provide a modulated carrier signal in response to a signal provided from the antenna. The modulated carrier signal conveys data using peaks or amplitudes of the carrier signal. A second circuit is configured to rectify the modulated carrier signal and integrate the rectified signal in response to a first clock signal. A third circuit is coupled to an output of the second circuit and is configured to sample the integrated signal values and provide therefrom a sample-based approximation of the modulated carrier signal. | 07-10-2014 |