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| 20120015143 | Epitaxial substrate having nano-rugged surface and fabrication thereof - The invention provides an epitaxial substrate and fabrication thereof. The epitaxial substrate according to the invention includes a crystalline substrate. In particular, the crystalline substrate has an epitaxial surface which is nano-rugged and non-patterned. The epitaxial substrate according to the invention thereon benefits a compound semiconductor material in growth of epitaxy films with excellent quality. Moreover, the fabrication of the epitaxial substrate according to the invention has advantages of low cost and rapid production. | 01-19-2012 |
| 20120112158 | EPITAXIAL SUBSTRATE, SEMICONDUCTOR LIGHT-EMITTING DEVICE USING SUCH EPITAXIAL SUBSTRATE AND FABRICATION THEREOF - The invention provides an epitaxial substrate, a semiconductor light-emitting device using such epitaxial substrate and fabrication thereof. The epitaxial substrate according to the invention includes a crystalline substrate. In particular, a crystal surface of the crystalline substrate thereon has a plurality of randomly arranged nanorods. The plurality of nanorods is formed of oxide of a material different from that forms the crystalline substrate. | 05-10-2012 |
| 20120193764 | NANOSTRUCTURING PROCESS FOR INGOT SURFACE, WAFER MANUFACTURING METHOD, AND WAFER USING THE SAME - The instant disclosure relates to a nanostructuring process for an ingot surface prior to the slicing operation. A surface treatment step is performed for at least one surface of the ingot in forming a nanostructure layer thereon. The nanostructure layer is capable of enhancing the mechanical strength of the ingot surface to reduce the chipping ratio of the wafer during slicing. | 08-02-2012 |
| 20140220301 | EPITAXIAL SUBSTRATE HAVING NANO-RUGGED SURFACE AND FABRICATION THEREOF - The invention provides an epitaxial substrate and fabrication thereof. The epitaxial substrate according to the invention includes a crystalline substrate. In particular, the crystalline substrate has an epitaxial surface which is nano-rugged and non-patterned. The epitaxial substrate according to the invention thereon benefits a compound semiconductor material in growth of epitaxy films with excellent quality. Moreover, the fabrication of the epitaxial substrate according to the invention has advantages of low cost and rapid production. | 08-07-2014 |
| 20150284876 | CRYSTAL GROWTH APPARATUS AND THERMAL INSULATION COVER OF THE SAME - A crystal growth apparatus includes a crucible, a heating device, a thermal insulation cover, and a driving device. The crucible contains materials to be melted, wherein the heating device heats the crucible to melt the materials; the thermal insulation cover is provided upon the materials, wherein the thermal insulation cover includes a main body, which has a bottom surface facing an interior of the crucible, and a insulating member being provided at the main body; the driving device moves the thermal insulation cover towards or away from the materials, whereby, the thermal insulation cover effectively blocks heat conduction and heat convection, which prevents thermal energy from escaping out of the crucible. | 10-08-2015 |
| 20150299895 | STIRRING APPARATUS OF INGOT CASTING FURNACE - A stirring apparatus of an ingot casting furnace includes a rotating shaft and at least one fin. The fin is provided onto the rotating shaft, and has a first edge, a second edge of unequal length provided correspondingly, and a third edge connecting the first and the second edges. The rotating shaft can be driven to rotate, which consequently drives the at least one fin to stir materials in a crucible. The length of the first edge is different from that of the second edge in order for the materials in the crucible can be mixed with dopants more uniformly during the stirring process to produce ingots of stable quality. | 10-22-2015 |
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| 20140248422 | METHOD OF FABRICATING A CONDUCTIVE PATTERN WITH HIGH OPTICAL TRANSMISSION AND LOW VISIBILITY - A method of fabricating a conductive pattern includes disposing an image of the conductive pattern on a substrate. The image includes material capable of being electroless plated. The image is electroless plated with a first metal forming a first plated image. The first plated image is electroless plated with a second metal forming a second plated image. The second metal passivates the first metal. The second plated image is bathed in an immersion bath comprising a darkening material. | 09-04-2014 |
| 20150309600 | METHOD OF FABRICATING A CONDUCTIVE PATTERN WITH HIGH OPTICAL TRANSMISSION, LOW REFLECTANCE, AND LOW VISIBILITY - A method of fabricating a conductive pattern includes disposing an image of the conductive pattern on a substrate. The image includes material capable of being electroless plated. The image is electroless plated with a first metal forming a plated image. The first metal includes copper. The plated image is bathed in an immersion bath that includes a metal ion source of a second metal that reacts with the first metal. The second metal includes palladium. The conductive pattern includes a first metal layer having a first metal thickness, an intermetallic first metal-second metal interface layer, and a second metal layer having a second metal thickness. | 10-29-2015 |
| 20160040290 | ROLL-TO-ROLL ELECTROLESS PLATING SYSTEM FOR CONTROLLED SUBSTRATE DEPTH - A roll-to-roll electroless plating system for controlled substrate depth includes electroless plating solution disposed within an electroless plating bath, a conveyor system configured to convey a roll-to-roll substrate material through the electroless plating solution, a first depth setting roller disposed at an entry location of the roll-to-roll substrate material to the electroless plating solution, and a second depth setting roller disposed at an exit location of the roll-to-roll substrate material from the electroless plating solution. A diameter of the first and the second depth setting rollers is selected to dispose the roll-to-roll substrate material at a predetermined depth of the electroless plating solution. | 02-11-2016 |
| 20160040294 | METHOD OF CONTROLLING OXYGEN LEVELS FOR ELECTROLESS PLATING OF CATALYTIC FINE LINES OR FEATURES - A method of controlling oxygen levels for electroless plating of catalytic fine lines or features includes selecting a substrate that includes a plurality of catalytic lines or features that are part of or are disposed on the substrate. The plurality of catalytic lines or features include at least one catalytic fine line or feature and at least one catalytic standard line or feature. A dissolved oxygen concentration of an electroless plating solution is regulated to a candidate controlled oxygen level. The candidate controlled oxygen level is set to a smallest value in a regulated range in a first pass of the method. The substrate is submerged in the solution for a period of time sufficient to initiate plating of the at least one catalytic standard line or feature. The substrate is evaluated and candidate controlled oxygen level is incremented or the previous value is selected as the regulated oxygen level. | 02-11-2016 |
| 20160091998 | METHOD OF DESIGNING A CONDUCTIVE PATTERN WITH REDUCED CHANNEL BREAK VISIBILITY - A method of designing a conductive pattern with reduced channel break visibility includes generating a representation of the conductive pattern in a software application and placing a plurality of non-linear channel break voids that partition the conductive pattern into a plurality of channels. Each non-linear channel break isolates adjacent channels. | 03-31-2016 |
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| 20090283918 | SEMICONDUCTOR CHIP PACKAGE STRUCTURE - A semiconductor chip package structure is described. The semiconductor chip package structure comprises a first chip, which is operated through a first power connection, having a central region and a marginal region. The first chip comprises a plurality of first and second power bonding pads disposed in a marginal region on the top of the first chip. A first power ring and a second power ring are disposed on the first chip, wherein the first and second power rings are respectively electrically connected to the first and second power bonding pads. A second chip, which is operated through a second power connection, is mounted on the central region of the first chip, wherein the second chip comprises a plurality of power bonding pads thereon. A plurality of second bonding wires are electrically connected to the power bonding pads and the second power bonding pads, respectively. | 11-19-2009 |
| 20110004795 | METHOD FOR ENHANCING VERIFICATION EFFICIENCY REGARDING AN ERROR HANDLING MECHANISM OF A CONTROLLER OF A FLASH MEMORY, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method for enhancing verification efficiency regarding error handling mechanism of a controller of a Flash memory includes: providing an error generation module, for generating errors; and triggering the error generation module to actively generate errors of at least one specific type in order to increase an error rate corresponding to the specific type. An associated memory device and the controller thereof are provided, where the controller includes: a ROM arranged to store a program code; a microprocessor arranged to execute the program code to control access to the Flash memory and manage a plurality of blocks, and further enhance the verification efficiency regarding error handling mechanism of the controller; and an error generation module arranged to generate errors. The controller that executes the program code by utilizing the microprocessor triggers the error generation module to actively generate errors of at least one specific type to increase an error rate. | 01-06-2011 |
| 20130312123 | EMBEDDED MULTIMEDIACARD AND ELECTRONIC DEVICE USING THE SAME, AND ENERGINING BOARD FOR EMBEDDED MULTIMEDIACARD - An embedded MultiMediaCard (eMMC), an electronic device equipped with an eMMC and an eMMC engineering board are disclosed. The eMMC includes an eMMC substrate plate, a plurality of solder balls and an eMMC chip. The solder balls are soldered to the eMMC substrate plate, and, one of the solder balls is designed as a security protection enable/disable solder ball. The eMMC chip is bound to the eMMC substrate plate, and, the eMMC chip has a security protection enable/disable pin electrically connected to the security protection enable/disable solder ball. The security protection enable/disable pin is internally pulled high by the eMMC chip when the security protection enable/disable solder ball is floating. When the security protection enable/disable solder ball is coupled to ground, the eMMC is protected from software-based attacks. | 11-21-2013 |
| 20140304458 | MEMORY CONTROLLER AND ACCESSING SYSTEM UTILIZING THE SAME - A memory controller including a first transmittal module, a clock pin, a second transmittal module, a first control module and a second control module is disclosed. The first transmittal module includes a specific pin. The clock pin receives a clock signal. The first transmittal module and the clock pin constitute an embedded multimedia card (eMMC) interface. The second transmittal module and the clock pin constitute a universal flash storage (UFS) interface. The first control module communicates with an external host via the first transmittal module according to the clock signal when a level of the specific pin is at a first level. The second control module communicates with the external host via the second transmittal module according to the clock signal when the level of the specific pin is at a second level. The first level exceeds the second level. | 10-09-2014 |
| 20140380000 | MEMORY CONTROLLER AND ACCESSING SYSTEM UTILIZING THE SAME - A memory controller is coupled to a memory device including a first block and a second block and includes a first register module, a first execution unit and a second register module. The first register module includes a plurality of set registers to store a first configuration file and a second configuration file. The first execution unit computes data stored in the first block simultaneously according to the first and the second configuration files to generate a first computation result and a computation operation result. The second register module includes a plurality of result registers to store the first and the second computation results. | 12-25-2014 |
| 20140380026 | CONTROL DEVICE AND ACCESS SYSTEM UTILIZING THE SAME - A control device coupled between a first memory and a second memory and including an execution unit, a first storage unit, a second storage unit, a selection unit and a processing unit is disclosed. The execution unit executes a specific instruction set to access the first and the second memories. The first storage unit is configured to store a first instruction set. The second storage unit is configured to store a second instruction set. The selection unit outputs one of the first and the second instruction sets to serve as the specific instruction set according to a control signal. The processing unit generates the control signal according to an execution state of the execution unit. | 12-25-2014 |
