Patent application number | Description | Published |
20120171833 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - The present application discloses a method for manufacturing a semiconductor device, comprising the steps of: forming a semiconductor substrate, a gate stack and a second protection layer in sequence on a first insulating layer; after defining a gate region and removing portions of the second protection layer and the gate stack outside the gate region, while keeping portions of the stop layer, the semiconductor layer and the second insulating layer which covers sidewalls of the patterned semiconductor layer outside the gate region and exposing the sacrificial layer, performing source/drain ion implementation in the semiconductor layer; after forming a second sidewall spacer so as to cover at least the exposed portion of the sacrificial layer, removing the first protection layer and the second protection layer so as to expose the semiconductor layer and the gate stack; and forming a contact layer on the exposed portion of the semiconductor layer and the gate stack; performing planarization so as to expose the first protection layer, and then removing the first protection layer, the sacrificial layer, the stop layer and the semiconductor layer with the first sidewall spacer and the second sidewall spacer as a mask, so as to form a cavity which exposes the first insulating layer. It facilitates reduction of short channel effects, resistance of source/drain regions, and parasite capacitance. | 07-05-2012 |
20120247723 | WAFER TRANSFER APPARATUS AND WAFER TRANSFER METHOD - A water transfer apparatus and a wafer transfer method are provided. The wafer transfer apparatus is provided with a heating component and a cooling component, the heating component heats the wafer carrying component to a temperature the same as the wafer when it is just unloaded from the rapid thermal anneal tool, and the cooling component cools the wafer carrying component along with the wafer to room temperature, thereby avoiding the large temperature difference between the wafer and the wafer transfer apparatus, preventing the high thermal stress induced inside the wafer during wafer transfer, avoiding wafer breakage, and ensuring the completeness of the wafer. | 10-04-2012 |
20120252225 | SEMICONDUCTOR FABRICATION METHOD - A semiconductor fabrication method is provided, in which a protective layer is deposited on the dummy wafer such that the protective layer fully encases the dummy wafer. Therefore, the dummy wafer will not be oxidized during thermal oxidation, thereby reducing dummy wafer consumption, decreasing production cost, avoiding particulate matter produced due to oxidation of the dummy wafer, and preventing the wafer to be oxidized from contamination. | 10-04-2012 |
20120269710 | Thermal oxidation system and method for preventing water from accumulation - The invention proposes a thermal oxidation system, which comprises: a reaction furnace for preparing silicon oxide by wet oxidation; a vapor generating chamber, feed gases reacting in the vapor generating chamber to generate water vapor and the generated water vapor entering the reaction furnace through the delivery of a pipeline; a feed gas inlet pipeline for providing the feed gases to the vapor generating chamber; a carrier gas inlet pipeline for providing the carrier gas to the reaction furnace; and a heater coupled to the feed gas inlet pipeline for heating the feed gases to promote their reaction to generate water vapor; characterized in that, the thermal oxidation system further comprises a heating device coupled to the carrier gas inlet pipeline. In the thermal oxidation system and method according to the invention, since the carrier gas is heated, liquid water is avoided to remain in the gas inlet pipeline, which controls the quality in growth of the film, and improves the reliability of the semiconductor device. | 10-25-2012 |
20120270165 | HEATING METHOD FOR MAINTAINING A STABLE THERMAL BUDGET - The present invention discloses a heating method for maintaining a stable thermal budget. By following the primary procedure with a virtual procedure in such a manner that the total duration of the whole heating process remains constant, it is beneficial to maintain a stable thermal budget and further to maintain a stable device performance. | 10-25-2012 |
20120319215 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The present invention discloses a semiconductor device and method of manufacturing the same, comprising: forming an insulating isolation layer on a substrate; forming an insulating isolation layer trench in the insulating isolation layer; forming an active region layer in the insulating isolation layer trench; and forming a semiconductor device structure in and above the active region layer, wherein the carrier mobility of the active region layer is higher than that of the substrate. In accordance with the semiconductor device and the manufacturing method thereof in the present invention, an active region formed of a material different from that of the substrate is used, the carrier mobility in the channel region is enhanced, thereby the device response speed is substantially improved and the device performance is enhanced greatly. Furthermore, unlike the existing STI manufacturing process, in the present invention a STI is formed first, and then filling is performed to form an active region, to avoid the problem of generation of holes in the STI and improve the device reliability. | 12-20-2012 |
20130105859 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME | 05-02-2013 |
20140273426 | Method for Manufacturing Dummy Gate in Gate-Last Process and Dummy Gate in Gate-Last Process - A method for manufacturing a dummy gate in a gate-last process and a dummy gate in a gate-last process are provided. The method includes: providing a semiconductor substrate; growing a gate oxide layer on the semiconductor substrate; depositing bottom-layer amorphous silicon on the gate oxide layer; depositing an ONO structured hard mask on the bottom-layer amorphous silicon; depositing top-layer amorphous silicon on the ONO structured hard mask; depositing a hard mask layer on the top-layer amorphous silicon, and trimming the hard mask layer so that the trimmed hard mask layer has a width less than or equal to 22 nm; and etching the top-layer amorphous silicon, the ONO structured hard mask and the bottom-layer amorphous silicon in accordance with the trimmed hard mask layer, and removing the hard mask layer and the top-layer amorphous silicon. | 09-18-2014 |
20140332958 | Method for Manufacturing Dummy Gate in Gate-Last Process and Dummy Gate in Gate-Last Process - A method for manufacturing a dummy gate in a gate-last process is provided. The method includes: providing a semiconductor substrate; growing a gate oxide layer on the semiconductor substrate; depositing bottom-layer amorphous silicon on the gate oxide layer; depositing an ONO structured hard mask on the bottom-layer amorphous silicon; depositing top-layer amorphous silicon on the ONO structured hard mask; depositing a hard mask layer on the top-layer amorphous silicon; forming photoresist lines having a width ranging from 32 nm to 45 nm on the hard mask layer; and etching the hard mask layer, the top-layer amorphous silicon, the ONO structured hard mask and the bottom-layer amorphous silicon in accordance with the photoresist lines, and removing the photoresist lines, the hard mask layer and the top-layer α-Si. Correspondingly, a dummy gate in a gate-last process is also provided. | 11-13-2014 |
20150035087 | Method for Manufacturing Dummy Gate in Gate-Last Process and Dummy Gate in Gate-Last Process - A method for manufacturing a dummy gate in a gate-last process and a dummy gate in a gate-last process are provided. The method includes: providing a semiconductor substrate; growing a gate oxide layer on the semiconductor substrate; depositing bottom-layer amorphous silicon on the gate oxide layer; depositing an ONO structured hard mask on the bottom-layer amorphous silicon; depositing top-layer amorphous silicon on the ONO structured hard mask; depositing a hard mask layer on the top-layer amorphous silicon; forming photoresist lines on the hard mask layer, and trimming the formed photoresist lines so that the trimmed photoresist lines a width less than or equal to 22 nm; and etching the hard mask layer, the top-layer amorphous silicon, the ONO structured hard mask and the bottom-layer amorphous silicon in accordance with the trimmed photoresist lines, and removing the photoresist lines, the hard mask layer and the top-layer amorphous silicon. | 02-05-2015 |