Patent application number | Description | Published |
20090073992 | SYSTEM AND METHOD FOR PROVIDING PROXY AND TRANSLATION DOMAINS IN A FIBRE CHANNEL ROUTER - A Fibre Channel router used to join fabrics. EX_ports are used to connect to the fabrics. The EX_port joins the fabric but the router will not merge into the fabric. Ports in the Fibre Channel router can be in a fabric, but other ports can be connected to other fabrics. Fibre Channel routers can be interconnected using a backbone fabric. Global, interfabric and encapsulation headers are developed to allow routing by conventional Fibre Channel switch devices in the backbone fabric and simplify Fibre Channel router routing. Phantom domains and devices must be developed for each of the fabrics being interconnected. Front phantom domains are present at each port directly connected to a fabric. Each of these is then connected to at least one translate phantom domain. Zoning is accomplished by use of a special LSAN zoning naming convention. This allows each administrator to independently define devices are accessible. | 03-19-2009 |
20110085557 | Partitioning of Switches and Fabrics into Logical Switches and Fabrics | 04-14-2011 |
20110085558 | Virtual and Logical Inter-Switch Links | 04-14-2011 |
20110085559 | Transit Switches in a Network of Logical Switches - A Layer 2 network switch is partitionable into a plurality of switch fabrics. The single-chassis switch is partitionable into a plurality of logical switches, each associated with one of the virtual fabrics. The logical switches behave as complete and self-contained switches. A logical switch fabric can span multiple single-chassis switch chassis. Logical switches are connected by inter-switch links that can be either dedicated single-chassis links or logical links. An extended inter-switch link can be used to transport traffic for one or more logical inter-switch links. Physical ports of the chassis are assigned to logical switches and are managed by the logical switch. Legacy switches that are not partitionable into logical switches can serve as transit switches between two logical switches. | 04-14-2011 |
20110103258 | SELECTIVE NETWORK MERGING - Subsets of isolated communications networks are selectively merged without merging the entire isolated communications networks, and devices are imported across isolated communications networks without merging the isolated communications networks. The presently disclosed technology provides for improved scalability, performance, and security in logical networks spanning two or more physical communications networks. | 05-05-2011 |
20110216778 | MULTIFABRIC ZONE DEVICE IMPORT AND EXPORT - A Fibre Channel router used to join fabrics. EX_ports are used to connect to the fabrics. The EX_port joins the fabric but the router will not merge into the fabric. Ports in the Fibre Channel router can be in a fabric, but other ports can be connected to other fabrics. Fibre Channel routers can be interconnected using a backbone fabric. Global, interfabric and encapsulation headers are developed to allow routing by conventional Fibre Channel switch devices in the backbone fabric and simplify Fibre Channel router routing. Phantom domains and devices must be developed for each of the fabrics being interconnected. Front phantom domains are present at each port directly connected to a fabric. Each of these is then connected to at least one translate phantom domain. Zoning is accomplished by use of a special LSAN zoning naming convention. This allows each administrator to independently define devices are accessible. | 09-08-2011 |
20120106957 | Single Virtual Domain Fibre Channel over Ethernet Fabric - The entire FCoE fabric is a single virtual domain, even though there may be multiple FCFs and FDFs. The virtual domain is a different Domain_ID than any of the FCFs. In certain embodiments there are multiple FCFs, of which one is selected as the master or designated FCF. The master FCF performs normal fabric configuration in conjunction with the Fibre Channel fabric. The master FCF assigns the virtual domain FC node IDs and controls development of subdomain IDs. Virtual links are instantiated between the master FCF and other FCFs, between top level FDFs and the FCFs and between the FDFs at each of various levels. FDFs connected to ENodes proxy the master FCF for most FIP operations. FIP FLOGI and FDISC operations are handled by the master FDF, but the FDFs convert the FIP FLOGI requests to VD_FLOGI requests, which include information about the FDF handling the transaction. | 05-03-2012 |
20140313934 | Selective Network Merging - Subsets of isolated communications networks are selectively merged without merging the entire isolated communications networks, and devices are imported across isolated communications networks without merging the isolated communications networks. The presently disclosed technology provides for improved scalability, performance, and security in logical networks spanning two or more physical communications networks. | 10-23-2014 |
Patent application number | Description | Published |
20130082754 | PHASE LOCKED LOOP CALIBRATION - An inductor-capacitor phase locked loop (LCPLL) includes an inductor-capacitor voltage controlled oscillator (LCVCO) that provides an output frequency. A calibration circuit includes two comparators and provides a coarse tune signal to the LCVCO. The two comparators respectively compare the loop filter signal with a first reference voltage and a second reference voltage that is higher than the first reference voltage to supply a first and second comparator output, respectively. The calibration circuit is capable of adjusting the coarse tune signal continuously in voltage values and adjusts the coarse tune signal based on the two comparator outputs. A loop filter provides a loop filter signal to the calibration circuit and a fine tune signal to the LCVCO. A coarse tune frequency range is greater than a fine tune frequency range. | 04-04-2013 |
20130099767 | DRIVERS HAVING T-COIL STRUCTURES - A driver includes a first driver stage having at least one input node and at least one first output node. The first driver stage includes a T-coil structure that is disposed adjacent to the at least one first output node. The T-coil structure includes a first set of inductors each being operable to provide a first inductance. A second set of inductors are electrically coupled with the first set of inductors in a parallel fashion. The second set of inductors each are operable to provide a second inductance. A second driver stage is electrically coupled with the first driver stage. | 04-25-2013 |
20130120884 | INPUT/OUTPUT CIRCUIT WITH INDUCTOR - An input/output (I/O) circuit includes an electrostatic discharge (ESD) protection circuit electrically coupled with an output node of the I/O circuit. At least one inductor and at least one loading are electrically coupled in a series fashion and between the output node of the I/O circuit and a power line. A circuitry is electrically coupled with a node between the at least one inductor and the at least one loading. The circuitry is operable to increase a current flowing through the at least one inductor during a signal transition. | 05-16-2013 |
20130121396 | DECISION FEEDBACK EQUALIZER HAVING PROGRAMMABLE TAPS - A Decision Feedback Equalizer (DFE) with programmable taps includes a summer configured to receive a DFE input signal. Delay elements are coupled to the summer. The delay elements are connected in series. Each delay element provides a respective delayed signal of an input signal to the delay element. A weight generator is configured to provide tap weights. The DFE is configured to multiply each tap weight to the respective delayed signal from the respective delay element to provide tap outputs. Each tap output is selectively enabled to be added to the summer or disabled based on a first comparison of a first threshold value and each impulse response or each tap weight corresponding to the respective tap output, where the impulse response is the DFE input signal in response to a pulse signal transmitted through a channel. | 05-16-2013 |
20130141170 | AMPLIFIER INDUCTOR SHARING FOR INDUCTIVE PEAKING - A method of sharing inductors for inductive peaking of an amplifier having at least two stages includes calculating a single stage inductance of a single stage of the at least two stages for inductive peaking in order to have a stable impulse response. A shared inductance is calculated for inductive peaking by dividing the single stage inductance by a number of stages of the at least two stages. At least two inductors having the shared inductance are shared among the at least two stages for inductive peaking. | 06-06-2013 |
20130342247 | CAPACTIVE LOAD PLL WITH CALIBRATION LOOP - A circuit includes a capacitive-load voltage controlled oscillator having an input configured to receive a first input signal and an output configured to output an oscillating output signal. A calibration circuit is coupled to the voltage controlled oscillator and is configured to output one or more control signals to the capacitive-load voltage controlled oscillator for adjusting a frequency of the oscillating output signal. The calibration circuit is configured to output the one or more control signals in response to a comparison of an input voltage to at least one reference voltage. | 12-26-2013 |
20130346811 | DECISION FEEDBACK EQUALIZER - A circuit includes a summation circuit for receiving an input data signal and a feedback signal including a previous data bit. The summation circuit is configured to output a conditioned input data signal to a clock and data recovery circuit. A first flip-flop is coupled to an output of the summation circuit and is configured to receive a first set of bits of the conditioned input data signal and a first clock signal having a frequency that is less than a frequency at which the input data signal is received by the first summation circuit. A second flip-flop is coupled to the output of the summation circuit and is configured to receive a second set of bits of the conditioned input data signal and a second clock signal having a frequency that is less than the frequency at which the input data signal is received by the first summation circuit. | 12-26-2013 |
20140002332 | PIXELS FOR DISPLAY | 01-02-2014 |
20140015582 | SLICER AND METHOD OF OPERATING THE SAME - This description relates to a slicer including a first latch. The first latch includes an evaluating transistor configured to receive a first clock signal and a developing transistor configured to receive a second clock signal. The first clock signal is different from the second clock signal. The first latch includes first and second input transistors configured to receive first and second complementary inputs. The first latch includes at least one pre-charging transistor configured to receive a third clock signal. The first latch further at least one cross-latched pair of transistors, the at least one cross-latched transistor pair connected between the evaluating transistor and the first and second output nodes. The slicer includes a second latch connected to the first and second output nodes and to a third output node. The slicer includes a buffer connected to the third output node and configured to generate a final output signal. | 01-16-2014 |
20140015611 | METHOD AND APPARATUS FOR FEEDBACK-BASED RESISTANCE CALIBRATION - A circuit has a first circuit module including a first resistor and first and second transistors coupled in parallel with the first resistor. The first resistor and the first and second transistors are coupled together at a first node. An equivalent resistance across the first circuit module increases as a voltage of the first node is increased from a first voltage to a second voltage, and the equivalent resistance across the first circuit module decreases as the voltage of the first node is increased from the second voltage to a third voltage. | 01-16-2014 |
20140028407 | Reconfigurable and Auto-Reconfigurable Resonant Clock - The present disclosure relates to a resonant clock system having a driver component, a clock load capacitor, and a reconfigurable inductor array. The driver component generates a driven input signal. The clock load capacitor is configured to receive the driven input signal. The inductor array is configured to have an effective inductance according to a selected frequency. The inductor array also generates a resonant signal at the selected frequency using the effective inductance. | 01-30-2014 |
20140037035 | PHASE INTERPOLATOR FOR CLOCK DATA RECOVERY CIRCUIT WITH ACTIVE WAVE SHAPING INTEGRATORS - A phase interpolator for a CDR circuit produces an output clock having level transitions between the level transitions on two input clocks. The input clocks drive cross-coupled differential amplifiers with an output that can be varied in phase by variable current throttling or steering, according to an input control value. The differential amplifiers produce an output signal with a transition spanning a time between the start of a transition on the leading input clock up to the end of the transition on the lagging input clock. The output clock is linear so long as the transitions on the two input clocks overlap. Active integrators each having an amplifier with a series resistance and capacitive feedback path are coupled to each input to the cross-coupled differential amplifiers, which enhances overlap of the input clock rise times and improves the linearity of the interpolated output signal. | 02-06-2014 |
20140038085 | Automatic Misalignment Balancing Scheme for Multi-Patterning Technology - Some aspects of the present disclosure provide for a method of automatically balancing mask misalignment for multiple patterning layers to minimize the consequences of mask misalignment. In some embodiments, the method defines a routing grid for one or more double patterning layers within an IC layout. The routing grid has a plurality of vertical grid lines extending along a first direction and a plurality of horizontal grid lines extending along a second, orthogonal direction. Alternating lines of the routing grid in a given direction (e.g., the horizontal and vertical direction) are assigned different colors. Shapes on the double patterning layers are then routed along the routing grid in a manner that alternates between different colored grid lines. By routing in such a manner, variations in capacitive coupling caused by mask misalignment are reduced. | 02-06-2014 |
20140085009 | AMPLIFIER INDUCTOR SHARING FOR INDUCTIVE PEAKING AND METHOD THEREFOR - A method of sharing inductors for inductive peaking of an amplifier includes calculating a single stage inductance of a single stage for inductive peaking in order to have a stable impulse response. The method further includes determining a number of stages for shared inductance for inductive peaking. The method further includes sharing at least two inductors having the shared inductance among the determined number of stages for inductive peaking. | 03-27-2014 |
20140092511 | INPUT/OUTPUT CIRCUIT HAVING AN INDUCTOR - An input/output (I/O) circuit includes an electrostatic discharge (ESD) protection circuit electrically coupled with an output node of the I/O circuit. At least one inductor and at least one loading are electrically coupled in a series fashion and between the output node of the I/O circuit and a power line. A circuitry is electrically coupled with a node between the at least one inductor and the at least one loading. The circuitry is operable to increase a current flowing through the at least one inductor during a signal transition. The circuitry comprises at least one pre-driver stage having at least one output node, and the at least one output node of the at least one pre-driver stage is electrically coupled with at least one input node of a driver stage. | 04-03-2014 |
20140119426 | SLICER AND METHOD OF OPERATING THE SAME - A slicer includes a first latch. The first latch includes an evaluating transistor configured to receive a first clock signal. The first latch further includes a developing transistor configured to receive a second clock signal, wherein the first clock signal is different from the second clock signal. The first latch further includes a first input transistor configured to receive a first input. The first latch further includes a second input transistor configured to receive a second input, wherein the first and second input transistors are connected with the developing transistor. The first latch further includes at least one pre-charging transistor configured to receive a third clock signal, wherein the at least one pre-charging transistor is connected to a first output node and a second output node. The slicer further includes a second latch connected to the first and second output nodes and to a third output node. | 05-01-2014 |
20140126656 | CLOCK DATA RECOVERY CIRCUIT WITH HYBRID SECOND ORDER DIGITAL FILTER HAVING DISTINCT PHASE AND FREQUENCY CORRECTION LATENCIES - A clock data recovery circuit (CDR) extracts bit data values from a serial bit stream without reference to a transmitter clock. A controllable oscillator produces a regenerated clock signal controlled to match the frequency and phase of transitions between bits and the serial data is sampled at an optimal phase. A phase detector generates early-or-late indication bits for clock versus data transition times, which are accumulated and applied to a second order feedback control with two distinct feedback paths for frequency and phase, combined for correcting the controllable oscillator, selecting a sub-phase and/or determining an optimal phase at which the bit stream data values are sampled. The second order filter is operated at distinct rates such that the phase correction has a latency as short as one clock cycle and the frequency correction latency occurs over plural cycles. | 05-08-2014 |
20140184299 | VOLTAGE LEVEL SHIFTER - A circuit includes a first capacitive device and a first latch. The first capacitive device includes a first end configured to receive a first input signal and a second end coupled with the first latch. The first latch includes a first transistor and a second transistor that are of a first type. A first terminal of the first transistor and a first terminal of the second transistor are each configured to receive a first voltage value. A second terminal of the first transistor is coupled with a third terminal of the second transistor. A third terminal of the first transistor is coupled with a second terminal of the second transistor and with the second end of the capacitive device, and is configured to provide an output voltage for the first latch. | 07-03-2014 |
20140185401 | SENSING CIRCUIT, MEMORY DEVICE AND DATA DETECTING METHOD - A sensing circuit includes a sensing resistor, a reference resistor and a comparator. The comparator has a first input coupled to the sensing resistor, a second input coupled to the reference resistor, and an output. The first input is configured to be coupled to a data bit line associated with a memory cell to receive a sensing input voltage caused by a cell current of the memory cell flowing through the sensing resistor. The second input is configured to be coupled to a reference bit line associated with a reference cell to receive a sensing reference voltage caused by a reference current of the reference cell flowing through the reference resistor. The comparator is configured to generate, at the output, an output signal indicating a logic state of data stored in the memory cell based on a comparison between the sensing input voltage and the sensing reference voltage. | 07-03-2014 |
20140189623 | PARASITIC COMPONENT LIBRARY AND METHOD FOR EFFICIENT CIRCUIT DESIGN AND SIMULATION USING THE SAME - A method for circuit design includes a parasitic aware library embedded with one or more parameterized cells. The parasitic aware library is used to insert nets representing some but not all parasitic effects of a circuit into a circuit schematic enabling a single circuit schematic to be used for simulation of the circuit, parasitic verification of the circuit and LVS (Layout Versus Schematic) check. Only the single circuit schematic is required for the circuit design process and to form a mask set. Critical paths of the single circuit schematic are identified and parasitic effects are extracted and inserted into the schematic, enabling a pre-estimation of parasitic verification to be carried out and the LVS check to be carried out using a circuit schematic with some parasitic effects prior to the post-layout simulation in which all parasitic components of the layout are included. | 07-03-2014 |
20140266118 | VOLTAGE REGULATOR - A voltage regulator includes a driving circuit, a feedback circuit, first and second control circuits and a resistor. The driving circuit is coupled to an input node and an output node and generates an output voltage at the output node from an input voltage at the input node. The feedback circuit is coupled to the output node and generates a feedback voltage based on the output voltage. The first control circuit is coupled to the feedback circuit and the driving circuit to control the output voltage based on the feedback voltage. The resistor has opposite first and second terminals. The first terminal of the resistor is coupled to the output node. The second control circuit is coupled to the second terminal of the output stage resistor and the feedback circuit to control the feedback voltage based on a regulated voltage at the second terminal of the resistor. | 09-18-2014 |
20140282308 | METHOD OF RADIO-FREQUENCY AND MICROWAVE DEVICE GENERATION - The present disclosure relates to an apparatus and method to generate a device library, along with layout versus schematic (LVS) and parasitic extraction set-up files for connecting with official tools of a design window supported by a process design kit (PDK). The device library comprises passive devices which can be utilized at any point in an end-to-end design flow from pre-layout verification to post-layout verification of an integrated circuit design. The device library allows for a single schematic view for pre-layout verification but also post-layout verification, thus allowing for pole or pin comparison, and prevents double-counting of parasitic effects from passive design elements by directly instantiating a device from the device library for a verification step. An LVS and parasitic extraction graphical user interface (GUI) allows for incorporation of the generated device library into a pre-existing PDK without any modification to the PDK. Other devices and methods are also disclosed. | 09-18-2014 |
20140347110 | CAPACITIVE LOAD PLL WITH CALIBRATION LOOP - A circuit includes a capacitive-load voltage controlled oscillator having an input configured to receive a first input signal and an output configured to output an oscillating output signal. A calibration circuit is coupled to the voltage controlled oscillator and is configured to output one or more control signals to the capacitive-load voltage controlled oscillator for adjusting a frequency of the oscillating output signal. The calibration circuit is configured to output the one or more control signals in response to a comparison of an input voltage to at least one reference voltage. | 11-27-2014 |
20150014518 | HIGH-SPEED TRANSIMPEDANCE AMPLIFIER - A transimpedance amplifier includes a first inverter having a first input node and a first output node. The first input node is configured to receive an input signal. A second inverter has a second input node and a second output node. The second input node connects to a reference voltage terminal. The first inverter and the second inverter are configured to provide a differential output voltage signal between the first output node and the second output node. A first amplifier is configured to provide feedback to the first input node and a second amplifier is configured to provide feedback to the second input node. | 01-15-2015 |
20150035566 | DRIVERS HAVING T-COIL STRUCTURES - A driver includes a first driver stage having a first T-coil structure. The first T-coil structure includes a first set of inductors each being operable to provide a first inductance. The first T-coil structure further includes a second set of inductors electrically coupled with the first set of inductors, wherein the second set of inductors each are operable to provide a second inductance. | 02-05-2015 |
20150074629 | PARASITIC COMPONENT LIBRARY AND METHOD FOR EFFICIENT CIRCUIT DESIGN AND SIMULATION USING THE SAME - A method for circuit design includes a parasitic aware library embedded with one or more parameterized cells. The parasitic aware library is used to insert nets representing some but not all parasitic effects of a circuit into a circuit schematic enabling a single circuit schematic to be used for simulation of the circuit, parasitic verification of the circuit and LVS (Layout Versus Schematic) check. Only the single circuit schematic is required for the circuit design process and to form a mask set. Critical paths of the single circuit schematic are identified and parasitic effects are extracted and inserted into the schematic, enabling a pre-estimation of parasitic verification to be carried out and the LVS check to be carried out using a circuit schematic with some parasitic effects prior to the post-layout simulation in which all parasitic components of the layout are included. | 03-12-2015 |
20150131711 | APPARATUS HAVING PROGRAMMABLE TAPS - An apparatus comprises a plurality of delay elements connected in series. Each delay element is configured to delay a respective input signal and to output a respective delayed signal. The apparatus also comprises a weight generator configured to generate a plurality of tap weights based on the delayed signals. The apparatus further comprises a tap controller configured to (1) generate tap weight enabling signals corresponding to one or more of the tap weights based on a determination that the corresponding tap weights are greater than a predetermined threshold value, and (2) generate a set of bias factors. The apparatus additionally comprises a summer configured to output a weighted signal based on the delayed signals, the tap weight enabling signals, the tap weights, and the bias factors. | 05-14-2015 |
20150319017 | APPARATUS HAVING PROGRAMMABLE TAPS AND METHOD OF USING THE SAME - An apparatus includes a plurality of delay elements configured to delay a respective input signal and to output a respective delayed signal. The apparatus also includes a weight generator configured to generate a plurality of tap weights based on the delayed signals. The apparatus further includes a tap controller configured to generate tap weight enabling signals corresponding to one or more of the tap weights if the corresponding tap weights are greater than a predetermined threshold value. The tap controller is also configured to generate a set of bias factors based on corresponding tap weights of the plurality of tap weights. | 11-05-2015 |
Patent application number | Description | Published |
20090318914 | SYSTEM AND METHOD FOR ABLATIONAL TREATMENT OF UTERINE CERVICAL NEOPLASIA - The invention provides a system, devices, and methods for ablating abnormal epithelial tissue of the uterine cervix. Embodiments of an ablation device include an operative head with a support surface adapted to conformably engage and therapeutically contact the cervix, and an energy delivery element on the support surface. The energy delivery element is configured to deliver energy, such as RF energy, to the tissue in a manner that controls the surface area and depth of ablation. The device may further include a shaft and a handle to support the ablation device, and may further include a speculum to facilitate access to the cervix. A system to support the operation of the ablation device includes a generator to deliver energy to the energy delivery element. Embodiments of a method for ablating abnormal cervical tissue include inserting an ablation device intravaginally to contact the cervix, aligning an energy delivery element support surface conformably against a region of the cervix with abnormal tissue, and ablating the tissue. | 12-24-2009 |
20100004654 | ACCESS AND TISSUE MODIFICATION SYSTEMS AND METHODS - Described herein are methods and systems for precisely placing and/or manipulating devices within the body by first positioning a guidewire or pullwire through the body from a first location, around a curved pathway, and out of the body through a second location, so that the distal and proximal ends of the guidewire extend from the body, then pulling a device into position using the guidewire. The device to be positioned within the body is coupled to the proximal end of the guidewire, and the device is pulled into the body by pulling on the distal end of the guidewire that extends from the body. The device may be bimanually manipulated by pulling the guidewire distally, and an attachment to the device that extends proximally, allowing control of both the proximal and the distal ends. In this manner devices (and particularly implants such as innerspinous distracters, stimulating leads, and disc slings) may be positioned and/or manipulated within the body. Devices to modify tissue may also be positioned or manipulated so that a target tissue within the body is modified. | 01-07-2010 |
20100331883 | ACCESS AND TISSUE MODIFICATION SYSTEMS AND METHODS - Described herein are methods and systems for precisely placing and/or manipulating devices within the body by first positioning a guidewire or pullwire through the body from a first location, around a curved pathway, and out of the body through a second location, so that the distal and proximal ends of the guidewire extend from the body, then pulling a device into position using the guidewire. The device to be positioned within the body is coupled to the proximal end of the guidewire, and the device is pulled into the body by pulling on the distal end of the guidewire that extends from the body. The device may be bimanually manipulated by pulling the guidewire distally, and an attachment to the device that extends proximally, allowing control of both the proximal and the distal ends. In this manner devices (and particularly implants such as innerspinous distracters, stimulating leads, and disc slings) may be positioned and/or manipulated within the body. Devices to modify tissue may also be positioned or manipulated so that a target tissue within the body is modified. | 12-30-2010 |
20110060314 | DEVICES AND METHODS FOR TREATING TISSUE - Described herein are devices, systems and methods for treating target tissue in a patient's spine. In general, the methods include the steps of advancing a wire into the patient from a first location, through a neural foramen, and out of the patient from a second location; connecting a tissue modification device to the wire; positioning the tissue modification device through the neural foramen using the wire; modifying target tissue in the spine by moving the tissue modification device against the target tissue; and delivering an agent to modified target tissue, wherein the agent is configured to inhibit blood flow from the modified target tissue. In some embodiments, the step of modifying target tissue comprises removing target tissue located ventral to the superior articular process while avoiding non-target tissue located lateral to the superior articular process. | 03-10-2011 |
20130053851 | ACCESS AND TISSUE MODIFICATION SYSTEMS AND METHODS - Described herein are methods and systems for precisely placing and/or manipulating devices within the body by first positioning a guidewire or pullwire. The device to be positioned within the body is coupled to the proximal end of the guidewire, and the device is pulled into the body by pulling on the distal end of the guidewire that extends from the body. The device may be bimanually manipulated by pulling the guidewire distally, and an attachment to a device that extends proximally, allowing control of both the proximal and the distal ends. In this manner devices (and particularly implants such as innerspinous distracters, stimulating leads, and disc slings) may be positioned and/or manipulated within the body. Guidewire exchange systems, devices and methods are also described. A guidewire may be exchanged between different surgical devices and may be releaseably or permanently coupled. | 02-28-2013 |
20140107709 | ACCESS AND TISSUE MODIFICATION SYSTEMS AND METHODS - Described herein are methods and systems for precisely placing and/or manipulating devices within the body by first positioning a guidewire or pullwire. The device to be positioned within the body is coupled to the proximal end of the guidewire, and the device is pulled into the body by pulling on the distal end of the guidewire that extends from the body. The device may be bimanually manipulated by pulling the guidewire distally, and an attachment to a device that extends proximally, allowing control of both the proximal and the distal ends. In this manner devices (and particularly implants such as innerspinous distracters, stimulating leads, and disc slings) may be positioned and/or manipulated within the body. Guidewire exchange systems, devices and methods are also described. A guidewire may be exchanged between different surgical devices and may be releaseably or permanently coupled. | 04-17-2014 |
Patent application number | Description | Published |
20080226929 | SILICON-RICH SILICON NITRIDES AS ETCH STOP IN MEMS MANUFACTURE - The fabrication of a MEMS device such as an interferometric modulator is improved by employing an etch stop layer between a sacrificial layer and a an electrode. The etch stop may reduce undesirable over-etching of the sacrificial layer and the electrode. The etch stop layer may also serve as a barrier layer, buffer layer, and/or template layer. The etch stop layer may include silicon-rich silicon nitride. | 09-18-2008 |
20090305010 | LOW TEMPERATURE AMORPHOUS SILICON SACRIFICIAL LAYER FOR CONTROLLED ADHESION IN MEMS DEVICES - Methods of fabricating an electromechanical systems device that mitigate permanent adhesion, or stiction, of the moveable components of the device are provided. The methods provide an amorphous silicon sacrificial layer with improved and reproducible surface roughness. The amorphous silicon sacrificial layers further exhibit excellent adhesion to common materials used in electromechanical systems devices. | 12-10-2009 |
20100202038 | MEMS DEVICE AND INTERCONNECTS FOR SAME - A microelectromechanical systems device having an electrical interconnect connected to at least one of an electrode and a movable layer within the device. At least a portion of the electrical interconnect is formed from the same material as a movable layer of the device. A thin film, particularly formed of molybdenum, is provided underneath the electrical interconnect. The movable layer preferably comprises aluminum. | 08-12-2010 |
20110051224 | LOW TEMPERATURE AMORPHOUS SILICON SACRIFICIAL LAYER FOR CONTROLLED ADHESION IN MEMS DEVICES - Methods of fabricating an electromechanical systems device that mitigate permanent adhesion, or stiction, of the moveable components of the device are provided. The methods provide an amorphous silicon sacrificial layer with improved and reproducible surface roughness. The amorphous silicon sacrificial layers further exhibit excellent adhesion to common materials used in electromechanical systems devices. | 03-03-2011 |
20110205197 | ELECTROMECHANICAL DEVICES HAVING SUPPORT STRUCTURES AND METHODS OF FABRICATING THE SAME - Embodiments of MEMS devices comprise a conductive movable layer spaced apart from a conductive fixed layer by a gap, and supported by rigid support structures, or rivets, overlying depressions in the conductive movable layer, or by posts underlying depressions in the conductive movable layer. In certain embodiments, both rivets and posts may be used. In certain embodiments, these support structures are formed from rigid inorganic materials, such as metals or oxides. In certain embodiments, etch barriers may also be deposited to facilitate the use of materials in the formation of support structures which are not selectively etchable with respect to other components within the MEMS device. | 08-25-2011 |