Patent application number | Description | Published |
20100237348 | Thin Film Transistor Array Substrate - A thin film transistor (TFT) array substrate includes a stack structure disposed to raise an extended electrode of a drain electrode of a thin film transistor. Therefore, a contact hole does need to be very deep to expose the extended electrode of the drain electrode. | 09-23-2010 |
20110001138 | Thin Film Transistor Array and Method for Manufacturing the Same - A thin film transistor (TFT) array includes a substrate, a thin film transistor, a first wall, a transparent electrode and a color resist. The thin film transistor is disposed on the substrate. The first wall is disposed on the substrate and separates a first contact hole from a pixel region on the substrate, wherein the first contact hole exposes a drain electrode of the thin film transistor. The first wall has a first sidewall facing towards the first contact hole and a second sidewall facing towards the pixel region, wherein the slope of the first sidewall is gentler than the slope of the second sidewall. The transparent electrode is electrically connected to the drain electrode of the thin film transistor through the first contact hole. The pixel region is filled with the color resist. | 01-06-2011 |
20110149224 | POLYMER STABILIZATION ALIGNMENT LIQUID CRYSTAL DISPLAY PANEL AND LIQUID CRYSTAL DISPLAY PANEL - The present invention provides a polymer stabilization alignment liquid crystal display panel having a plurality of pixel regions. Each pixel region includes a main region and a sub region, and a first pixel electrode and a second pixel electrode correspond to the main region and the sub region respectively. Each first pixel electrode is separated from the adjacent data line and thereby forming a gap therebetween. Each second pixel electrode partially overlaps the adjacent data line. In addition, each second pixel electrode includes a plurality of branches, and at least one edge of the branches may be parallel to the data lines. Accordingly, the present invention not only can increase the aperture ratio, but also well control the liquid crystal molecules located near the data lines. Therefore, the display quality of the liquid crystal display panel can be improved. | 06-23-2011 |
20110317103 | LIQUID CRYSTAL DISPLAY PANEL - A liquid crystal display panel includes a first substrate, a second substrate, a liquid crystal layer, pixel regions, pixel electrodes and color filters. Each pixel region at least includes a main pixel region and a sub pixel region. Each pixel electrode is disposed on the first substrate. Each pixel electrode includes a first electrode disposed in the main pixel region and a second electrode disposed in the sub pixel region. Each color filter is disposed between the first substrate and the second substrate and corresponds to each pixel region. Each color filter includes a curved surface facing the liquid crystal layer and an extreme thickness position. When a predetermined voltage is applied to each pixel electrode, aligning directions of the liquid crystal molecules disposed above the first electrode are converged toward a center. The extreme thickness position substantially overlaps the center in a vertical projection direction. | 12-29-2011 |
20120181541 | Thin Film Transistor Array Substrate - A thin film transistor (TFT) array substrate includes a stack structure disposed to raise an extended electrode of a drain electrode of a thin film transistor. Therefore, a contact hole does need to be very deep to expose the extended electrode of the drain electrode. | 07-19-2012 |
20120181542 | Thin Film Transistor Array Substrate - A thin film transistor (TFT) array substrate includes a stack structure disposed to raise an extended electrode of a drain electrode of a thin film transistor. Therefore, a contact hole does need to be very deep to expose the extended electrode of the drain electrode. | 07-19-2012 |
20130278853 | POLYMER STABILIZATION ALIGNMENT LIQUID CRYSTAL DISPLAY PANEL AND LIQUID CRYSTAL DISPLAY PANEL - The present invention provides a polymer stabilization alignment liquid crystal display panel having a plurality of pixel regions defined by plurals of data lines and gate lines. Each pixel region includes a main region and a sub region, and a first pixel electrode and a second pixel electrode correspond to the main region and the sub region respectively, wherein each of the data lines has a first width adjacent to the main display region and a second width adjacent to the sub display region, and the second width is larger than the first width. Each first pixel electrode is separated from the adjacent data line and thereby forming a gap therebetween. Each second pixel electrode partially overlaps the adjacent data line to form an overlap width. Accordingly, the present invention not only can increase the aperture ratio, but also well control the liquid crystal molecules located near the data lines. | 10-24-2013 |
20140342554 | METHOD FOR MANUFACTURING THIN FILM TRANSISTOR ARRAY - A thin film transistor (TFT) array includes a substrate, a thin film transistor, a first wall, a transparent electrode and a color resist. The thin film transistor is disposed on the substrate. The first wall is disposed on the substrate and separates a first contact hole from a pixel region on the substrate, wherein the first contact hole exposes a drain electrode of the thin film transistor. The first wall has a first sidewall facing towards the first contact hole and a second sidewall facing towards the pixel region, wherein the slope of the first sidewall is gentler than the slope of the second sidewall. The transparent electrode is electrically connected to the drain electrode of the thin film transistor through the first contact hole. The pixel region is filled with the color resist. | 11-20-2014 |
Patent application number | Description | Published |
20120138963 | PIXEL STRUCTURE - A pixel structure includes a substrate, a scan line, a first data line, a second data line, a first active device, a second active device, a first pixel electrode, and a second pixel electrode. The substrate has a first unit area and a second unit area. The first pixel electrode is disposed in the first unit area and includes a first main portion and first branch portions extending from the first main portion to an edge of the first unit area. The second pixel electrode is disposed in the second unit area and includes a second main portion and second branch portions extending from the second main portion to an edge of the second unit area, wherein at least a part of the first branch portions and at least a part of the second branch portions are asymmetrically arranged at two sides of the second data line. | 06-07-2012 |
20130113695 | DISPLAY DEVICE - A display device includes a first panel and a second panel stacked together. The first panel includes a first active region, a first peripheral region, a first substrate, a second substrate, a display medium, a pixel array integrated with a color filter film, a common electrode, and a first light shielding layer. The second panel includes a second active region, a second peripheral region, a third substrate, an element layer, and a second light shielding layer disposed in the second peripheral region. The first light shielding layer includes first light shielding patterns leaning against the pixel array and the common electrode and second light shielding patterns forming a black matrix in the first active region. The second light shielding patterns are shorter than the first light shielding patterns. The second active region is smaller than, the first active region. The second peripheral region is larger than the first peripheral region. | 05-09-2013 |
20140071385 | LIQUID CRYSTAL DISPLAY PANEL - A liquid crystal display (LCD) panel includes an active device array substrate, an opposite substrate, a sealant, a liquid crystal layer, a black matrix, and a plurality of rough structures. The active device array substrate has a display area and a peripheral area surrounding the display area, and the liquid crystal layer and the peripheral area are surrounded by the sealant. The black matrix is disposed between the active device array substrate and the opposite substrate and distributed corresponding to the display area and the peripheral area. The rough structures are disposed on a portion of the black matrix and distributed corresponding to the peripheral area. Surface roughness of the rough structures is greater than surface roughness of the black matrix distributed corresponding to the display area. | 03-13-2014 |
20140327864 | PIXEL STRUCTURE - A pixel structure including a substrate, a scan line, a first data line, a second data line, a first pixel unit and a second pixel unit is provided. The first pixel unit includes a first active device and a first pixel electrode. The first active device is electrically connected to the scan line and the first data line. The first pixel electrode electrically connected to the first active device and has a plurality of first branches. The first branches outwardly extend from a center of the first pixel unit, and a projection of the first branches are separated from a projection of the adjacent first data line projecting onto the substrate, and the first pixel electrode is apart from the adjacent first data line with a distance. The second pixel unit located between the first data line and the second data line. | 11-06-2014 |
20150086708 | METHOD OF PROCESSING A SUBSTRATE - A method of processing a substrate or panel is disclosed. A substrate having thereon an array of chips is provided. A mask layer is laminated on the substrate. The mask layer has a plurality of openings to reveal active areas of the chips respectively. A spray-coating process is then performed to form an adhesive film in the active areas. The mask layer is then stripped off. | 03-26-2015 |
Patent application number | Description | Published |
20100095253 | TABLE-BASED DFM FOR ACCURATE POST-LAYOUT ANALYSIS - Disclosed is a system and method for integrated circuit designs and post layout analysis. The integrated circuit design method includes providing a plurality of IC devices with various design dimensions; collecting electrical performance data of the IC devices; extracting equivalent dimensions of the IC devices; generating a shape related model to relate the equivalent dimensions to the electrical performance data of the IC devices; and creating a data refinement table using the equivalent dimensions and the electrical performance data. | 04-15-2010 |
20110289466 | Table-Based DFM for Accurate Post-Layout Analysis - Disclosed is a system and method for integrated circuit designs and post layout analysis. The integrated circuit design method includes providing a plurality of IC devices with various design dimensions; collecting electrical performance data of the IC devices; extracting equivalent dimensions of the IC devices; generating a shape related model to relate the equivalent dimensions to the electrical performance data of the IC devices; and creating a data refinement table using the equivalent dimensions and the electrical performance data. | 11-24-2011 |
20140215419 | ANALYTICAL MODEL FOR PREDICTING CURRENT MISMATCH IN METAL OXIDE SEMICONDUCTOR ARRAYS - A system and method for designing integrated circuits and predicting current mismatch in a metal oxide semiconductor (MOS) array. A first subset of cells in the MOS array is selected and current measured for each of these cells. Standard deviation of current for each cell in the first subset of cells is determined with respect to current of a reference cell. Standard deviation of local variation can be determined using the determined standard deviation of current for one or more cells in the first subset. Standard deviations of variation induced by, for example, poly density gradient effects, in the x and/or y direction of the array can then be determined and current mismatch for any cell in the array determined therefrom. | 07-31-2014 |
20140372959 | ANALYTICAL MODEL FOR PREDICTING CURRENT MISMATCH IN METAL OXIDE SEMICONDUCTOR ARRAYS - A system and method for designing integrated circuits and predicting current mismatch in a metal oxide semiconductor (MOS) array. A first subset of cells in the MOS array is selected and current measured for each of these cells. Standard deviation of current for each cell in the first subset of cells is determined with respect to current of a reference cell. Standard deviation of local variation can be determined using the determined standard deviation of current for one or more cells in the first subset. Standard deviations of variation induced by, for example, poly density gradient effects, in the x and/or y direction of the array can then be determined and current mismatch for any cell in the array determined therefrom. | 12-18-2014 |