Patent application number | Description | Published |
20120092066 | INTEGRATED CIRCUITS AND OPERATING METHODS THEREOF - An integrated circuit includes a first pass gate and a first receiver electrically coupled with the first pass gate. The first receiver includes a first N-type transistor. A first gate of the first N-type transistor is electrically coupled with the first pass gate. A first P-type bulk of the first N-type transistor is surrounded by a first N-type doped region. The first N-type doped region is surrounded by a first N-type well. The first N-type doped region has a dopant concentration higher than that of the first N-type well. | 04-19-2012 |
20120104569 | INTEGRATED CIRCUITS AND FABRICATION METHODS THEREOF - An integrated circuit includes a signal line routed in a first direction. A first shielding pattern is disposed substantially parallel with the signal line. The first shielding pattern has a first edge having a first dimension and a second edge having a second dimension. The first edge is substantially parallel with the signal line. The first dimension is larger than the second dimension. A second shielding pattern is disposed substantially parallel with the signal line. The second shielding pattern has a third edge having a third dimension and a fourth edge having a fourth dimension. The third edge is substantially parallel with the signal line. The third dimension is larger than the fourth dimension. The fourth edge faces the second edge. A first space is between the second and fourth edges. | 05-03-2012 |
20130043541 | LOW POWER/HIGH SPEED TSV INTERFACE DESIGN - A TSV interface circuit for a TSV provided in an interposer substrate that forms a connection between a first die and a second die includes a driving circuit provided in the first die and a receiver circuit provided in the second die where the driving circuit is coupled to a first supply voltage and a second supply voltage that are both lower than the interposer substrate voltage that substantially reduces the parasitic capacitance of the TSV. The receiver circuit is also coupled to the first supply voltage and the second supply voltage that are both lower than the interposer substrate voltage. | 02-21-2013 |
20130147057 | THROUGH SILICON VIA (TSV) ISOLATION STRUCTURES FOR NOISE REDUCTION IN 3D INTEGRATED CIRCUIT - Through silicon via (TSV) isolation structures are provided and suppress electrical noise such as may be propagated through a semiconductor substrate when caused by a signal carrying active TSV such as used in | 06-13-2013 |
20130162332 | INTEGRATED CIRCUITS WITH REDUCED VOLTAGE ACROSS GATE DIELECTRIC AND OPERATING METHODS THEREOF - An integrated circuit includes a first pad configured to carry a signal, a first receiver having an input node, a second receiver having an input node, a first pass gate, and a second pass gate. The first pass gate is coupled between the first pad and the input node of the first receiver. The first pass gate is configured to be turned on when the signal on the first pad is greater than a first voltage level. The second pass gate is coupled between the first pad and the input node of the second receiver. The second pass gate is configured to be turned on when the signal on the first pad is less than a second voltage level. | 06-27-2013 |
20130169339 | LEVEL SHIFTING CIRCUIT AND SEMICONDUCTOR DEVICE USING THE SAME - A level shifting circuit includes a first circuit, a second circuit and an output voltage controlling circuit. The first circuit is coupled to an input node, an output node and a first supply voltage node and configured to pull an output voltage at the output node toward the first supply voltage in accordance with an input voltage applied to the input node. The second circuit is coupled to the first circuit, the output node and the second supply voltage node and configured to pull the output voltage toward the second supply voltage in accordance with the input voltage from the first circuit. The output voltage controlling circuit is coupled to the output node and configured to control the output voltage within a range narrower than a range from the first voltage to the second voltage. | 07-04-2013 |
20130175589 | DECOUPLING CAPACITOR AND METHOD OF MAKING SAME - A semiconductor substrate has at least two active regions, each having at least one active device that includes a gate electrode layer, and a shallow trench isolation (STI) region between the active regions. A decoupling capacitor comprises first and second dummy conductive patterns formed in the same gate electrode layer over the STI region. The first and second dummy conductive regions are unconnected to any of the at least one active device. The first dummy conductive pattern is connected to a source of a first potential. The second dummy conductive pattern is connected to a source of a second potential. A dielectric material is provided between the first and second dummy conductive patterns. | 07-11-2013 |
20130181269 | DECOUPLING CAPACITOR AND METHOD OF MAKING SAME - A device comprises a semiconductor substrate having first and second implant regions and an electrode above and between the first and second implant regions of a first dopant type. A contact structure is in direct contact with the first and second implant regions and the electrode. A third implant region has a second dopant type different from the first dopant type. A bulk contact is provided on the third implant. | 07-18-2013 |
20130185689 | METHOD OF AND SYSTEM FOR GENERATING OPTIMIZED SEMICONDUCTOR COMPONENT LAYOUT - A method of generating an optimized layout of semiconductor components in conformance with a set of design rules includes generating, for a unit cell including one or more semiconductor components, a plurality of configurations each of which satisfies some, but not all, of the design rules. For each configuration, it is checked whether a layout, which is a repeating pattern of the unit cell, satisfies the remaining design rules. Among the configurations which satisfy all of the design rules, the configuration providing an optimal value of a property is selected for generating the optimized layout of the semiconductor components. | 07-18-2013 |
20130193499 | DECOUPLING CAPACITOR AND LAYOUT FOR THE CAPACITOR - A device comprises a semiconductor substrate having first and second implant regions of a first dopant type. A gate insulating layer and a gate electrode are provided above a resistor region between the first and second implant regions. A first dielectric layer is on the first implant region. A contact structure is provided, including a first contact portion conductively contacting the gate electrode, at least part of the first contact portion directly on the gate electrode. A second contact portion directly contacts the first contact portion and is formed directly on the first dielectric layer. A third contact portion is formed on the second implant region. | 08-01-2013 |
20130193500 | DECOUPLING FINFET CAPACITORS - A semiconductor device including field-effect transistors (finFETs) and fin capacitors are formed on a silicon substrate. The fin capacitors include silicon fins, one or more electrical conductors between the silicon fins, and insulating material between the silicon fins and the one or more electrical conductors. The fin capacitors may also include insulating material between the one or more electrical conductors and underlying semiconductor material. | 08-01-2013 |
20130198710 | SEMICONDUCTOR DEVICE FEATURE DENSITY GRADIENT VERIFICATION - A method for verifying that acceptable device feature gradients and device feature disparities are present in a semiconductor device layout, is provided. The method provides for dividing a device layout into a plurality of windows and measuring or otherwise determining the device feature density within each window. The device layout includes various device regions and the method provides for comparing an average device feature density within one region to surrounding areas or other regions and also for determining gradients of device feature densities. The gradients may be monitored from within a particular device region to surrounding regions. Instructions for carrying out the method may be stored on a computer readable storage medium and executed by a processor. | 08-01-2013 |
20130200449 | FINFET STRUCTURE WITH NOVEL EDGE FINS - A semiconductor device including field-effect transistors (finFETs) formed on a silicon substrate. The device includes a number of active areas each having a number of equally-spaced fins separated into regular fins and at least one edge fin, a gate structure over the regular fins, and a drain region as well as a source region electrically connected to the regular fins and disconnected to the at least one edge fin. The edge fins may be floating, connected to a potential source, or serve as a part of a decoupling capacitor. | 08-08-2013 |
20130307516 | BANDGAP REFERENCE CIRCUIT - A bandgap reference circuit including two sets of bipolar junction transistors (BJTs). A first set of two or more BJTs configured to electrically connect in a parallel arrangement. The first set of BJTs is configured to produce a first proportional to absolute temperature (PTAT) signal. A second set of two or more BJTs configured to electrically connect in a parallel arrangement. The second set of BJTs is configured to produce a second PTAT signal. A circuitry configured to electrically connect to the first set of BJTs and the second set of BJTs. The circuitry is configured to combine the first PTAT signal and the second PTAT signal to produce a reference voltage. | 11-21-2013 |
20130328162 | HOMO-JUNCTION DIODE STRUCTURES USING FIN FIELD EFFECT TRANSISTOR PROCESSING - Diodes and bipolar junction transistors (BJTs) are formed in IC devices that include fin field-effect transistors (FinFETs) by utilizing various process steps in the FinFET formation process. The diode or BJT includes an isolated fin area and fin array area having n-wells having different depths and a p-well in a portion of the fin array area that surrounds the n-well in the isolated fin area. The n-wells and p-well for the diodes and BJTs are implanted together with the FinFET n-wells and p-wells. | 12-12-2013 |
20130328614 | DEVICE LAYOUT FOR REFERENCE AND SENSOR CIRCUITS - A band gap reference circuit includes an error-amplifier-based current mirror coupled between a first supply node and a pair of intermediate voltage nodes, and a matched diode pair for providing a proportional-to-absolute temperature (PTAT) current. The matched diode pair includes a first diode connected between a first intermediate voltage node from the pair of intermediate voltage nodes and a second supply node, and a second diode connected in series with a resistor between a second intermediate voltage node from the pair of intermediate voltage nodes and the second supply node. Each diode has a P-N diode junction that is a homojunction. | 12-12-2013 |
20130334646 | METALLIC THERMAL SENSOR FOR IC DEVICES - A thermal sensor for use in an IC device is formed of a plurality of metal resistor units connected in series where each of the plurality of metal resistor units are formed on different wiring layers of the IC device connected by via segments and the metal resistor units are in a superimposed alignment with each other forming a stack. | 12-19-2013 |
20130346935 | SEMICONDUCTOR DEVICE FEATURE DENSITY GRADIENT VERIFICATION - A method for verifying that acceptable device feature gradients and device feature disparities are present in a semiconductor device layout, is provided. The method provides for dividing a device layout into a plurality of windows and measuring or otherwise determining the device feature density within each window. The device layout includes various device regions and the method provides for comparing an average device feature density within one region to surrounding areas or other regions and also for determining gradients of device feature densities. The gradients may be monitored from within a particular device region to surrounding regions. Instructions for carrying out the method may be stored on a computer readable storage medium and executed by a processor. | 12-26-2013 |
20140077230 | DEVICE LAYOUT FOR REFERENCE AND SENSOR CIRCUITS - A band gap reference circuit includes an error-amplifier-based current mirror coupled between a first supply node and a pair of intermediate voltage nodes, and a matched diode pair for providing a proportional-to-absolute temperature (PTAT) current. The matched diode pair includes a first diode connected between a first intermediate voltage node from the pair of intermediate voltage nodes and a second supply node, and a second diode connected in series with a resistor between a second intermediate voltage node from the pair of intermediate voltage nodes and the second supply node. Each diode has a P-N diode junction that is a homojunction. | 03-20-2014 |
20140077331 | DIODE STRUCTURES USING FIN FIELD EFFECT TRANSISTOR PROCESSING AND METHOD OF FORMING THE SAME - A method of forming one or more diodes in a fin field-effect transistor (FinFET) device includes forming a hardmask layer having a fin pattern, said fin pattern including an isolated fin area, a fin array area, and a FinFET area. The method further includes etching a plurality of fins into a semiconductor substrate using the fin pattern, and depositing a dielectric material over the semiconductor substrate to fill spaces between the plurality of fins. The method further includes planarizing the semiconductor substrate to expose the hardmask layer. The method further includes implanting a p-type dopant into the fin array area and portions of the FinFET area, and implanting an n-type dopant into the isolated fin area, a portion of the of fin array area surrounding the p-well and portions of the FinFET area. The method further includes annealing the semiconductor substrate. | 03-20-2014 |
20140159195 | DECOUPLING CAPACITOR AND METHOD OF MAKING SAME - A semiconductor substrate has at least two active regions, each having at least one active device that includes a gate electrode layer, and a shallow trench isolation (STI) region between the active regions. A decoupling capacitor comprises first and second dummy conductive patterns formed in the same gate electrode layer over the STI region. The first and second dummy conductive regions are unconnected to any of the at least one active device. The first dummy conductive pattern is connected to a source of a first potential. The second dummy conductive pattern is connected to a source of a second potential. A dielectric material is provided between the first and second dummy conductive patterns. | 06-12-2014 |
20140239450 | GUARD STRUCTURE FOR SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING GUARD LAYOUT PATTERN FOR SEMICONDUCTOR LAYOUT PATTERN - A guard structure for a semiconductor structure is provided. The guard structure includes a first guard ring, a second guard ring and a third guard ring. The first guard ring has a first conductivity type. The second guard ring has a second conductivity type, and surrounds the first guard ring. The third guard ring has the first conductivity type, and surrounds the second guard ring, wherein the first, the second and the third guard rings are grounded. A method of forming a guard layout pattern for a semiconductor layout pattern is also provided. | 08-28-2014 |
20140327119 | INTEGRATED CIRCUIT HAVING SHIELDING STRUCTURE - An integrated circuit includes a signal line and a plurality of shielding structures. The signal line is routed along a first direction and is in a first metallization layer. Each shielding structure includes a plurality of non-contiguous shielding patterns aligned along the first direction. The plurality of shielding structures includes a first and a second shielding structures in a second metallization layer that adjoins the first metallization layer and a third and a fourth shielding structures in a third metallization layer that adjoins the first metallization layer. The first metallization layer is between the second and the third metallization layers. The first and the second shielding structures are separated from each other along a second direction perpendicular to the first direction. The third and the fourth shielding structures are separated from each other along the second direction. | 11-06-2014 |
20140368264 | TEMPERATURE/VOLTAGE DETECTION CIRCUIT - A circuit includes a comparator unit, a capacitive device, and a switching network. The comparator unit is configured to set a control signal at a first logical value when an output voltage reaches a first voltage value from being less than the first voltage value, and to set the control signal at a second logical value when the output voltage reaches a second voltage value from being greater than the second voltage. The capacitive device provides the output voltage. The switching network is configured to charge or discharge the capacitive device based on the control signal. | 12-18-2014 |
20140369381 | THERMAL SENSOR - A circuit includes a comparator unit and a switching network. The comparator unit is configured to receive a first voltage value, a second voltage value and a third voltage value of a voltage node, and to provide a control signal. The switching network includes the voltage node and is configured to operate in a first condition or in a second condition based on the control signal. Based on the first condition, the voltage node is configured to have a voltage value increase to the first voltage value. Based on a second condition, the voltage node is configured to have a voltage decrease to the second voltage | 12-18-2014 |
20150115717 | MOS-BASED VOLTAGE REFERENCE CIRCUIT - A voltage reference circuit is provided that includes a first circuit, a second circuit and a third circuit. The first circuit has a first MOS transistor pair and the second circuit has a second MOS transistor pair. The first circuit is configured to provide a first voltage component that changes at a first rate having a first slope as a temperature to which the voltage reference circuit is subjected changes. The second circuit is configured to provide a second voltage component that changes at a second rate having a second slope as the temperature changes. The third circuit is configured to use the first voltage component and the second voltage component to generate the reference voltage component that changes at a fifth rate having a fifth slope as the temperature changes. The fifth slope is substantially equal to zero to promote insensitivity of the reference voltage component to temperature changes. | 04-30-2015 |