Patent application number | Description | Published |
20080248624 | METHOD OF MAKING INTEGRATED CIRCUIT (IC) INCLUDING AT LEAST ONE STORAGE CELL - A storage cell, integrated circuit (IC) chip with one or more storage cells that may be in an array of the storage cells and a method of forming the storage cell and IC. Each storage cell includes a stylus, the tip of which is phase change material. The phase change tip may be sandwiched between an electrode and conductive material, e.g., titanium nitride (TiN), tantalum nitride (TaN) or n-type semiconductor. The phase change layer may be a chalcogenide and in particular a germanium (Ge), antimony (Sb), tellurium (Te) (GST) layer. | 10-09-2008 |
20080251778 | FOUR-TERMINAL PROGRAMMABLE VIA-CONTAINING STRUCTURE AND METHOD OF FABRICATING SAME - A semiconductor structure that includes two programmable vias each of which contains a phase change material that is integrated with a heating material. In particular, the present invention provides a structure in which two programmable vias, each containing a phase change material, are located on opposing surfaces of a heating material. Each end portion of an upper surface of the heating material is connected to a metal terminal. These metal terminals, which are in contact with the end portions of the upper surface of the heating material, can be each connected to an outside component that controls and switches the resistance states of the two programmable vias. The two programmable vias of the inventive structure are each connected to another metal terminal. These metal terminals that are associated with the programmable vias can be also connected to a circuit block that may be present in the structure. | 10-16-2008 |
20080277644 | SWITCH ARRAY CIRCUIT AND SYSTEM USING PROGRAMMABLE VIA STRUCTURES WITH PHASE CHANGE MATERIALS - The present invention provides at least one programmable via structure that includes at least two phase change material vias that are both directly contacting a heating element, the programmable via structure further including a first terminal in contact with a first portion of the heating element, a second terminal in contact with a second portion of the heating element, a third terminal in contact with one of the at least two programmable vias, and a fourth terminal in contact with another one of the at least two programmable vias; a first circuit block in contact with one of the third and fourth terminals; a second circuit block in contact with the third or fourth terminal not contacting the first circuit block; a source region of a first field effect transistor in contact with one of the first and second terminals; and a drain region of a second field effect transistor in contact with the first or second terminal that is not contacting the source region of the first field effect transistor. A method of operating the at least one programmable via structure is also provided. | 11-13-2008 |
20080286905 | Fin-Type Antifuse - A method of forming an antifuse forms a material layer and then patterns the material layer into a fin. The center portion of the fin is converted into a substantially non-conductive region and the end portions of the fin into conductors. The process of converting the center portion of the fin into an insulator allows a process of heating the fin above a predetermined temperature to convert the insulator into a conductor. Thus, the fin-type structure that can be selectively converted from an insulator into a permanent conductor using a heating process. | 11-20-2008 |
20080299731 | ERASEABLE NONVOLATILE MEMORY WITH SIDEWALL STORAGE - A nonvolatile storage cell, integrated circuit (IC) including the cells and method of manufacturing the cells. A layered spacer (ONO) is formed at least at one sidewall of cell gates. Source/drain diffusions at each layered spacer underlap the adjacent gate. Charge may be stored at a layer (an imbedded nitride layer) in the layered spacer. | 12-04-2008 |
20090013146 | METHOD TO CREATE A UNIFORMLY DISTRIBUTED MULTI-LEVEL CELL (MLC) BITSTREAM FROM A NON-UNIFORM MLC BITSTREAM - A method, system, and computer software product for operating a collection of memory cells. Each memory cell in the collection of memory cells is configured to store a binary multi-bit value delimited by characteristic parameter bands. In one embodiment, a transforming unit transforms an original collection of data to a transformed collection of data using a reversible mathematical operator. The original collection of data has binary multi-bit values arbitrarily distributed across the binary multi-bit values assigned to the characteristic parameter bands and the transformed collection of data has binary multi-bit values substantially uniformly distributed across the binary multi-bit values assigned to the characteristic parameter bands. | 01-08-2009 |
20090013223 | MULTI-BIT ERROR CORRECTION SCHEME IN MULTI-LEVEL MEMORY STORAGE SYSTEM - A method, system, and computer software product for operating a collection of memory cells. Memory cells are organized into a group of memory cells, with each memory cell storing a binary multi-bit value delimited by characteristic parameter bands. Two adjacent characteristic parameter bands are assigned binary multi-bit values that differ by only one bit. In one embodiment, an error correction unit calculates an actual parity check value of the retrieved binary multi-bit values for the group of memory cells. If the actual parity check value is not equal to the expected parity check value, the error correction unit assigns the error memory cell a corrected binary multi-bit value with the characteristic parameter value within the characteristic parameter band adjacent to the characteristic parameter band associated with the retrieved binary multi-bit value such that calculating a second actual parity check value correctly indicates the parity for the group of memory cells. | 01-08-2009 |
20090013231 | Multi-bit error correction scheme in multi-level memory storage system - A method, system, and computer software product for operating a memory cell collection. Memory cells in the collection store binary multi-bit values delimited by characteristic parameter bands of a characteristic parameter. In one embodiment, a comparing unit compares a retrieved count and a stored count for each binary multi-bit value. The retrieved count, equal to the number of occurrences the binary multi-bit value, is retrieved from the memory cell collection. The stored count, equal to the number of occurrences the binary multi-bit value, is stored in the memory cell collection. An error correction unit then assigns the error memory cell(s) a corrected binary multi-bit value with the characteristic parameter value within the characteristic parameter band adjacent to the characteristic parameter band associated with the retrieved binary multi-bit value such that the retrieved count of each binary multi-bit value is equal to the stored count of each binary multi-bit value. | 01-08-2009 |
20090039331 | PHASE CHANGE MATERIAL STRUCTURES - Structures including a phase change material are disclosed. The structure may include a first electrode; a second electrode; a phase change material electrically connecting the first electrode and the second electrode for passing a current therethrough; and a tantalum nitride heater layer about the phase change material for converting the phase change material between an amorphous, insulative state and a crystalline, conductive state by application of a second current to the phase change material. The structure may be used as a fuse or a phase change material random access memory (PRAM). | 02-12-2009 |
20090045388 | PHASE CHANGE MATERIAL STRUCTURE AND RELATED METHOD - A structure including a phase change material and a related method are disclosed. The structure may include a first electrode; a second electrode; a third electrode; a phase change material electrically connecting the first, second and third electrodes for passing a first current through two of the first, second and third electrodes; and a refractory metal barrier heater layer about the phase change material for converting the phase change material between an amorphous, insulative state and a crystalline, conductive state by application of a second current to the phase change material. The structure may be used as a fuse or a phase change material random access memory (PRAM). | 02-19-2009 |
20090073783 | MULTI-LEVEL MEMORY CELL UTILIZING MEASUREMENT TIME DELAY AS THE CHARACTERISTIC PARAMETER FOR LEVEL DEFINITION - A memory array and computer program product for operating a memory cell and memory array. An embodiment of the invention entails receiving a request to read a binary value stored in the memory cell. A pre-charging operation pre-charges a bit-line capacitor in an electronic circuit formed by the memory cell to a pre-charge voltage. A word-line in the electronic circuit is then activated. A discharging operation discharges the bit-line capacitor through the said memory cell in the electronic circuit to the word-line. Additionally, an electron discharge time measurement is started when the word-line is activated. The electron discharge time measurement is stopped when the voltage level in the bit-line falls below a pre-defined reference voltage. A determining operation determines the binary value from the measured electron discharge time. | 03-19-2009 |
20090073784 | MULTI-LEVEL MEMORY CELL UTILIZING MEASUREMENT TIME DELAY AS THE CHARACTERISTIC PARAMETER FOR LEVEL DEFINITION - A memory array and computer program product for operating a memory cell and memory array. An embodiment of the invention entails receiving a binary value to be stored by a memory cell. A determining operation determines a target discharge time corresponding to the binary value. The target discharge time being the time needed to discharge a pre-charged circuit through the said memory cell to a predetermined level. A storing operation stores a characteristic parameter in the memory cell such that an electron discharge time through an electronic circuit formed, at least partially, by the memory cell, is substantially equal to the target discharge time. | 03-19-2009 |
20090073790 | MULTI-LEVEL MEMORY CELL UTILIZING MEASUREMENT TIME DELAY AS THE CHARACTERISTIC PARAMETER FOR LEVEL DEFINITION - A method for operating a memory cell and memory array. The method of memory cell operation entails receiving a request to read a binary value stored in the memory cell. A pre-charging operation pre-charges a bit-line capacitor in an electronic circuit formed by the memory cell to a pre-charge voltage. A word-line in the electronic circuit is then activated. A discharging operation discharges the bit-line capacitor through the said memory cell in the electronic circuit to the word-line. Additionally, an electron discharge time measurement is started when the word-line is activated. The electron discharge time measurement is stopped when the voltage level in the bit-line falls below a pre-defined reference voltage. A determining operation determines the binary value from the measured electron discharge time. | 03-19-2009 |
20090111228 | SELF ALIGNED RING ELECTRODES - The present invention in one embodiment provides a method of manufacturing an electrode that includes providing at least one metal stud positioned in a via extending into a first dielectric layer, wherein an electrically conductive liner is positioned between at least a sidewall of the via and the at least one metal stud; recessing an upper surface of the at least one metal stud below an upper surface of the first dielectric layer to provide at least one recessed metal stud; and forming a second dielectric atop the at least one recessed metal stud, wherein an upper surface of the electrically conductive liner is exposed. | 04-30-2009 |
20090173928 | POLYSILICON EMITTER BJT ACCESS DEVICE FOR PCRAM - A resistive non-volatile memory cell with a bipolar junction transistor (BJT) access device formed in conjunction with the entire memory cell. The memory cell includes a substrate acting as a collector, a semiconductor base layer acting as a base, and a semiconductor emitter layer acting as an emitter. Additionally, metal plugs and the phase change memory element are formed above the BJT access device while the emitter, metal plugs, and phase change memory element are contained within an insulating region. In one embodiment of the invention, a spacer layer is formed and the emitter layer is contained within the protective spacer layer. The spacer layer is contained within the insulating region. | 07-09-2009 |
20090186485 | SUB-LITHOGRAPHIC PRINTING METHOD - A method to form sub-lithographic trench structures in a substrate and an integrated circuit comprising sub-lithographic trench structures in a substrate. The method includes forming sets of trenches with a lithographic mask and filling the sets of trenches with sets of step spacer blocks comprising two alternating spacer materials which are separately removable from each other. In one embodiment, the trench structures formed are one-nth the thickness of the lithographic mask's feature size. The size of the trench structures being dependent on the thickness and number of spacer material layers used to form the set of step spacer blocks. The number of spacer material layers being n/2 and the thickness of each spacer material layer being one-nth of the lithographic mask's feature size. | 07-23-2009 |
20090189139 | PORE PHASE CHANGE MATERIAL CELL FABRICATED FROM RECESSED PILLAR - A method of manufacturing an electrode is provided that includes providing a pillar of a first phase change material atop a conductive structure of a dielectric layer; or the inverted structure; forming an insulating material atop dielectric layer and adjacent the pillar, wherein an upper surface of the first insulating material is coplanar with an upper surface of the pillar; recessing the upper surface of the pillar below the upper surface of the insulating material to provide a recessed cavity; and forming a second phase change material atop the recessed cavity and the upper surface of the insulating material, wherein the second phase change material has a greater phase resistivity than the first phase change material. | 07-30-2009 |
20090189731 | CROSS POINT SWITCH USING PHASE CHANGE MATERIAL - A cross-point switch and cross-point switch fabric utilizing phase change material, and method of operating the same. The cross-point switch includes a phase change cross-point circuit containing a plurality of terminal nodes connected to a central node. The connections between the terminal nodes and the central nodes are regulated by phase change switches comprised of a phase change material. The phase change switches being controlled by heating elements capable of melting or crystallizing the phase change material in the phase change switch. The heating elements are operated by a separate heating circuit. Each individual heating element is regulated by an individual transistor. | 07-30-2009 |
20090194757 | PHASE CHANGE ELEMENT EXTENSION EMBEDDED IN AN ELECTRODE - The present invention in one embodiment provides a method of forming a memory device that includes providing an interlevel dielectric layer including a conductive stud having a first width; forming an stack comprising a metal layer and a first insulating layer; forming a second insulating layer atop portions of the interlevel dielectric layer adjacent each sidewall of the stack; removing the first insulating layer to provide a cavity; forming a conformal insulating layer atop the second insulating layer and the cavity; applying an anisotropic etch step to the conformal insulating layer to produce a opening having a second width exposing an upper surface of the metal layer, wherein the first width is greater than the second width; and forming a memory material layer in the opening. | 08-06-2009 |
20090212272 | SELF-CONVERGING BOTTOM ELECTRODE RING - A method and memory cell including self-converged bottom electrode ring. The method includes forming a step spacer, a top insulating layer, an intermediate insulating layer, and a bottom insulating layer above a substrate. The method includes forming a step spacer within the top insulating layer and the intermediate insulating layer. The step spacer size is easily controlled. The method also includes forming a passage in the bottom insulating layer with the step spacer as a mask. The method includes forming bottom electrode ring within the passage comprising a cup-shaped outer conductive layer within the passage and forming an inner insulating layer within the cup-shaped outer conductive layer. The method including forming a phase change layer above the bottom electrode ring and a top electrode above the bottom electrode ring. | 08-27-2009 |
20090212274 | PHASE CHANGE MEMORY RANDOM ACCESS DEVICE USING SINGLE-ELEMENT PHASE CHANGE MATERIAL - A phase change memory cell with a single element phase change thin film layer; and a first electrode and a second electrode coupled to the single element phase change thin film layer. A current flows from the first electrode to the single element phase change thin film layer, and through to the second electrode. The single element phase change thin film layer includes a single element phase change material. The single element phase change thin film layer can be less than 5 nanometers thick. The temperature of crystallization of the single element phase change material can be controlled by its thickness. In one embodiment, the single element phase change thin film layer is configured to be amorphous at room temperature (25 degrees Celsius). In one embodiment, the single element phase change thin film layer is comprised of Antimony (Sb). | 08-27-2009 |
20090230377 | Phase Change Materials for Applications that Require Fast Switching and High Endurance - A memory device utilizing a phase change material as the storage medium, the phase change material based on antimony as the solvent in a solid solution; wherein the memory device further includes a means for heating the phase change material. | 09-17-2009 |
20090268507 | PHASE CHANGE MEMORY DEVICE AND METHOD OF MANUFACTURE - A phase change memory control ring lower electrode is disclosed. The lower electrode includes an outer ring electrode in thermal contact with a phase change memory element, an inner seed layer disposed within the outer ring electrode and in contact with the phase change memory element, and an electrically conductive bottom layer coupled to the outer ring electrode. | 10-29-2009 |
20090275168 | PHASE CHANGE MATERIAL WITH FILAMENT ELECTRODE - The present invention, in one embodiment, provides a memory device that includes a phase change memory cell; a first electrode; and a layer of filamentary resistor material positioned between the phase change memory cell and the first electrode, wherein at least one bistable conductive filamentary pathway is present in at least a portion of the layer of filamentary resistor material that provides electrical communication between the phase change memory cell and the first electrode. | 11-05-2009 |
20090294850 | METHOD TO TAILOR LOCATION OF PEAK ELECTRIC FIELD DIRECTLY UNDERNEATH AN EXTENSION SPACER FOR ENHANCED PROGRAMMABILITY OF A PROMPT-SHIFT DEVICE - The invention provides a method to enhance the programmability of a prompt-shift device, which reduces the programming time to sub-millisecond times, by altering the extension and halo implants, instead of simply omitting the same from one side of the device as is the case in the prior art prompt-shift devices. The invention includes an embodiment in which no additional masks are employed, or one additional mask is employed. The altered extension implant is performed at a reduced ion dose as compared to a conventional extension implant process, while the altered halo implant is performed at a higher ion dose than a conventional halo implant. The altered halo/extension implant shifts the peak of the electrical field to under an extension dielectric spacer. | 12-03-2009 |
20090298223 | SELF-ALIGNED IN-CONTACT PHASE CHANGE MEMORY DEVICE - A memory cell and a method of making the same, that includes insulating material deposited on a substrate, a bottom electrode formed within the insulating material, a plurality of insulating layers deposited above the bottom electrode and at least one of which acts as an intermediate insulating layer. Then defining a via in the insulating layers above the intermediate insulating layer, creating a channel for etch with a step spacer, defining a pore in the intermediate insulating layer, removing all insulating layers above the intermediate insulating layer, filling the entirety of the pore with phase change material, and forming an upper electrode above the phase change material. Additionally, the formation of bit line connections with the upper electrode. | 12-03-2009 |
20090303786 | SWITCH ARRAY CIRCUIT AND SYSTEM USING PROGRAMMABLE VIA STRUCTURES WITH PHASE CHANGE MATERIALS - The present invention provides at least one programmable via structure that includes at least two phase change material vias that are both directly contacting a heating element, the programmable via structure further including a first terminal in contact with a first portion of the heating element, a second terminal in contact with a second portion of the heating element, a third terminal in contact with one of the at least two programmable vias, and a fourth terminal in contact with another one of the at least two programmable vias; a first circuit block in contact with one of the third and fourth terminals; a second circuit block in contact with the third or fourth terminal not contacting the first circuit block; a source region of a first field effect transistor in contact with one of the first and second terminals; and a drain region of a second field effect transistor in contact with the first or second terminal that is not contacting the source region of the first field effect transistor. A method of operating the at least one programmable via structure is also provided. | 12-10-2009 |
20090305492 | VERTICAL FIELD EFFECT TRANSISTOR ARRAYS AND METHODS FOR FABRICATION THEREOF - Vertical field effect transistor semiconductor structures and methods for fabrication of the vertical field effect transistor semiconductor structures provide an array of semiconductor pillars. Each vertical portion of each semiconductor pillar in the array of semiconductor pillars has a linewidth greater than a separation distance to an adjacent semiconductor pillar. Alternatively, the array may comprise semiconductor pillars with different linewidths, optionally within the context of the foregoing linewidth and separation distance limitations. A method for fabricating the array of semiconductor pillars uses a minimally photolithographically dimensioned pillar mask layer that is annularly augmented with at least one spacer layer prior to being used as an etch mask. | 12-10-2009 |
20090305508 | INTEGRATED CIRCUIT WITH UPSTANDING STYLUS - A stylus, an integrated circuit (IC) and method of forming the IC. The stylus extends upward from its apex and has a substantially circular cross section that decreases in diameter upward from the apex. The stylus is formed in a mold that may be formed in an orifice in a dielectric layer between wiring layers. The mold may include multiple concentric layers. For a more pronounced, non-linear stylus taper, each layer may be thinner than its next adjacent outer concentric layer. | 12-10-2009 |
20090311858 | PROGRAMMABLE VIA STRUCTURE AND METHOD OF FABRICATING SAME - A programmable via structure is provided as well as a method of fabricating the same. The inventive programmable via a semiconductor substrate. An oxide layer such as a thermal oxide is located on a surface of the semiconductor substrate. A patterned heating material is located on a surface of the oxide layer. The inventive structure also includes a patterned dielectric material having a least one via filled with a phase change material (PCM). The patterned dielectric material including the PCM filled via is located on a surface of the patterned heating material. A patterned diffusion barrier is located on an exposed surface of said at least one via filled with the phase change material. The inventive structure also includes contact vias that extend through the patterned dielectric material. The contact vias are filled with a conductive material which also extends onto the upper surface of the patterned dielectric material. A conductive material which serves as the input of the device is located atop the patterned diffusion barrier that is located directly above the via that is filled with the phase change material. | 12-17-2009 |
20100002481 | CONTENT ADDRESSABLE MEMORY USING PHASE CHANGE DEVICES - Content addressable memory device utilizing phase change devices. An aspect of the content addressable memory device is the use of a comparatively lower power search-line access element and a comparatively higher power word-line access element. The word-line access element is only utilized during write operations and the search-line access element is only utilized during search operations. The word-line access element being electrically coupled to a second end of a phase change memory element and a word-line. The search-line access element also being electrically coupled to the second end of the phase change memory element and a search-line. The search-line being electrically coupled to a match-line. A bit-line is electrically coupled to a first end of the phase change memory element. Additionally, a complementary set of access elements, a complementary phase change memory element, a complementary search-line, and a complementary bit-line are also included in the content addressable memory device. | 01-07-2010 |
20100002499 | PHASE CHANGE MEMORY PROGRAMMING METHOD WITHOUT RESET OVER-WRITE - A method for programming a phase change memory device that avoids RESET overwrite. The method partially comprised of applying a reset write current pulse through the phase change memory element such that the reset write current pulse produces a voltage drop across the phase change memory element less than a reset threshold voltage and greater than a set threshold voltage. The reset write current pulse writing a RESET state to the phase change memory cell. The method additionally comprised of applying a set write current pulse through the phase change memory element such that the set write current pulse produces a voltage drop across the phase change memory element that is equal to or greater than the reset threshold voltage. The set write current pulse writing a SET state to the phase change memory cell. | 01-07-2010 |
20100048020 | Nanoscale Electrodes for Phase Change Memory Devices - A process for preparing a phase change memory semiconductor device comprising a (plurality of) nanoscale electrode(s) for alternately switching a chalcogenide phase change material from its high resistance (amorphous) state to its low resistance (crystalline) state, whereby a reduced amount of current is employed, and wherein the plurality of nanoscale electrodes, when present, have substantially the same dimensions. | 02-25-2010 |
20100078617 | METHOD TO REDUCE A VIA AREA IN A PHASE CHANGE MEMORY CELL - A memory cell structure and method to form such structure. The method partially comprised of forming a via within an oxidizing layer, over the center of a bottom electrode. The method includes depositing a via spacer along the sidewalls of the via and oxidizing the via spacer. The via spacer being comprised of a material having a Pilling-Bedworth ratio of at least one and one-half and is an insulator when oxidized. The via area is reduced by expansion of the via spacer during the oxidation. Alternatively, the method is partially comprised of forming a via within a first layer, over the center of the bottom electrode. The first layer has a Pilling-Bedworth ratio of at least one and one-half and is an insulator when oxidized. The method also includes oxidizing at least a portion of the sidewalls of the via in the first layer. | 04-01-2010 |
20100078621 | METHOD TO REDUCE RESET CURRENT OF PCM USING STRESS LINER LAYERS - A memory cell structure and method for forming the same. The method includes forming a via within a dielectric layer. The via is formed over the center of an electrically conducting bottom electrode. The method includes depositing a stress liner along at least one sidewall of the via. The stress liner imparting stress on material proximate the stress liner. In one embodiment, the stress liner provides a stress in the range of 500 to 5000 MPa on the material enclosed within its volume. The method includes depositing phase change material within the via and the volume enclosed by the stress liner. The method also includes forming an electrically conducting top electrode above the phase change material. | 04-01-2010 |
20100135085 | MULTI-LEVEL MEMORY CELL UTILIZING MEASUREMENT TIME DELAY AS THE CHARACTERISTIC PARAMETER FOR LEVEL DEFINITION - A computer program product for operating a memory cell and memory array. The computer program product of memory cell operation entails receiving a request to read a binary value stored in the memory cell. A pre-charging operation pre-charges a bit-line capacitor in an electronic circuit formed by the memory cell to a pre-charge voltage. A word-line in the electronic circuit is then activated. A discharging operation discharges the bit-line capacitor through the said memory cell in the electronic circuit to the word-line. Additionally, an electron discharge time measurement is started when the word-line is activated. The electron discharge time measurement is stopped when the voltage level in the bit-line falls below a pre-defined reference voltage. A determining operation determines the binary value from the measured electron discharge time. | 06-03-2010 |
20100176362 | POLYSILICON PLUG BIPOLAR TRANSISTOR FOR PHASE CHANGE MEMORY - Memory devices and methods for manufacturing are described herein. A memory device described herein includes a plurality of memory cells. Memory cells in the plurality of memory cells comprise respective bipolar junction transistors and memory elements. The bipolar junction transistors are arranged in a common collector configuration and include an emitter comprising doped polysilicon having a first conductivity type, the emitter contacting a corresponding word line in a plurality of word lines to define a pn junction. The bipolar junction transistors include a portion of the corresponding word line underlying the emitter acting as a base, and a collector comprising a portion of the single-crystalline substrate underlying the base. | 07-15-2010 |
20100181649 | POLYSILICON PILLAR BIPOLAR TRANSISTOR WITH SELF-ALIGNED MEMORY ELEMENT - Memory cells having memory elements self-aligned with the emitters of bipolar junction transistor access devices are described herein, as well as methods for manufacturing such devices. A memory device as described herein comprises a plurality of memory cells. Memory cells in the plurality of memory cells include a bipolar junction transistor comprising an emitter comprising a pillar of doped polysilicon. The memory cells include an insulating element over the emitter and having an opening extending through the insulating layer, the opening centered over the emitter. The memory cells also include a memory element within the opening and electrically coupled to the emitter. | 07-22-2010 |
20100214811 | CODING TECHNIQUES FOR IMPROVING THE SENSE MARGIN IN CONTENT ADDRESSABLE MEMORIES - A content addressable memory using encoded data words and search words, and techniques for operating such device. In one embodiment, the data word is transformed into a code word guaranteeing a mismatch of at least two code word bits of different binary values during the memory search operation when the data word does not match a search word. In another embodiment, the search word is transformed into a search code such that the Hamming distance between the code word and the search code is greater than a given threshold when there is a mismatch of at least one bit between the data word and the search word. | 08-26-2010 |
20100226161 | TERNARY CONTENT ADDRESSABLE MEMORY USING PHASE CHANGE DEVICES - A content addressable memory device with a plurality of memory cells storing ternary data values of high, low, and don't care. An aspect of the content addressable memory device is the use of first memory elements and second memory elements in the memory cells. The first and second memory elements are electrically coupled in parallel circuit to a match-line. The first memory elements are coupled to first word-lines and the second memory elements are coupled to second word-lines. The first memory elements are configured to store low resistance states if the ternary data value is low and high resistance states if the ternary data value is either high or don't care. The second memory elements are configured to store the low resistance states if the ternary data value is high and the high resistance states if the ternary data value is either low or don't care. | 09-09-2010 |
20100265748 | HIGH DENSITY TERNARY CONTENT ADDRESSABLE MEMORY - A content addressable memory device with a plurality of memory cells storing data words. Each data bit in the data words is set to one of three values of a first binary value, a second binary value, and a don't care value. An aspect of the content addressable memory device is the use of a single memory element and an access device in the memory cells. The memory cells are arranged such that each memory cell is electrically coupled to a single bit line, a single match line, and a single word line. The memory elements in the memory cells store low resistance states if the data bit value is the first binary value, high resistance states if the data bit value is the second binary value, and very high resistance states if the data bit value is the don't care value. | 10-21-2010 |
20100295009 | Phase Change Memory Cells Having Vertical Channel Access Transistor and Memory Plane - Memory devices are described along with methods for manufacturing. A memory device as described herein comprises a plurality of word lines overlying a plurality of bit lines, and a plurality of field effect transistors. Field effect transistors in the plurality of field effect transistors comprises a first terminal electrically coupled to a corresponding bit line in the plurality of bit lines, a second terminal overlying the first terminal, and a channel region separating the first and second terminals and adjacent a corresponding word line in the plurality of word lines. The corresponding word line acts as the gate of the field effect transistor. A dielectric separates the corresponding word line from the channel region. A memory plane comprises programmable resistance memory material electrically coupled to respective second terminals of the field effect transistors, and conductive material on the programmable resistance memory material and coupled to a common voltage. | 11-25-2010 |
20100295123 | Phase Change Memory Cell Having Vertical Channel Access Transistor - Memory devices are described along with methods for manufacturing. A device as described herein includes a substrate having a first region and a second region. The first region comprises a first field effect transistor comprising first and second doped regions separated by a horizontal channel region within the substrate, a gate overlying the horizontal channel region, and a first dielectric covering the gate of the first field effect transistor. The second region of the substrate includes a second field effect transistor comprising a first terminal extending through the first dielectric to contact the substrate, a second terminal overlying the first terminal and having a top surface, and a vertical channel region separating the first and second terminals. The second field effect transistor also includes a gate on the first dielectric and adjacent the vertical channel region, the gate having a top surface that is co-planar with the top surface of the second terminal. A second dielectric separates the gate of the second field effect transistor from the vertical channel region. | 11-25-2010 |
20100301409 | VERTICAL FIELD EFFECT TRANSISTOR ARRAYS AND METHODS FOR FABRICATION THEREOF - Vertical field effect transistor semiconductor structures and methods for fabrication of the vertical field effect transistor semiconductor structures provide an array of semiconductor pillars. Each vertical portion of each semiconductor pillar in the array of semiconductor pillars has a linewidth greater than a separation distance to an adjacent semiconductor pillar. Alternatively, the array may comprise semiconductor pillars with different linewidths, optionally within the context of the foregoing linewidth and separation distance limitations. A method for fabricating the array of semiconductor pillars uses a minimally photolithographically dimensioned pillar mask layer that is annularly augmented with at least one spacer layer prior to being used as an etch mask. | 12-02-2010 |
20100328994 | PHASE CHANGE MEMORY WITH FINITE ANNULAR CONDUCTIVE PATH - A phase change memory device and a method for programming the same. The method includes determining a maximum possible resistance for the memory cells in the phase change memory device. The method includes determining a high resistance state for the memory cells in the phase change memory device. The method includes receiving a request to program a target memory cell in the phase change memory device to the high resistance state. The method also includes resetting the target memory cell in the phase change memory device to the high resistance state such that the high resistance state of the target memory cell is of less resistance than the maximum possible resistance. In one embodiment of the invention, the high resistance state for the memory cells in the phase change memory device is at least 10% less than the maximum possible resistance. | 12-30-2010 |
20110001111 | THERMALLY INSULATED PHASE CHANGE MATERIAL CELLS - A memory cell structure and method for forming the same. The method includes forming a pore within a dielectric layer. The pore is formed over the center of an electrically conducting bottom electrode. The method includes depositing a thermally insulating layer along at least one sidewall of the pore. The thermally insulating layer isolates heat from phase change current to the volume of the pore. In one embodiment phase change material is deposited within the pore and the volume of the thermally insulating layer. In another embodiment a pore electrode is formed within the pore and the volume of the thermally insulating layer, with the phase change material being deposited above the pore electrode. The method also includes forming an electrically conducting top electrode above the phase change material. | 01-06-2011 |
20110049460 | SINGLE MASK ADDER PHASE CHANGE MEMORY ELEMENT - A method of fabricating a phase change memory element within a semiconductor structure includes etching an opening to an upper surface of a bottom electrode, the opening being formed of a height equal to a height of a metal region at a same layer within the semiconductor structure, depositing phase change material within the opening, recessing the phase change material within the opening, and forming a top electrode on the recessed phase change material. | 03-03-2011 |
20110049461 | CHEMICAL MECHANICAL POLISHING STOP LAYER FOR FULLY AMORPHOUS PHASE CHANGE MEMORY PORE CELL - A method for fabricating a phase change memory pore cell that includes forming a bottom electrode, forming a first dielectric layer on the bottom electrode, forming a sacrificial layer on the first dielectric layer, forming an isolation layer on the sacrificial layer, and forming a second dielectric layer on the isolation layer. The method further includes forming a via overlying the bottom electrode, the via extending to the sacrificial layer, etching through the sacrificial layer to the first dielectric layer to form a pore defined extending through the sacrificial layer and the first dielectric layer, depositing phase change material on the sacrificial layer and into the pore and removing the phase change material formed outside the pore, removing the sacrificial layer to expose the pore, the pore being vertically aligned, and forming a top electrode over the pore. | 03-03-2011 |
20110049462 | FLAT LOWER BOTTOM ELECTRODE FOR PHASE CHANGE MEMORY CELL - A phase change memory cell having a flat lower bottom electrode and a method for fabricating the same. The method includes forming a dielectric layer over a substrate including an array of conductive contacts, patterning, a via having a low aspect ratio such that a depth of the via is less than a width thereof, to a contact surface of the substrate corresponding to each of the array of conductive contacts to be connected to access circuitry, etching the dielectric layer and depositing electrode material over the etched dielectric layer and within each via, and planarizing the electrode material to form a plurality of lower bottom electrodes on each of the conductive contacts. | 03-03-2011 |
20110057162 | IN VIA FORMED PHASE CHANGE MEMORY CELL WITH RECESSED PILLAR HEATER - A method for fabricating a phase change memory device including a plurality of in via phase change memory cells includes forming pillar heaters formed of a conductive material along a contact surface of a substrate corresponding to each of an array of conductive contacts to be connected to access circuitry, forming a dielectric layer along exposed areas of the substrate surrounding the pillar heaters, forming an interlevel dielectric (ILD) layer above the dielectric layer, etching a via to the dielectric layer, each via corresponding to each of pillar heater such that an upper surface of each pillar heater is exposed within each via, recessing each pillar heater, depositing phase change material in each via on each recessed pillar heater, recessing the phase change material within each via, and forming a top electrode within the via on the phase change material. | 03-10-2011 |
20110069538 | MULTI-LEVEL CELL PROGRAMMING OF PCM BY VARYING THE RESET AMPLITUDE - A phase change memory device and a method for programming the same. The method includes determining a characterized lowest SET current and corresponding SET resistance for the phase change memory device. The method includes determining a characterized RESET current slope for the phase change memory device. The method also includes calculating a first current amplitude for a RESET pulse based on the characterized lowest SET current and the characterized RESET current slope. The method includes applying the RESET pulse to a target memory cell in the phase change memory device and measuring the resistance of the target memory cell. If the measured resistance is substantially less than a target resistance, the method further includes applying one or more additional RESET pulses. In one embodiment of the invention, the one or more additional RESET pulses have current amplitudes greater than a previously applied RESET pulse. | 03-24-2011 |
20110104899 | SUB-LITHOGRAPHIC PRINTING METHOD - A trench structure and an integrated circuit comprising sub-lithographic trench structures in a substrate. In one embodiment the trench structure is created by forming sets of trenches with a lithographic mask and filling the sets of trenches with sets of step spacer blocks comprising two alternating spacer materials which are separately removable from each other. In one embodiment, the trench structures formed are one-nth the thickness of the lithographic mask's feature size. The size of the trench structures being dependent on the thickness and number of spacer material layers used to form the set of step spacer blocks. The number of spacer material layers being n/2 and the thickness of each spacer material layer being one-nth of the lithographic mask's feature size. | 05-05-2011 |
20110108960 | SUB-LITHOGRAPHIC PRINTING METHOD - A trench structure and an integrated circuit comprising sub-lithographic trench structures in a substrate. In one embodiment the trench structure is created by forming sets of trenches with a lithographic mask and filling the sets of trenches with sets of step spacer blocks comprising two alternating spacer materials which are separately removable from each other. In one embodiment, the trench structures formed are one-nth the thickness of the lithographic mask's feature size. The size of the trench structures being dependent on the thickness and number of spacer material layers used to form the set of step spacer blocks. The number of spacer material layers being n/2 and the thickness of each spacer material layer being one-nth of the lithographic mask's feature size. | 05-12-2011 |
20110116312 | NON VOLATILE CELL AND ARCHITECTURE WITH SINGLE BIT RANDOM ACCESS READ, PROGRAM AND ERASE - One embodiment is a non-volatile memory cell with random access read, program, and erase. The memory cell includes a cell transistor that includes a source region, a drain region, a first insulating spacer, and a second insulating spacer. The memory cell also includes a source-side transistor, a drain-side transistor, a source-side multiplexer, a drain-side multiplexer, a source-side sense amplifier, and a drain-side write driver. A first binary value is stored in a first bit in the memory cell by trapping or releasing a first electric charge in the first insulating spacer. The first bit is read by sensing the resistive change in the cell transistor or by sensing the threshold voltage change in the cell transistor. | 05-19-2011 |
20110186800 | PORE PHASE CHANGE MATERIAL CELL FABRICATED FROM RECESSED PILLAR - A method of manufacturing an electrode is provided that includes providing a pillar of a first phase change material atop a conductive structure of a dielectric layer; or the inverted structure; forming an insulating material atop dielectric layer and adjacent the pillar, wherein an upper surface of the first insulating material is coplanar with an upper surface of the pillar; recessing the upper surface of the pillar below the upper surface of the insulating material to provide a recessed cavity; and forming a second phase change material atop the recessed cavity and the upper surface of the insulating material, wherein the second phase change material has a greater phase resistivity than the first phase change material. | 08-04-2011 |
20110193045 | POST DEPOSITION METHOD FOR REGROWTH OF CRYSTALLINE PHASE CHANGE MATERIAL - Techniques for forming a phase change memory cell. An example method includes forming a bottom electrode within a substrate. The method includes forming a phase change layer above the bottom electrode. The method includes forming a capping layer and an insulator layer. The method includes crystallizing the phase change material in the phase change layer so that the phase change layer is void free. The method further comprises heating the phase change material in the phase change layer from the bottom electrode and as a result the phase change layer is crystallized from the bottom to the top. In one embodiment, a rapid thermal anneal (RTA) is applied for crystallizing the phase change material. | 08-11-2011 |
20110210307 | CHEMICAL MECHANICAL POLISHING STOP LAYER FOR FULLY AMORPHOUS PHASE CHANGE MEMORY PORE CELL - A method for fabricating a phase change memory pore cell that includes forming a bottom electrode, forming a dielectric layer on the bottom electrode, and forming a sacrificial layer on the dielectric layer. The method further includes selectively etching portions of the sacrificial layer and the dielectric layer to define a pore extending through the sacrificial layer and the dielectric layer, depositing phase change material on the sacrificial layer and into the pore and removing the phase change material formed outside the pore, removing the sacrificial layer to expose the pore, the pore being vertically aligned, and forming a top electrode over the pore. | 09-01-2011 |
20110217818 | PHASE CHANGE MEMORY CELL HAVING VERTICAL CHANNEL ACCESS TRANSISTOR - A device includes a substrate having a first region and a second region. The first region comprises a first field effect transistor having a horizontal channel region within the substrate, a gate overlying the horizontal channel region, and a first dielectric covering the gate of the first field effect transistor. The second region of the substrate includes a second field effect transistor comprising a first terminal extending through the first dielectric to contact the substrate, a second terminal overlying the first terminal and having a top surface, and a vertical channel region separating the first and second terminals. The second field effect transistor also includes a gate on the first dielectric and adjacent the vertical channel region, the gate having a top surface that is co-planar with the top surface of the second terminal. | 09-08-2011 |
20110227021 | POST DEPOSITION METHOD FOR REGROWTH OF CRYSTALLINE PHASE CHANGE MATERIAL - Techniques for forming a phase change memory cell. An example apparatus includes a substrate and a bottom electrode carried by the substrate. The bottom electrode is a thermal conductor. A phase change layer, including phase change material, is disposed over the bottom electrode. A thermal insulating layer is disposed above the phase change layer. A heater is configured to temporarily melt the phase change material such that the phase change material crystallizes without voids within a switching region after melting. | 09-22-2011 |
20110275209 | VERTICAL FIELD EFFECT TRANSISTOR ARRAYS AND METHODS FOR FABRICATION THEREOF - Vertical field effect transistor semiconductor structures and methods for fabrication of the vertical field effect transistor semiconductor structures provide an array of semiconductor pillars. Each vertical portion of each semiconductor pillar in the array of semiconductor pillars has a linewidth greater than a separation distance to an adjacent semiconductor pillar. Alternatively, the array may comprise semiconductor pillars with different linewidths, optionally within the context of the foregoing linewidth and separation distance limitations. A method for fabricating the array of semiconductor pillars uses a minimally photolithographically dimensioned pillar mask layer that is annularly augmented with at least one spacer layer prior to being used as an etch mask. | 11-10-2011 |
20120018845 | Polysilicon Plug Bipolar Transistor For Phase Change Memory - Memory devices and methods for manufacturing are described herein. A memory device described herein includes a plurality of memory cells. Memory cells in the plurality of memory cells comprise respective bipolar junction transistors and memory elements. The bipolar junction transistors are arranged in a common collector configuration and include an emitter comprising doped polysilicon having a first conductivity type, the emitter contacting a corresponding word line in a plurality of word lines to define a pn junction. The bipolar junction transistors include a portion of the corresponding word line underlying the emitter acting as a base, and a collector comprising a portion of the single-crystalline substrate underlying the base. | 01-26-2012 |
20120037877 | ONE-MASK PHASE CHANGE MEMORY PROCESS INTEGRATION - An example embodiment disclosed is a method for fabricating a phase change memory cell. The method includes forming a non-sublithographic via within an insulating substrate. The insulating substrate is embedded on the same layer as a first metalization layer (Metal | 02-16-2012 |
20120063195 | Reconfigurable Multi-level Sensing Scheme for Semiconductor Memories - A method for sensing at least one parameter indicative of a logical state of a multi-level memory cell includes the steps of: measuring the parameter of the multi-level memory cell; comparing the measured parameter of the multi-level memory cell with a prescribed reference signal, the reference signal having a value which varies as a function of time; and storing a time value corresponding to a point in time at which the reference signal is substantially equal to the measured parameter of the multi-level memory cell, the stored time value being indicative of a sensed logical state of the multi-level memory cell. | 03-15-2012 |
20120084241 | PRODUCING SPIKE-TIMING DEPENDENT PLASTICITY IN A NEUROMORPHIC NETWORK UTILIZING PHASE CHANGE SYNAPTIC DEVICES - Embodiments of the invention relate to a neuromorphic network for producing spike-timing dependent plasticity. The neuromorphic network includes a plurality of electronic neurons and an interconnect circuit coupled for interconnecting the plurality of electronic neurons. The interconnect circuit includes plural synaptic devices for interconnecting the electronic neurons via axon paths, dendrite paths and membrane paths. Each synaptic device includes a variable state resistor and a transistor device with a gate terminal, a source terminal and a drain terminal, wherein the drain terminal is connected in series with a first terminal of the variable state resistor. The source terminal of the transistor device is connected to an axon path, the gate terminal of the transistor device is connected to a membrane path and a second terminal of the variable state resistor is connected to a dendrite path, such that each synaptic device is coupled between a first axon path and a first dendrite path, and between a first membrane path and said first dendrite path. | 04-05-2012 |
20120112154 | IN VIA FORMED PHASE CHANGE MEMORY CELL WITH RECESSED PILLAR HEATER - A method for fabricating a phase change memory device including a plurality of in via phase change memory cells includes forming pillar heaters formed of a conductive material along a contact surface of a substrate corresponding to each of an array of conductive contacts to be connected to access circuitry, forming a dielectric layer along exposed areas of the substrate surrounding the pillar heaters, forming an interlevel dielectric (ILD) layer above the dielectric layer, etching a via to the dielectric layer, each via corresponding to each of pillar heater such that an upper surface of each pillar heater is exposed within each via, recessing each pillar heater, depositing phase change material in each via on each recessed pillar heater, recessing the phase change material within each via, and forming a top electrode within the via on the phase change material. | 05-10-2012 |
20120115302 | METHOD TO REDUCE A VIA AREA IN A PHASE CHANGE MEMORY CELL - A memory cell structure and method to form such structure. The method partially comprised of forming a via within an oxidizing layer, over the center of a bottom electrode. The method includes depositing a via spacer along the sidewalls of the via and oxidizing the via spacer. The via spacer being comprised of a material having a Pilling-Bedworth ratio of at least one and one-half and is an insulator when oxidized. The via area is reduced by expansion of the via spacer during the oxidation. Alternatively, the method is partially comprised of forming a via within a first layer, over the center of the bottom electrode. The first layer has a Pilling-Bedworth ratio of at least one and one-half and is an insulator when oxidized. The method also includes oxidizing at least a portion of the sidewalls of the via in the first layer. | 05-10-2012 |
20120120701 | TERNARY CONTENT ADDRESSABLE MEMORY USING PHASE CHANGE DEVICES - A content addressable memory device with a plurality of memory cells storing ternary data values of high, low, and don't care. An aspect of the content addressable memory device is the use of first memory elements and second memory elements in the memory cells. The first and second memory elements are electrically coupled in parallel circuit to a match-line. The first memory elements are coupled to first word-lines and the second memory elements are coupled to second word-lines. The first memory elements are configured to store low resistance states if the ternary data value is low and high resistance states if the ternary data value is either high or don't care. The second memory elements are configured to store the low resistance states if the ternary data value is high and the high resistance states if the ternary data value is either low or don't care. | 05-17-2012 |
20120126194 | THERMALLY INSULATED PHASE CHANGE MATERIAL MEMORY CELLS - A memory cell structure and method for forming the same. The method includes forming a pore within a dielectric layer. The pore is formed over the center of an electrically conducting bottom electrode. The method includes depositing a thermally insulating layer along at least one sidewall of the pore. The thermally insulating layer isolates heat from phase change current to the volume of the pore. In one embodiment phase change material is deposited within the pore and the volume of the thermally insulating layer. In another embodiment a pore electrode is formed within the pore and the volume of the thermally insulating layer, with the phase change material being deposited above the pore electrode. The method also includes forming an electrically conducting top electrode above the phase change material. | 05-24-2012 |
20120129313 | THERMALLY INSULATED PHASE MATERIAL CELLS - A memory cell structure and method for forming the same. The method includes forming a pore within a dielectric layer. The pore is formed over the center of an electrically conducting bottom electrode. The method includes depositing a thermally insulating layer along at least one sidewall of the pore. The thermally insulating layer isolates heat from phase change current to the volume of the pore. In one embodiment phase change material is deposited within the pore and the volume of the thermally insulating layer. In another embodiment a pore electrode is formed within the pore and the volume of the thermally insulating layer, with the phase change material being deposited above the pore electrode. The method also includes forming an electrically conducting top electrode above the phase change material. | 05-24-2012 |
20120168709 | SINGLE MASK ADDER PHASE CHANGE MEMORY ELEMENT - A method of fabricating a phase change memory element within a semiconductor structure includes etching an opening to an upper surface of a bottom electrode, the opening being formed of a height equal to a height of a metal region at a same layer within the semiconductor structure, depositing phase change material within the opening, recessing the phase change material within the opening, and forming a top electrode on the recessed phase change material. | 07-05-2012 |
20120181627 | METHOD TO TAILOR LOCATION OF PEAK ELECTRIC FIELD DIRECTLY UNDERNEATH AN EXTENSION SPACER FOR ENHANCED PROGRAMMABILITY OF A PROMPT-SHIFT DEVICE - A prompt-shift device having reduced programming time in the sub-millisecond range is provided. The prompt-shift device includes an altered extension region located within said semiconductor substrate and on at least one side of the patterned gate region, and an altered halo region located within the semiconductor substrate and on at least one side of the patterned gate region. The altered extension region has an extension ion dopant concentration of less than about 1E20 atoms/cm | 07-19-2012 |
20120181628 | METHOD TO TAILOR LOCATION OF PEAK ELECTRIC FIELD DIRECTLY UNDERNEATH AN EXTENSION SPACER FOR ENHANCED PROGRAMMABILITY OF A PROMPT-SHIFT DEVICE - A prompt-shift device having reduced programming time in the sub-millisecond range is provided. The prompt-shift device includes an altered extension region located within said semiconductor substrate and on at least one side of the patterned gate region, and an altered halo region located within the semiconductor substrate and on at least one side of the patterned gate region. The altered extension region has an extension ion dopant concentration of less than about 1E20 atoms/cm | 07-19-2012 |
20120199806 | POLYSILICON EMITTER BJT ACCESS DEVICE FOR PCRAM - A resistive non-volatile memory cell with a bipolar junction transistor (BJT) access device formed in conjunction with the entire memory cell. The memory cell includes a substrate acting as a collector, a semiconductor base layer acting as a base, and a semiconductor emitter layer acting as an emitter. Additionally, metal plugs and the phase change memory element are formed above the BJT access device while the emitter, metal plugs, and phase change memory element are contained within an insulating region. In one embodiment of the invention, a spacer layer is formed and the emitter layer is contained within the protective spacer layer. The spacer layer is contained within the insulating region. | 08-09-2012 |
20120267601 | PHASE CHANGE MEMORY CELLS WITH SURFACTANT LAYERS - An example embodiment is a phase change memory cell including a bottom electrode and phase change material carried within a via above the bottom electrode. A surfactant layer is deposited above the bottom electrode. The surfactant layer includes a surfactant configured to lower an interfacial force between the phase change material and the via surface. | 10-25-2012 |
20120280197 | FLAT LOWER BOTTOM ELECTRODE FOR PHASE CHANGE MEMORY CELL - A phase change memory cell having a flat lower bottom electrode and a method for fabricating the same. The method includes forming a dielectric layer over a substrate including an array of conductive contacts, patterning, a via having a low aspect ratio such that a depth of the via is less than a width thereof, to a contact surface of the substrate corresponding to each of the array of conductive contacts to be connected to access circuitry, etching the dielectric layer and depositing electrode material over the etched dielectric layer and within each via, and planarizing the electrode material to form a plurality of lower bottom electrodes on each of the conductive contacts. | 11-08-2012 |
20120309159 | METHOD TO SELECTIVELY GROW PHASE CHANGE MATERIAL INSIDE A VIA HOLE - An example embodiment is a method for filling a via hole with phase change material. The method steps include forming a bottom electrode in a substrate, depositing a dielectric layer above the bottom electrode, and forming a via hole within the dielectric layer down to a top surface of the bottom electrode. The substrate is heated to a reaction temperature and a first phase change material precursor is deposited within the via hole. The first precursor is configured to decompose on the top surface of the bottom electrode and chemisorb on a top surface of the dielectric layer at the reaction temperature. A second precursor is deposited within the via hole after the first precursor at least partially decomposes on the top surface of the bottom electrode. | 12-06-2012 |
20130001500 | PORE PHASE CHANGE MATERIAL CELL FABRICATED FROM RECESSED PILLAR - A method of manufacturing an electrode is provided that includes providing a pillar of a first phase change material atop a conductive structure of a dielectric layer; or the inverted structure; forming an insulating material atop dielectric layer and adjacent the pillar, wherein an upper surface of the first insulating material is coplanar with an upper surface of the pillar; recessing the upper surface of the pillar below the upper surface of the insulating material to provide a recessed cavity; and forming a second phase change material atop the recessed cavity and the upper surface of the insulating material, wherein the second phase change material has a greater phase resistivity than the first phase change material. | 01-03-2013 |
20130039110 | 3D ARCHITECTURE FOR BIPOLAR MEMORY USING BIPOLAR ACCESS DEVICE - Memory device and method for fabricating a memory device on two layers of a semiconductor wafer. An example device includes bit lines and word lines fabricated at one layer of a semiconductor wafer and re-writable nonvolatile memory cells that include a two-terminal access device with a bidirectional voltage-current characteristics for positive and negative voltages applied at the terminals. Additionally, a drive circuit electrically coupled to the memory cells and configured to program the memory cells is fabricated at another layer of the semiconductor wafer. Another example embodiment includes a memory device where a plurality of memory arrays are fabricated at one layer of a semiconductor wafer and a plurality of drive circuits electrically coupled to the memory cells and configured to read the memory cells are fabricated at a second layer of the semiconductor wafer. | 02-14-2013 |
20130087756 | HEAT SHIELD LINER IN A PHASE CHANGE MEMORY CELL - A memory cell structure and method to form such structure. An example memory cell includes a bottom electrode formed within a substrate. The memory cell also includes a phase change memory element in contact with the bottom electrode. The memory cell includes a liner laterally surrounding the phase change memory element. The liner includes dielectric material that is thermally conductive and electrically insulating. The memory cell includes an insulating dielectric layer laterally surrounding the liner. The insulating dielectric layer includes material having a lower thermal conductivity than that of the liner. | 04-11-2013 |
20130119339 | MEMORY CELL WITH POST DEPOSITION METHOD FOR REGROWTH OF CRYSTALLINE PHASE CHANGE MATERIAL - A phase change memory cell with substantially void free crystalline phase change material. An example memory cell includes a substrate and a bottom electrode carried by the substrate. The bottom electrode is a thermal conductor. A phase change layer includes phase change material. The phase change layer is void free within a switching region when the phase change material is in a crystalline phase. A top electrode is positioned over the phase change layer. | 05-16-2013 |
20130163320 | ENERGY-EFFICIENT ROW DRIVER FOR PROGRAMMING PHASE CHANGE MEMORY - A drive circuit and method for parallel programming a plurality of phase change memory (PCM) cells includes a first signal generator device for generating a slow ramping signal; an adiabatic computing element receives the slow ramping signal and responsively generates an output slow ramping signal in adiabatic fashion, the output slow ramping signal applied to the single wordline conductor associated with each PCM cell of the plurality of cells being programmed in a time interval. Each PCM cell of the plurality being programmed is connected to a respective bitline conductor. A second signal generator generates, during the time interval, one or more bitline signals for input to a respective bitline conductor of a respective PCM cell. A state of the applied slow ramping output signal and the one or more bitline signals during the time interval governs a programmed state of the PCM cell. | 06-27-2013 |
20130163321 | DRIFT MITIGATION FOR MULTI-BITS PHASE CHANGE MEMORY - An RC-based sensing scheme to effectively sense the cell resistance of a programmed Phase Change Material (PCM) memory cell. The sensing scheme ensures the same physical configuration of each cell (after programming): same amorphous volume, same trap density/distribution, etc. The sensing scheme is based on a metric: the RC based sense amplifier implements two trigger points. The measured time interval between these two points is used as the metric to determine whether the programmed cell state, e.g., resistance, is programmed into desired value. The RC-based sensing scheme is embedded into an iterative PCM cell programming technique to ensure a tight distribution of resistance at each level after programming; and ensure the probability of level aliasing is very small, leading to less problematic drift. | 06-27-2013 |
20130163322 | PARALLEL PROGRAMMING SCHEME IN MULTI-BIT PHASE CHANGE MEMORY - A system, a method for parallel programming multiple bits of a phase change memory array for high bandwidth. The system and method includes parallel programming scheme wherein a common wordline (WL) is driven with a first pulse of one of: gradually increasing (RESET) or decreasing (SET) amplitudes which control current flow through one or more phase change memory cells associated with the WL. Simultaneously therewith, one or more bitlines (BLs) are driven with one or more second pulses, each second pulse more narrow than that of the first pulse applied to the WL. The starting time of the one or more second pulses may vary with each bitline driven at a time later than, but within the window of the wordline pulse to achieve a programming current suitable for achieving the corresponding memory cell state. | 06-27-2013 |
20130193401 | SELF-ALIGNED PROCESS TO FABRICATE A MEMORY CELL ARRAY WITH A SURROUNDING-GATE ACCESS TRANSISTOR - A memory array including a plurality of memory cells. Each word line is electrically coupled to a set of memory cells, a gate contact and a pair of dielectric pillars positioned parallel to the word line. Dielectric pillars are placed on both sides of the gate contact. Also a method to prevent a gate contact from electrically connecting to a source contact for a plurality of memory cells on a substrate. The method includes formation of a pair of pillars made of an insulating material over the substrate, depositing an electrically conductive gate material between and over the pillars, etching the gate material such that it both partially fills a space between the pair of pillars and forms a word line for the memory cells, and depositing a gate contact between the dielectric pillars such that the gate contact is in electrical contact with the gate material. | 08-01-2013 |
20130200330 | SELF-ALIGNED PROCESS TO FABRICATE A MEMORY CELL ARRAY WITH A SURROUNDING-GATE ACCESS TRANSISTOR - A memory array including a plurality of memory cells. Each word line is electrically coupled to a set of memory cells, a gate contact and a pair of dielectric pillars positioned parallel to the word line and placed on both sides of the gate contact over a layer of insulating material. Also a method to prevent a gate contact from electrically connecting to a source contact for a plurality of memory cells on a substrate. The method includes formation of a pair of pillars over an insulating material on the substrate, depositing an electrically conductive gate material between and over the pillars, etching the gate material such that it both partially fills a space between the pair of pillars and forms a word line for the memory cells, and depositing a gate contact between the dielectric pillars such that the gate contact is in electrical contact with the gate material. | 08-08-2013 |
20130223121 | SENSE SCHEME FOR PHASE CHANGE MATERIAL CONTENT ADDRESSABLE MEMORY - A sensing circuit and method for sensing match lines in content addressable memory. The sensing circuit includes an inverter electrically coupled in a feedback loop to a match line. The inverter includes an inverting threshold of the match line. The match line is charged to substantially a first voltage threshold during a pre-charge phase. An evaluation phase occurs when the match line voltage drops from substantially the first voltage threshold to substantially the second voltage threshold. | 08-29-2013 |
20130223125 | DECODING SCHEME FOR BIPOLAR-BASED DIODE THREE-DIMENSIONAL MEMORY REQUIRING BIPOLAR PROGRAMMING - A system and method for operating a bipolar memory cell array including a bidirectional access diode. The system includes a column voltage. The column voltage switch includes column voltages and an output electrically coupled to the bidirectional access diode. The column voltages include at least one write-one column voltage and at least one write-zero column voltage. The system also includes a row voltage switch. The row voltage switch includes row voltages and an output electrically coupled to the bidirectional access diode. The row voltages include at least one write-one row voltage and at least one write-zero row voltage. The system further includes a column decoder and a row decoder electrically coupled to a select line of the column voltage switch and row voltage switch, respectively. The system includes a write driver electrically coupled to the select lines of the row and column switches. | 08-29-2013 |
20130277639 | SELF-ALIGNED PROCESS TO FABRICATE A MEMORY CELL ARRAY WITH A SURROUNDING-GATE ACCESS TRANSISTOR - A memory array including a plurality of memory cells. Each word line is electrically coupled to a set of memory cells, a gate contact and a pair of dielectric pillars positioned parallel to the word line with a spacer of electrically insulating material surrounding the gate contact. Also a method to prevent a gate contact from electrically connecting to a source contact for a plurality of memory cells on a substrate. The method includes depositing and etching gate material to partially fill a space between the pillars and to form a word line for the memory cells, etching a gate contact region for the word line between the pair of pillars, forming a spacer of electrically insulating material in the gate contact region, and depositing a gate contact between the pair of pillars to be in electrical contact with the gate material such that the spacer surrounds the gate contact. | 10-24-2013 |
20130295742 | METHOD TO TAILOR LOCATION OF PEAK ELECTRIC FIELD DIRECTLY UNDERNEATH AN EXTENSION SPACER FOR ENHANCED PROGRAMMABILITY OF A PROMPT-SHIFT DEVICE - A method to enhance the programmability of a prompt-shift device is provided, which reduces the programming time to sub-millisecond times, by altering the extension and halo implants, instead of simply omitting the same from one side of the device as is the case in the prior art prompt-shift devices. In one embodiment, no additional masks are employed. The altered extension implant is performed at a reduced ion dose as compared to a conventional extension implant process, while the altered halo implant is performed at a higher ion dose than a conventional halo implant. The altered halo/extension implant shifts the peak of the electrical field to under an extension dielectric spacer. | 11-07-2013 |
20130299768 | THERMALLY INSULATED PHASE CHANGE MATERIAL CELLS - Memory cell structures for phase change memory. An example memory cell structure comprising includes a bottom electrode comprised of electrically conducting material, and phase change material disposed above the bottom electrode. A layer of thermally insulating material is disposed, at least partially, between the bottom electrode and the phase change material. The thermally insulating material is comprised of Tantalum Oxide. A top electrode is comprised of electrically conducting material. | 11-14-2013 |
20130313501 | DRIFT-INSENSITIVE OR INVARIANT MATERIAL FOR PHASE CHANGE MEMORY - A method of storing a bit at a memory device is disclosed. A memory cell the memory device is formed of a germanium-deficient chalcogenide glass configured to alternate between an amorphous phase and a crystalline phase upon application of a selected voltage, wherein a drift coefficient of the germanium-deficient chalcogenide glass is less than a drift coefficient of an undoped chalcogenide glass. A voltage is applied to the formed memory cell to select one of the amorphous phase and the crystalline phase to store the bit. | 11-28-2013 |
20130314983 | DRIFT-INSENSITIVE OR INVARIANT MATERIAL FOR PHASE CHANGE MEMORY - A method of storing a bit at a memory device is disclosed. A memory cell the memory device is formed of a germanium-deficient chalcogenide glass configured to alternate between an amorphous phase and a crystalline phase upon application of a selected voltage, wherein a drift coefficient of the germanium-deficient chalcogenide glass is less than a drift coefficient of an undoped chalcogenide glass. A voltage is applied to the formed memory cell to select one of the amorphous phase and the crystalline phase to store the bit. | 11-28-2013 |
20140021533 | SELF-ALIGNED PROCESS TO FABRICATE A MEMORY CELL ARRAY WITH A SURROUNDING-GATE ACCESS TRANSISTOR - A memory array including a plurality of memory cells. In one embodiment, each memory cell is coupled to an electrically conductive gate material. A word line is coupled to the gate material at a contact interface level. A pair of pillars is comprised of an insulating material that extends below the contact interface level. Also, a method to prevent a gate contact from electrically connecting to a source contact for a plurality of memory cells on a substrate. The method includes depositing and etching gate material to partially fill a space between the pillars and to form a word line for the memory cells, forming a pair of pillars comprised of an insulating material and depositing a gate contact between the pair of pillars such that the gate contact electrically couples the gate material at a contact interface level and the insulating material extends below the contact interface level. | 01-23-2014 |
20140022850 | DECODING SCHEME FOR BIPOLAR-BASED DIODE THREE-DIMENSIONAL MEMORY REQUIRING UNIPOLAR PROGRAMMING - A system and method for operating a unipolar memory cell array including a bidirectional access diode. The system includes a column voltage switch electrically coupled to a plurality of column voltages. The column voltage switch includes an output electrically coupled to the bidirectional access diode. The plurality of column voltages includes at least one select column voltage and one deselect column voltage. The system includes a row voltage switch electrically coupled to a plurality of row voltages. The row voltage switch includes an output electrically coupled to the bidirectional access diode. The plurality of row voltages includes at least one select row voltage and one deselect row voltage. The system includes a column and row decoder electrically coupled to a select line of the column and row voltage switches, respectively. | 01-23-2014 |
20140022851 | DECODING SCHEME FOR BIPOLAR-BASED DIODE THREE-DIMENSIONAL MEMORY REQUIRING UNIPOLAR PROGRAMMING - A system and method for operating a unipolar memory cell array including a bidirectional access diode. An example embodiment is a method including determining if the operating state of the unipolar memory cell is in a select state or a deselect state and the programming state is a read state or a write state. The method switches a column voltage switch based on the operating state and the programming state of the unipolar memory cell. The method further switches a row voltage switch based on the operating state and the programming state of the unipolar memory cell. | 01-23-2014 |
20140024185 | SELF-ALIGNED PROCESS TO FABRICATE A MEMORY CELL ARRAY WITH A SURROUNDING-GATE ACCESS TRANSISTOR - A method to prevent a gate contact from electrically connecting to a source contact for a plurality of memory cells on a substrate. The method includes forming pillars with a doped silicon region on the substrate. An electrically conductive gate material is deposited between and over the pillars. The gate material is etched such that the gate material partially fills a space between the pillars. The pillars are then etched such that a pair of pillars from the pillars include an insulating material over the doped silicon region. A gate contact is deposited between the pair of pillars such that the gate contact electrically couples the gate material at a contact interface level, and the insulating material extends below the contact interface level. | 01-23-2014 |
20140026008 | WRITING SCHEME FOR PHASE CHANGE MATERIAL-CONTENT ADDRESSABLE MEMORY - A system for programming a phase change material-content addressable memory (PCM-CAM). The system includes a receiving unit for receiving a word to be written in the PCM-CAM. The word includes low bits represented by a low resistance state in the PCM-CAM and high bits represented by a high resistance state in the PCM-CAM. The system includes a writing unit configured to repeatedly write the low bits in memory cells of the PCM-CAM until the resistance of the memory cells are below a threshold value, and to write high bits in memory cells of the PCM-CAM only once. | 01-23-2014 |
20140052894 | MEMORY CONTROLLER FOR MEMORY WITH MIXED CELL ARRAY AND METHOD OF CONTROLLING THE MEMORY - A memory controller, system including the memory controller and method of controlling the memory. The memory controller receives requests for memory and content sensitively allocates memory space in a mixed cell memory. The memory controller allocates sufficient space including performance memory storing a single bit per cell and dense memory storing more than one bit per cell. Some or all of the memory may be selectable by the memory controller as either Single Level per Cell (SLC) or Multiple Level per Cell (MLC). | 02-20-2014 |
20140052895 | MEMORY WITH MIXED CELL ARRAY AND SYSTEM INCLUDING THE MEMORY - A memory system, system including the memory system and method of reducing memory system power consumption. The memory system includes multiple memory units allocable to one of a number of processor units, e.g., processors or processor cores. A memory controller receives requests for memory from the processor units and allocates sufficient space from the memory to each requesting processor unit. Allocated memory can include some Single Level per Cell (SLC) memory units storing a single bit per cell and other memory units storing more than one bit per cell. Thus, two processor units may be assigned identical memory space, while half, or fewer, than the number of cells of one are assigned to the other. | 02-20-2014 |
20140052900 | MEMORY CONTROLLER FOR MEMORY WITH MIXED CELL ARRAY AND METHOD OF CONTROLLING THE MEMORY - A memory controller, system including the memory controller and method of controlling the memory. The memory controller receives requests for memory and content sensitively allocates memory space in a mixed cell memory. The memory controller allocates sufficient space including performance memory storing a single bit per cell and dense memory storing more than one bit per cell. Some or all of the memory may be selectable by the memory controller as either Single Level per Cell (SLC) or Multiple Level per Cell (MLC). | 02-20-2014 |
20140052901 | MEMORY WITH MIXED CELL ARRAY AND SYSTEM INCLUDING THE MEMORY - A memory system, system including the memory system and method of reducing memory system power consumption. The memory system includes multiple memory units allocable to one of a number of processor units, e.g., processors or processor cores. A memory controller receives requests for memory from the processor units and allocates sufficient space from the memory to each requesting processor unit. Allocated memory can include some Single Level per Cell (SLC) memory units storing a single bit per cell and other memory units storing more than one bit per cell. Thus, two processor units may be assigned identical memory space, while half, or fewer, than the number of cells of one are assigned to the other. | 02-20-2014 |
20140061581 | SELF-ALIGNED PROCESS TO FABRICATE A MEMORY CELL ARRAY WITH A SURROUNDING-GATE ACCESS TRANSISTOR - A memory array including a plurality of memory cells. Each word line is electrically coupled to a set of memory cells, a gate contact and a pair of dielectric pillars positioned parallel to the word line. Dielectric pillars are placed on both sides of the gate contact. Also a method to prevent a gate contact from electrically connecting to a source contact for a plurality of memory cells on a substrate. The method includes formation of a pair of pillars made of an insulating material over the substrate, depositing an electrically conductive gate material between and over the pillars, etching the gate material such that it both partially fills a space between the pair of pillars and forms a word line for the memory cells, and depositing a gate contact between the dielectric pillars such that the gate contact is in electrical contact with the gate material. | 03-06-2014 |
20140092694 | MULTI-BIT RESISTANCE MEASUREMENT - An example embodiment is a circuit for determining a binary value of a memory cell. The circuit includes shunt capacitors having different capacitances to selectively couple with the memory cell, and a controller configured to iteratively charge the shunt capacitors to a first voltage until a selected shunt capacitor causes the first voltage to decay through the memory cell to a first reference voltage within a predetermined time range, determine a binary value of the most significant bits of the memory cell based on the selected shunt capacitor, charge the selected shunt capacitor to a second voltage after determining the binary value of the most significant bits of the memory cell, and determine a binary value of the least significant bits of the memory cell based on a decay of the second voltage at the selected shunt capacitor through the memory cell. | 04-03-2014 |
20140103957 | REACTIVE MATERIAL FOR INTEGRATED CIRCUIT TAMPER DETECTION AND RESPONSE - The present disclosure relates to integrated circuits having tamper detection and response devices and methods for manufacturing such integrated circuits. One integrated circuit having a tamper detection and response device includes at least one reactive material and at least one memory cell coupled to the at least one reactive material. An exothermic reaction in the at least one reactive material causes an alteration to a memory state of the at least one memory cell. Another integrated circuit having a tamper detection and response device includes a substrate, at least one gate on the substrate, and a reactive material between a first well and a second well of the at least one gate. A reaction in the reactive material causes a short in the gate. | 04-17-2014 |
20140140502 | RELIABLE PHYSICAL UNCLONABLE FUNCTION FOR DEVICE AUTHENTICATION - A device having a physical unclonable function includes an integrated circuit and a phase change memory embedded in the integrated circuit and including a plurality of cells, where the phase change memory is set in a manner that creates a phase variation over the plurality of cells, and where the phase variation comprises the physical unclonable function. In another embodiment, a device having a physical unclonable function includes a phase change memory embedded in the device and comprising a plurality of cells, where the phase change memory is set in a manner that creates a phase variation over the plurality of cells, and where the phase variation comprises the physical unclonable function, and a measurement circuit for extracting the physical unclonable function from the phase change memory. | 05-22-2014 |
20140140513 | RELIABLE PHYSICAL UNCLONABLE FUNCTION FOR DEVICE AUTHENTICATION - A method of manufacturing a secure device having a physical unclonable function includes embedding a phase change memory in the secure device, where the phase change memory includes a plurality of cells, and setting the phase change memory in a manner that results in a phase variation over the plurality of cells, wherein the phase variation is the physical unclonable function. A method for retrieving a cryptographic key from an integrated circuit, wherein the cryptographic key is stored in the integrated circuit, includes measuring a property of a phase change memory embedded in the integrated circuit, wherein the phase change memory includes a plurality of cells and the property is a function of a phase variation over the plurality of cells, deriving a signature from the property, and deriving the cryptographic key from the signature. | 05-22-2014 |
20140154862 | UNIFORM CRITICAL DIMENSION SIZE PORE FOR PCRAM APPLICATION - A memory cell and a method of making the same, that includes insulating material deposited on a substrate, a bottom electrode formed within the insulating material, a plurality of insulating layers deposited above the bottom electrode and at least one of which acts as an intermediate insulating layer. A via is defined in the insulating layers above the intermediate insulating layer. A channel is created for etch with a sacrificial spacer. A pore is defined in the intermediate insulating layer. All insulating layers above the intermediate insulating layer are removed, and the entirety of the remaining pore is filled with phase change material. An upper electrode is formed above the phase change material. | 06-05-2014 |
20140160836 | THREE-DIMENSIONAL MEMORY ARRAY AND OPERATION SCHEME - A system, method and computer program product for operating a three-dimensional memory array. An example array includes access transistors with first, second and gate terminals. Bit lines are coupled to the first terminals, word lines coupled to the gate terminals, and vertical lines are coupled to the second terminals. The bit, word, and vertical lines are perpendicular to one another. Memory cells are positioned along the vertical lines, including a bidirectional access device coupled in series with a memory element. The memory element is programmable to first and second states by application of first and second write voltages, opposite in polarity to one another. The array includes conductive plates parallel to the word and bit lines, and perpendicular to the vertical lines. The conductive plates are coupled to memory cells of the same height and separated by insulating layers. | 06-12-2014 |
20140160838 | THREE-DIMENSIONAL MEMORY ARRAY AND OPERATION SCHEME - A system, method and computer program product for operating a three-dimensional memory array. An example array includes access transistors with first, second and gate terminals. Bit lines are coupled to the first terminals, word lines coupled to the gate terminals, and vertical lines are coupled to the second terminals. The bit, word, and vertical lines are perpendicular to one another. Memory cells are positioned along the vertical lines, including a bidirectional access device coupled in series with a memory element. The memory element is programmable to first and second states by application of first and second write voltages, opposite in polarity to one another. The array includes conductive plates parallel to the word and bit lines, and perpendicular to the vertical lines. The conductive plates are coupled to memory cells of the same height and separated by insulating layers. | 06-12-2014 |
20140166962 | PHASE CHANGE MEMORY CELL WITH LARGE ELECTRODE CONTACT AREA - A phase change memory cell and a method for fabricating the phase change memory cell. The phase change memory cell includes a bottom electrode and a first non-conductive layer. The first non-conductive layer defines a first well, a first electrically conductive liner lines the first well, and the first well is filled with a phase change material in the phase change memory cell. | 06-19-2014 |
20140170831 | PHASE CHANGE MEMORY CELL WITH LARGE ELECTRODE CONTACT AREA - A phase change memory cell and a method for fabricating the phase change memory cell. The phase change memory cell includes a bottom electrode and a first non-conductive layer. The first non-conductive layer defines a first well, a first electrically conductive liner lines the first well, and the first well is filled with a phase change material in the phase change memory cell. | 06-19-2014 |
20140252294 | PHASE CHANGE MEMORY CELL WITH HEAT SHIELD - A phase change memory cell, an array of the phase change memory cells, and a method for fabricating the phase change memory cells. The phase change memory cell includes a bottom electrode, a heating element, and a heat shield. During programming of the phase change memory cell, the bottom electrode passes current to the phase change memory cell. The heating element is electrically coupled to the bottom electrode and generates heat during the programming of the phase change memory cell. The heat shield is thermally conductive and surrounds at least a portion of the heating element. The heat shield conducts heat generated during programming of the phase change memory cell to the bottom electrode. | 09-11-2014 |
20140252418 | ELECTRICAL COUPLING OF MEMORY CELL ACCESS DEVICES TO A WORD LINE - A memory array and a method for electrically coupling memory cell access devices to a word line. The memory array includes a source line electrically coupled to each source terminal of the memory cell access devices. The memory array also includes a first set of at least two vertical pillars positioned above and electrically coupled to the source line. A second set of vertical pillars electrically isolated from the source line and positioned such that the source line does not extend below the second set of vertical pillars is also included. Furthermore, gate terminals of the memory cell access devices laterally surround the first set of vertical pillars and the second set of vertical pillars. Finally, a first word line contact is positioned between two of the second set of vertical pillars. The first word line contact is electrically coupled to the gate terminals. | 09-11-2014 |
20140252556 | SINGLE-MASK SPACER TECHNIQUE FOR SEMICONDUCTOR DEVICE FEATURES - A method for fabricating semiconductor features. The method includes forming a first layer over a substrate. Forming a plurality of first holes in the first layer. The first layer includes sidewalls separating at least a portion of each first hole. The first holes include overlapping holes that are not separated by the sidewalls. Forming a plurality of spacers on the substrate and first layer. The spacers include spacer sidewalls separating adjacent overlapping holes. Etching exposed portions of the substrate to form a plurality of second holes. | 09-11-2014 |
20140254236 | MEMORY STATE SENSING BASED ON CELL CAPACITANCE - A memory cell and method for operating a memory cell including a bidirectional access device and memory element electrically coupled in series. The bidirectional access device includes a tunneling capacitance. The memory element programmable to a first and second state by application of a first and second write voltage opposite in polarity to one another. The memory element has a lower capacitance in the first state than the second state. A read unit senses a transient read current due to a voltage drop upon application of a read voltage. Determining if the memory element is the first or second state is based on whether the read current is greater or less than a sense threshold. The sense threshold is based on a capacitance ratio between the first and second state. | 09-11-2014 |
20140254291 | MEMORY STATE SENSING BASED ON CELL CAPACITANCE - A memory cell and method for operating a memory cell including a bidirectional access device and memory element electrically coupled in series. The bidirectional access device includes a tunneling capacitance. The memory element programmable to a first and second state by application of a first and second write voltage opposite in polarity to one another. The memory element has a lower capacitance in the first state than the second state. A read unit senses a transient read current due to a voltage drop upon application of a read voltage. Determining if the memory element is the first or second state is based on whether the read current is greater or less than a sense threshold. The sense threshold is based on a capacitance ratio between the first and second state. | 09-11-2014 |
20140256100 | ELECTRICAL COUPLING OF MEMORY CELL ACCESS DEVICES TO A WORD LINE - A memory array and a method for electrically coupling memory cell access devices to a word line. The memory array includes a source line electrically coupled to each source terminal of the memory cell access devices. The memory array also includes a first set of at least two vertical pillars positioned above and electrically coupled to the source line. A second set of vertical pillars electrically isolated from the source line and positioned such that the source line does not extend below the second set of vertical pillars is also included. Furthermore, gate terminals of the memory cell access devices laterally surround the first set of vertical pillars and the second set of vertical pillars. Finally, a first word line contact is positioned between two of the second set of vertical pillars. The first word line contact is electrically coupled to the gate terminals. | 09-11-2014 |
20140264497 | SELF-ALIGNED APPROACH FOR DRAIN DIFFUSION IN FIELD EFFECT TRANSISTORS - A method for doping terminals of a field-effect transistor (FET), the FET including a drain region, a source region, and a surround gate surrounding a channel region, the method including depositing a dopant-containing layer, such that the surround gate prevents the dopant-containing layer from contacting the channel region of the FET, the dopant-containing layer including a dopant. The dopant then diffuses the dopant from the dopant-containing layer into at least one of the drain region and source region of the FET. | 09-18-2014 |
20140264510 | MEMORY ARRAY WITH SELF-ALIGNED EPITAXIALLY GROWN MEMORY ELEMENTS AND ANNULAR FET - A system and method for fabricating a memory array device. An example memory array device includes a plurality of memory cells, each including a FET over a substrate and a memory element over the FET. Each memory element includes a plurality of epitaxially grown memory element layers. The memory array device includes a plurality of gate conductors configured a first axis, in parallel. Each gate conductor laterally surrounds a plurality of FETs of the memory cells along the first axis. The memory array device includes a plurality of bit lines configured along a second axis, in parallel, and electrically coupled to a plurality of memory elements along the second axis. Embodiments of the memory array preserve alignment of crystal lattices beginning from the bottom layers in the FET up to the top active layers in memory element, thus preserving crystal lattice alignment between transistor and memory element. | 09-18-2014 |
20140264512 | STRUCTURE AND FABRICATION OF MEMORY ARRAY WITH EPITAXIALLY GROWN MEMORY ELEMENTS AND LINE-SPACE PATTERNS - A system and method for fabricating a memory array device. An example memory array device includes a plurality of memory cells, each including a FET over a substrate and a memory element over the FET. Each memory element includes a plurality of epitaxially grown memory element layers. The memory elements formed utilizing two etches through all epitaxially grown layers. Each of these etches can be split to two separate processes specific to CMOS transistor etch and to memory element etch. The memory array device includes a plurality of gate conductors configured along a first axis, in parallel. Each FET of the memory cells adjacent to two gate conductors. The memory array device includes a plurality of bit lines configured along a second axis, in parallel, and electrically coupled to a plurality of memory elements along the second axis. | 09-18-2014 |
20140264557 | SELF-ALIGNED APPROACH FOR DRAIN DIFFUSION IN FIELD EFFECT TRANSISTORS - A method for doping terminals of a field-effect transistor (FET), the FET including a drain region, a source region, and a surround gate surrounding a channel region, the method including depositing a dopant-containing layer, such that the surround gate prevents the dopant-containing layer from contacting the channel region of the FET, the dopant-containing layer including a dopant. The dopant then diffuses the dopant from the dopant-containing layer into at least one of the drain region and source region of the FET. | 09-18-2014 |
20140273285 | MEMORY ARRAY WITH SELF-ALIGNED EPITAXIALLY GROWN MEMORY ELEMENTS AND ANNULAR FET - A system and method for fabricating a memory array device. An example memory array device includes a plurality of memory cells, each including a FET over a substrate and a memory element over the FET. Each memory element includes a plurality of epitaxially grown memory element layers. The memory array device includes a plurality of gate conductors configured a first axis, in parallel. Each gate conductor laterally surrounds a plurality of FETs of the memory cells along the first axis. The memory array device includes a plurality of bit lines configured along a second axis, in parallel, and electrically coupled to a plurality of memory elements along the second axis. Embodiments of the memory array preserve alignment of crystal lattices beginning from the bottom layers in the FET up to the top active layers in memory element, thus preserving crystal lattice alignment between transistor and memory element. | 09-18-2014 |
20140273286 | STRUCTURE AND FABRICATION OF MEMORY ARRAY WITH EPITAXIALLY GROWN MEMORY ELEMENTS AND LINE-SPACE PATTERNS - A system and method for fabricating a memory array device. An example memory array device includes a plurality of memory cells, each including a FET over a substrate and a memory element over the FET. Each memory element includes a plurality of epitaxially grown memory element layers. The memory elements formed utilizing two etches through all epitaxially grown layers. Each of these etches can be split to two separate processes specific to CMOS transistor etch and to memory element etch. The memory array device includes a plurality of gate conductors configured along a first axis, in parallel. Each FET of the memory cells adjacent to two gate conductors. The memory array device includes a plurality of bit lines configured along a second axis, in parallel, and electrically coupled to a plurality of memory elements along the second axis. | 09-18-2014 |
20140281162 | ADAPTIVE REFERENCE TUNING FOR ENDURANCE ENHANCEMENT OF NON-VOLATILE MEMORIES - A wear leveling technique is employed in a memory device so that the cycling history of a memory block is represented by the cycling history of a representative memory cell or a small number of representative memory cells. A control logic block tracks the cycling history of the one or more representative memory cells. A table tabulating the predicted shift in an optimal value for a reference variable for a sensing circuit as a function of cycling history is provided within the memory device. Prior to sensing a memory cell, the control logic block checks the total number of cycling in the one or more representative memory cells and adjusts the value for the reference variable in the sensing circuit, thereby providing an optimal value for the reference variable in the sensing circuit for each sensing cycle of the memory device. | 09-18-2014 |
20140281294 | ADAPTIVE REFERENCE TUNING FOR ENDURANCE ENHANCEMENT OF NON-VOLATILE MEMORIES - A wear leveling technique is employed in a memory device so that the cycling history of a memory block is represented by the cycling history of a representative memory cell or a small number of representative memory cells. A control logic block tracks the cycling history of the one or more representative memory cells. A table tabulating the predicted shift in an optimal value for a reference variable for a sensing circuit as a function of cycling history is provided within the memory device. Prior to sensing a memory cell, the control logic block checks the total number of cycling in the one or more representative memory cells and adjusts the value for the reference variable in the sensing circuit, thereby providing an optimal value for the reference variable in the sensing circuit for each sensing cycle of the memory device. | 09-18-2014 |
20140322907 | SELF-ALIGNED PROCESS TO FABRICATE A MEMORY CELL ARRAY WITH A SURROUNDING-GATE ACCESS TRANSISTOR - A method to prevent a gate contact from electrically connecting to a source contact for a plurality of memory cells on a substrate. The method includes depositing and etching gate material to partially fill a space between the pillars and to form a word line for the memory cells, etching a gate contact region for the word line between the pair of pillars, forming a spacer of electrically insulating material in the gate contact region, and depositing a gate contact between the pair of pillars to be in electrical contact with the gate material such that the spacer surrounds the gate contact. | 10-30-2014 |
20140374687 | RESISTIVE MEMORY WITH A STABILIZER - A resistive memory device and a method for fabricating the resistive memory device. The memory device includes a first electrode and a resistive memory element in electrical contact. The memory device also includes a non-programmable stabilizer element in electrical and thermal contact with the resistive memory element. The stabilizer element has at least one physical dimension based on a physical characteristic of the resistive memory element such that the maximum resistance of the stabilizer element is substantially less than the maximum resistance of the resistive memory element. | 12-25-2014 |
20140377929 | RESISTIVE MEMORY WITH A STABILIZER - A resistive memory device and a method for fabricating the resistive memory device. The memory device includes a first electrode and a resistive memory element in electrical contact. The memory device also includes a non-programmable stabilizer element in electrical and thermal contact with the resistive memory element. The stabilizer element has at least one physical dimension based on a physical characteristic of the resistive memory element such that the maximum resistance of the stabilizer element is substantially less than the maximum resistance of the resistive memory element. | 12-25-2014 |
20150023094 | DRIFT MITIGATION FOR MULTI-BITS PHASE CHANGE MEMORY - An RC-based sensing method and computer program product to effectively sense the cell resistance of a programmed Phase Change Material (PCM) memory cell. The sensing method ensures the same physical configuration of each cell (after programming): same amorphous volume, same trap density/distribution, etc. The sensing method is based on a metric: the RC based sense amplifier implements two trigger points. The measured time interval between these two points is used as the metric to determine whether the programmed cell state, e.g., resistance, is programmed into desired value. The RC-based sensing method is embedded into an iterative PCM cell programming technique to ensure a tight distribution of resistance at each level after programming; and ensure the probability of level aliasing is very small, leading to less problematic drift. | 01-22-2015 |