Patent application number | Description | Published |
20100308424 | Triple-Axis MEMS Accelerometer Having a Bottom Capacitor - An integrated circuit structure includes a substrate having a top surface; a first conductive layer over and contacting the top surface of the substrate; a dielectric layer over and contacting the first conductive layer, wherein the dielectric layer includes an opening exposing a portion of the first conductive layer; and a proof-mass in the opening and including a second conductive layer at a bottom of the proof-mass. The second conductive layer is spaced apart from the portion of the first conductive layer by an air space. Springs anchor the proof-mass to portions of the dielectric layer encircling the opening. The springs are configured to allow the proof-mass to make three-dimensional movements. | 12-09-2010 |
20110156245 | Method and Apparatus for Cooling an Integrated Circuit - An integrated circuit, a method of operating the integrated circuit, and a method of fabricating the integrated circuit are disclosed. According to one of the broader forms of the invention, a method and apparatus involve an integrated circuit that includes a heat transfer structure having a chamber that has a fluid disposed therein and that extends between a heat generating portion and a heat absorbing portion. Heat is absorbed into the fluid from the heat generating portion, and the fluid changes from a first phase to a second phase different from the first phase when the heat is absorbed. Heat is released from the fluid to the heat absorbing portion, and the fluid changes from the second phase to the first phase when the heat is released. | 06-30-2011 |
20110233621 | Wafer Level Packaging Bond - The present disclosure provides a method of bonding a plurality of substrates. In an embodiment, a first substrate includes a first bonding layer. The second substrate includes a second bonding layer. The first bonding layer includes silicon; the second bonding layer includes aluminum. The first substrate and the second substrate are bonded forming a bond region having an interface between the first bonding layer and the second bonding layer. A device having a bonding region between substrates is also provided. The bonding region includes an interface between a layer including silicon and a layer including aluminum. | 09-29-2011 |
20120025389 | Hermetic Wafer Level Packaging - Provided is a wafer level packaging. The packaging includes a first semiconductor wafer having a transistor device and a first bonding layer that includes a first material. The packaging includes a second semiconductor wafer having a second bonding layer that includes a second material different from the first material, one of the first and second materials being aluminum-based, and the other thereof being titanium-based. Wherein a portion of the second wafer is diffusively bonded to the first wafer through the first and second bonding layers. | 02-02-2012 |
20120043626 | MICROSTRUCTURE DEVICE WITH AN IMPROVED ANCHOR - The present disclosure provides a system of fabricating a microstructure device with an improved anchor. A method of fabricating a microstructure device with an improved anchor includes providing a substrate and forming an oxide layer on the substrate. Then, a cavity is etched in the oxide layer, such that the cavity includes a sidewall in the oxide layer. A microstructure device layer is then bonded to the oxide layer over the cavity. Forming a microstructure device, a trench is etched in the device layer to define an outer boundary of the microstructure device. In an embodiment, the outer boundary is substantially outside of the sidewall of the cavity. Then, the sidewall of the cavity is etched away through the trench in the device layer, to thereby suspend the microstructure device over the cavity. | 02-23-2012 |
20120061776 | WAFER LEVEL PACKAGING - A method of wafer level packaging includes providing a substrate including a buried oxide layer and a top oxide layer, and etching the substrate to form openings above the buried oxide layer and a micro-electro-mechanical systems (MEMS) resonator element between the openings, the MEMS resonator element enclosed within the buried oxide layer, the top oxide layer, and sidewall oxide layers. The method further includes filling the openings with polysilicon to form polysilicon electrodes adjacent the MEMS resonator element, removing the top oxide layer and the sidewall oxide layers adjacent the MEMS resonator element, bonding the polysilicon electrodes to one of a complementary metal-oxide semiconductor (CMOS) wafer or a carrier wafer, removing the buried oxide layer adjacent the MEMS resonator element, and bonding the substrate to a capping wafer to seal the MEMS resonator element between the capping wafer and one of the CMOS wafer or the carrier wafer. | 03-15-2012 |
20120068276 | MICROSTRUCTURE WITH AN ENHANCED ANCHOR - The present disclosure provides a microstructure device with an enhanced anchor and a narrow air gap. One embodiment of a microstructure device provided herein includes a layered wafer. The layered wafer includes a silicon handle layer, a buried oxide layer formed on the handle layer, and a silicon device layer formed on the buried oxide layer. A top oxide layer is formed on the device layer. The top oxide layer, the device layer, and the buried oxide layer are etched, thereby forming trenches to create an anchor and a microstructure device in the device layer. In process of fabricating the device, a thermal oxide layer is formed along sides of the microstructure device to enclose the microstructure device in the buried oxide layer, the top oxide layer and the thermal oxide layer. Then, a poly layer if formed to fill in the trenches and enclose the anchor. After the poly layer fills in the trenches, the oxide layers enclosing the microstructure device are etched away, releasing the microstructure device. | 03-22-2012 |
20120074554 | BOND RING FOR A FIRST AND SECOND SUBSTRATE - The present disclosure provides a device having a plurality of bonded substrates. The substrates are bonded by a first bond ring and a second bond ring. In an embodiment, the first bond ring is a eutectic bond and the second bond ring is at least one of an organic material and a eutectic bond. The second bond ring encircles the first bond ring. The first bond ring provides a hermetic region of the device. In a further embodiment, a plurality of wafers are bonded which include a third bond ring disposed at the periphery of the wafers. | 03-29-2012 |
20120074590 | MULTIPLE BONDING IN WAFER LEVEL PACKAGING - The present disclosure provides a method for fabricating a MEMS device including multiple bonding of substrates. In an embodiment, a method includes providing a micro-electro-mechanical systems (MEMS) substrate including a first bonding layer, providing a semiconductor substrate including a second bonding layer, and providing a cap including a third bonding layer. The method further includes bonding the MEMS substrate to the semiconductor substrate at the first and second bonding layers, and bonding the cap to the semiconductor substrate at the second and third bonding layers to hermetically seal the MEMS substrate between the cap and the semiconductor substrate. A MEMS device fabricated by the above method is also provided. | 03-29-2012 |
20120086126 | PACKAGE SYSTEMS AND MANUFACTURING METHODS THEREOF - A package system includes a first substrate and a second substrate. The second substrate is electrically coupled with the first substrate. The second substrate includes at least one first opening. At least one electrical bonding material is disposed between the first substrate and the second substrate. A first portion of the at least one electrical bonding material is at least partially filled in the at least one first opening. | 04-12-2012 |
20120086127 | PACKAGE SYSTEMS AND MANUFACTURING METHODS THEREOF - A package system includes a first substrate. A second substrate is electrically coupled with the first substrate. At least one electrical bonding material is disposed between the first substrate and the second substrate. The at least one electrical bonding material includes a eutectic bonding material. The eutectic bonding material includes a metallic material and a semiconductor material. The metallic material is disposed adjacent to a surface of the first substrate. The metallic material includes a first pad and at least one first guard ring around the first pad. | 04-12-2012 |
20120098074 | MEMS DEVICE WITH RELEASE APERTURE - The present disclosure provides a method of fabricating a micro-electro-mechanical systems (MEMS) device. In an embodiment, a method includes providing a substrate including a first sacrificial layer, forming a micro-electro-mechanical systems (MEMS) structure above the first sacrificial layer, and forming a release aperture at substantially a same level above the first sacrificial layer as the MEMS structure. The method further includes forming a second sacrificial layer above the MEMS structure and within the release aperture, and forming a first cap over the second sacrificial layer and the MEMS structure, wherein a leg of the first cap is disposed between the MEMS structure and the release aperture. The method further includes removing the first sacrificial layer, removing the second sacrificial layer through the release aperture, and plugging the release aperture. A MEMS device formed by such a method is also provided. | 04-26-2012 |
20120125747 | MEMS SWITCH WITH REDUCED DIELECTRIC CHARGING EFFECT - The present disclosure provides in one embodiment, a semiconductor device that includes a MEMS switch having a substrate, a first dielectric layer disposed above the substrate, and a bottom signal electrode, a bump, and a bottom actuation electrode disposed above the first dielectric layer. The MEMS switch further includes a second dielectric layer enclosing the bottom signal electrode, and a movable member including a top signal electrode disposed above the bottom signal electrode and a top actuation electrode disposed above the bottom actuation electrode and the bump, wherein the top actuation electrode is electrically coupled to the bump. A method of fabricating a MEMS switch is also disclosed. | 05-24-2012 |
20120148870 | SELF-REMOVAL ANTI-STICTION COATING FOR BONDING PROCESS - A bond free of an anti-stiction layer and bonding method is disclosed. An exemplary method includes forming a first bonding layer; forming an interlayer over the first bonding layer; forming an anti-stiction layer over the interlayer; and forming a liquid from the first bonding layer and interlayer, such that the anti-stiction layer floats over the first bonding layer. A second bonding layer can be bonded to the first bonding layer while the anti-stiction layer floats over the first bonding layer, such that a bond between the first and second bonding layers is free of the anti-stiction layer. | 06-14-2012 |
20130099332 | WAFER LEVEL PACKAGING - A method of wafer level packaging includes providing a substrate including a buried oxide layer and a top oxide layer, and etching the substrate to form openings above the buried oxide layer and a micro-electro-mechanical systems (MEMS) resonator element between the openings, the MEMS resonator element enclosed within the buried oxide layer, the top oxide layer, and sidewall oxide layers. The method further includes filling the openings with polysilicon to form polysilicon electrodes adjacent the MEMS resonator element, removing the top oxide layer and the sidewall oxide layers adjacent the MEMS resonator element, bonding the polysilicon electrodes to one of a complementary metal-oxide semiconductor (CMOS) wafer or a carrier wafer, removing the buried oxide layer adjacent the MEMS resonator element, and bonding the substrate to a capping wafer to seal the MEMS resonator element between the capping wafer and one of the CMOS wafer or the carrier wafer. | 04-25-2013 |
20130099355 | MEMS Structures and Methods for Forming the Same - A method includes forming a MEMS device, forming a bond layer adjacent the MEMS device, and forming a protection layer over the bond layer. The steps of forming the bond layer and the protection layer include in-situ deposition of the bond layer and the protection layer | 04-25-2013 |
20130102101 | Wafer Level Packaging - A method of wafer level packaging includes providing a substrate including a buried oxide layer and a top oxide layer, and etching the substrate to form openings above the buried oxide layer and a micro-electro-mechanical systems (MEMS) resonator element between the openings, the MEMS resonator element enclosed within the buried oxide layer, the top oxide layer, and sidewall oxide layers. The method further includes filling the openings with polysilicon to form polysilicon electrodes adjacent the MEMS resonator element, removing the top oxide layer and the sidewall oxide layers adjacent the MEMS resonator element, bonding the polysilicon electrodes to one of a complementary metal-oxide semiconductor (CMOS) wafer or a carrier wafer, removing the buried oxide layer adjacent the MEMS resonator element, and bonding the substrate to a capping wafer to seal the MEMS resonator element between the capping wafer and one of the CMOS wafer or the carrier wafer. | 04-25-2013 |
20130105868 | CMOS COMPATIBLE BIOFET | 05-02-2013 |
20130126989 | Microstructure Device with an Improved Anchor - A microelectromechanical system (MEMS) device includes a substrate and an oxide layer formed on the substrate. A cavity is etched in the oxide layer. A microstructure device layer is bonded to the oxide layer, over the cavity. The microstructure device layer includes a substantially solid microstructure MEMS device formed in the microstructure device layer and suspended over a portion of the cavity. An anchor is formed in the device layer and configured to support the microstructure device, the anchor having an undercut in the oxide layer. The undercut has a length along the anchor that is less than one-half a length of an outer boundary dimension of the microstructure MEMS device. | 05-23-2013 |
20130200438 | SYSTEMS AND METHODS FOR SIGNAL AMPLIFICATION WITH A DUAL-GATE BIO FIELD EFFECT TRANSISTOR - The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device may include a substrate; a gate structure disposed on a first surface of the substrate and an interface layer formed on the second surface of the substrate. The interface layer may allow for a receptor to be placed on the interface layer to detect the presence of a biomolecule or bio-entity. An amplification factor of the BioFET device may be provided by a difference in capacitances associated with the gate structure on the first surface and with the interface layer formed on the second surface. | 08-08-2013 |
20130203199 | Methods of Bonding Caps for MEMS Devices - A method includes bonding a first bond layer to a second bond layer through eutectic bonding. The step of bonding includes heating the first bond layer and the second bond layer to a temperature higher than a eutectic temperature of the first bond layer and the second bond layer, and performing a pumping cycle. The pumping cycle includes applying a first force to press the first bond layer and the second bond layer against each other. After the step of applying the first force, a second force lower than the first force is applied to press the first bond layer and the second bond layer against each other. After the step of applying the second force, a third force higher than the second force is applied to press the first bond layer and the second bond layer against each other. | 08-08-2013 |
20130285170 | MULTIPLE BONDING IN WAFER LEVEL PACKAGING - A MEMS device is described. The device includes a micro-electro-mechanical systems (MEMS) substrate including a first bonding layer, a semiconductor substrate including a second bonding layer, and a cap including a third bonding layer, the cap coupled to the semiconductor substrate by bonding the second bonding layer to the third bonding layer. The first bonding layer includes silicon, the semiconductor substrate is electrically coupled to the MEMS substrate by bonding the first bonding layer to the second bonding layer, and the MEMS substrate is hermetically sealed between the cap and the semiconductor substrate. | 10-31-2013 |
20130334620 | MEMS Devices and Fabrication Methods Thereof - A method for fabricating a MEMS device includes providing a micro-electro-mechanical system (MEMS) substrate having a sacrificial layer on a first side, providing a carrier including a plurality of cavities, bonding the first side of the MEMS substrate on the carrier, forming a first bonding material layer on a second side of the MEMS substrate, applying a sacrificial layer removal process to the MEMS substrate, providing a semiconductor substrate including a second bonding material layer and bonding the semiconductor substrate on the second side of the MEMS substrate. | 12-19-2013 |
20140015069 | MEMS Devices, Packaged MEMS Devices, and Methods of Manufacture Thereof - MEMS devices, packaged MEMS devices, and methods of manufacture thereof are disclosed. In one embodiment, a microelectromechanical system (MEMS) device includes a first MEMS functional structure and a second MEMS functional structure. An interior region of the second MEMS functional structure has a pressure that is different than a pressure of an interior region of the first MEMS functional structure. | 01-16-2014 |
20140035158 | Integrated Semiconductor Device and Wafer Level Method of Fabricating the Same - The present disclosure provides one embodiment of a stacked semiconductor device. The stacked semiconductor device includes a first substrate; a first bond pad over the first substrate; a second substrate including a second electrical device fabricated thereon; a second bond pad over the second electrical device over the second substrate, the second bond pad electrically connecting to the second electrical device; a second insulation layer over the second bond pad having a top surface, the second insulation layer being bonded toward the first bond pad of the first substrate; and a through-substrate-via (“TSV”) extending from a surface opposite to the first bond pad through the first substrate and through the top surface of the second insulation layer to the second bond pad. | 02-06-2014 |
20140042562 | MEMS Devices and Methods for Forming the Same - A device includes a Micro-Electro-Mechanical System (MEMS) wafer having a MEMS device therein. The MEMS device includes a movable element, and first openings in the MEMS wafer. The movable element is disposed in the first openings. A carrier wafer is bonded to the MEMS wafer. The carrier wafer includes a second opening connected to the first openings, wherein the second opening includes an entry portion extending from a surface of the carrier wafer into the carrier wafer, and an inner portion wider than the entry portion, wherein the inner portion is deeper in the carrier wafer than the entry portion. | 02-13-2014 |
20140054461 | LIGHT DETECTOR WITH GE FILM - A light detector includes a first light sensor and a second light sensor to detect incident light. A Ge film is disposed over the first light sensor to pass infra-red (IR) wavelength light and to block visible wavelength light. The Ge film does not cover the second light sensor. | 02-27-2014 |
20140103461 | MEMS Devices and Fabrication Methods Thereof - A method for fabricating a MEMS device includes providing a micro-electro-mechanical system (MEMS) substrate having a sacrificial layer on a first side, providing a carrier including a plurality of cavities, bonding the first side of the MEMS substrate on the carrier, forming a first bonding material layer on a second side of the MEMS substrate, applying a sacrificial layer removal process to the MEMS substrate, providing a semiconductor substrate including a second bonding material layer and bonding the semiconductor substrate on the second side of the MEMS substrate. | 04-17-2014 |
20140134748 | INTEGRATED ELECTRO-MICROFLUIDIC PROBE CARD, SYSTEM AND METHOD FOR USING THE SAME - The present disclosure provides a biological field effect transistor (BioFET) device testing and processing methods, system and apparatus. A wafer-level bio-sensor processing tool includes a wafer stage, an integrated electro-microfluidic probe card, and a fluid supply and return. The integrated electro-microfluidic probe card includes a fluidic mount that may be transparent, a microfluidic channels in the fluidic mount, at least one microfluidic probe and a number of electronic probe tips at the bottom of the fluidic mount, fluidic and electronic input and output ports on the sides of the fluidic mount, and at least one handle lug on the fluidic mount. The method includes aligning a wafer, mounting the integrated electro-microfluidic probe card, flowing a test fluid, and measuring electrical properties. The tool may also be used for stamping or printing a fluid in the device area on the wafer. | 05-15-2014 |
20140138853 | WAFER LEVEL PACKAGING BOND - A device is described in one embodiment that includes a micro-electro-mechanical systems (MEMS) device disposed on a first substrate and a semiconductor device disposed on a second substrate. A bond electrically connects the MEMS device and the semiconductor device. The bond includes an interface between a first bonding layer including silicon on the first substrate and a second bonding layer including aluminum on the second substrate. The physical interface between the aluminum and silicon (e.g., amorphous silicon) can provide an electrical connection. | 05-22-2014 |
20140151755 | BACKSIDE CMOS COMPATIBLE BIOFET WITH NO PLASMA INDUCED DAMAGE - The present disclosure provides a bio-field effect transistor (BioFET) device and methods of fabricating a BioFET and a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device includes a gate structure disposed on a first surface of a substrate and an interface layer formed on a second surface of the substrate. The substrate is thinned from the second surface to expose a channel region before forming the interface layer. | 06-05-2014 |
20140154841 | Hermetic Wafer Level Packaging - Provided is a wafer level packaging. The packaging includes a first semiconductor wafer having a transistor device and a first bonding layer that includes a first material. The packaging includes a second semiconductor wafer having a second bonding layer that includes a second material different from the first material, one of the first and second materials being aluminum-based, and the other thereof being titanium-based. Wherein a portion of the second wafer is diffusively bonded to the first wafer through the first and second bonding layers. | 06-05-2014 |
20140170849 | PACKAGE SYSTEMS AND MANUFACTURING METHODS THEREOF - A method of forming a package system includes providing a first substrate having a metallic pad and at least one metallic guard ring. The method further includes bonding the metallic pad of the first substrate with a semiconductor pad of a second substrate, wherein the at least one metallic guard ring is configured to at least partially interact with the semiconductor pad to form at least a first portion of an electrical bonding material between the first and second substrates. | 06-19-2014 |
20140183611 | METHOD TO INTEGRATE DIFFERENT FUNCTION DEVICES FABRICATED BY DIFFERENT PROCESS TECHNOLOGIES - The present disclosure is directed to an apparatus and method for manufacture thereof. The apparatus includes a first passive substrate bonded to a second active substrate by a conductive metal interface. The conductive metal interface allows for integration of different function devices at a wafer level. | 07-03-2014 |
20140191341 | Method and Apparatus for a Semiconductor Structure - A semiconductor structure may include a first device having first surface with a first bonding layer formed thereon and a second device having a first surface with a second bonding layer formed thereon. The first bonding layer may provide an electrically conductive path to at least one electrical device in the first device. The second bonding layer may provide an electrically conductive path to at least one electrical device in the second device. One of the first or the second devices may include MEMS electrical devices. The first and/or the second bonding layers may be formed of a getter material, which may provide absorption for outgassing. | 07-10-2014 |
20140206123 | Dual Layer Microelectromechanical Systems Device and Method of Manufacturing Same - Exemplary microelectromechanical system (MEMS) devices, and methods for fabricating such are disclosed. An exemplary method includes providing a silicon-on-insulator (SOI) substrate, wherein the SOI substrate includes a first silicon layer separated from a second silicon layer by an insulator layer; processing the first silicon layer to form a first structure layer of a MEMS device; bonding the first structure layer to a substrate; and processing the second silicon layer to form a second structure layer of the MEMS device. | 07-24-2014 |
20140239986 | PROCESS CONTROL MONITORING FOR BIOCHIPS - The present disclosure provides a biosensor device wafer testing and processing methods, system and apparatus. The biosensor device wafer includes device areas separated by scribe lines. A number of test areas that allow fluidic electrical testing are embedded in scribe lines or in device areas. An integrated electro-microfluidic probe card includes a fluidic mount that may be transparent, a microfluidic channels in the fluidic mount in a testing portion, at least one microfluidic probe and a number of electronic probe tips at the bottom of the fluidic mount, fluidic and electronic input and output ports on the sides of the fluidic mount, and at least one handle lug on the fluidic mount. The method includes aligning a wafer, mounting the integrated electro-microfluidic probe card, flowing one or more test fluids in series, and measuring and analyzing electrical properties to determine process qualities and an acceptance level of the wafer. | 08-28-2014 |
20140252358 | Methods and Apparatus for MEMS Devices with Increased Sensitivity - Methods and apparatus for forming MEMS devices. An apparatus includes at least a portion of a semiconductor substrate having a first thickness and patterned to form a moveable mass; a moving sense electrode forming the first plate of a first capacitance; at least one anchor patterned from the semiconductor substrate and having a portion that forms the second plate of the first capacitance and spaced by a first gap from the first plate; a layer of semiconductor material of a second thickness patterned to form a first electrode forming a first plate of a second capacitance and further patterned to form a second electrode overlying the at least one anchor and forming a second plate spaced by a second gap that is less than the first gap; wherein a total capacitance is formed that is the sum of the first capacitance and the second capacitance. Methods are disclosed. | 09-11-2014 |
20140252421 | Backside CMOS Compatible BioFET with No Plasma Induced Damage - The present disclosure provides a bio-field effect transistor (BioFET) device and methods of fabricating a BioFET and a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device includes a gate structure disposed on a first surface of a substrate and an interface layer formed on a second surface of the substrate. The substrate is thinned from the second surface to expose a channel region before forming the interface layer. | 09-11-2014 |
20140252508 | MEMS Device with a Capping Substrate - An integrated circuit device includes a dielectric layer disposed onto a first substrate, the dielectric layer having a sacrificial cavity formed therein. The circuit also includes a membrane layer formed onto the dielectric layer and suspended over the sacrificial cavity, and a capping substrate bonded to the membrane layer such that a second cavity is formed, the second cavity being connected to the sacrificial cavity though a via formed into the membrane layer. | 09-11-2014 |
20140264467 | BACKSIDE SENSING BIOFET WITH ENHANCED PERFORMANCE - The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device includes a substrate, a transistor structure having a treated layer adjacent to the channel region, an isolation layer, and a dielectric layer in an opening of the isolation layer on the treated layer. The dielectric layer and the treated layer are disposed on opposite side of the transistor from a gate structure. The treated layer may be a lightly doped channel layer or a depleted layer. | 09-18-2014 |
20140264468 | BIOFET WITH INCREASED SENSING AREA - The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device includes a substrate, a transistor structure, an isolation layer, an interface layer in an opening of the isolation layer, and a metal crown structure over the interface layer. The interface layer and the metal crown structure are disposed on opposite side of the transistor from a gate structure. | 09-18-2014 |
20140264474 | STACKED SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME RELATED CASES - A stacked semiconductor device includes a CMOS device and a MEMS device. The CMOS device includes a multilayer interconnect with metal elements disposed over the multilayer interconnect. The MEMS device includes metal sections with a first dielectric layer disposed over the metal sections. A cavity in the first dielectric layer exposes portions of the metal sections. A dielectric stop layer is disposed at least over the interior surface of the cavity. A movable structure is disposed over a front surface of the first dielectric layer and suspending over the cavity. The movable structure includes a second dielectric layer over the front surface of the first dielectric layer and suspending over the cavity, metal features over the second dielectric layer, and a flexible dielectric membrane over the metal features. The CMOS device is bonded to the MEMS device with the metal elements toward the flexible dielectric membrane. | 09-18-2014 |
20140264648 | MEMS Integrated Pressure Sensor Devices and Methods of Forming Same - A method embodiment includes providing a micro-electromechanical (MEMS) wafer including a polysilicon layer having a first and a second portion. A carrier wafer is bonded to a first surface of the MEMS wafer. Bonding the carrier wafer creates a first cavity. A first surface of the first portion of the polysilicon layer is exposed to a pressure level of the first cavity. A cap wafer is bonded to a second surface of the MEMS wafer opposite the first surface of the MEMS wafer. The bonding the cap wafer creates a second cavity comprising the second portion of the polysilicon layer and a third cavity. A second surface of the first portion of the polysilicon layer is exposed to a pressure level of the third cavity. The first cavity or the third cavity is exposed to an ambient environment. | 09-18-2014 |
20140264653 | MEMS Pressure Sensor and Microphone Devices Having Through-Vias and Methods of Forming Same - A method embodiment includes providing a MEMS wafer. A portion of the MEMS wafer is patterned to provide a first membrane for a microphone device and a second membrane for a pressure sensor device. A carrier wafer is bonded to the MEMS wafer. The carrier wafer is etched to expose the first membrane and a first surface of the second membrane to an ambient environment. A MEMS structure is formed in the MEMS wafer. A cap wafer is bonded to a side of the MEMS wafer opposing the carrier wafer to form a first sealed cavity including the MEMS structure and a second sealed cavity including a second surface of the second membrane for the pressure sensor device. The cap wafer comprises an interconnect structure. A through-via electrically connected to the interconnect structure is formed in the cap wafer. | 09-18-2014 |
20140264661 | MEMS Devices and Methods for Forming Same - Embodiments of the present disclosure include MEMS devices and methods for forming MEMS devices. An embodiment is a method for forming a microelectromechanical system (MEMS) device, the method including forming a MEMS wafer having a first cavity, the first cavity having a first pressure, and bonding a carrier wafer to a first side of the MEMS wafer, the bonding forming a second cavity, the second cavity having a second pressure, the second pressure being greater than the first pressure. The method further includes bonding a cap wafer to a second side of the MEMS wafer, the second side being opposite the first side, the bonding forming a third cavity, the third cavity having a third pressure, the third pressure being greater than the first pressure and less than the second pressure. | 09-18-2014 |
20140264662 | MEMS Integrated Pressure Sensor and Microphone Devices and Methods of Forming Same - A method embodiment for forming a micro-electromechanical (MEMS) device includes providing a MEMS wafer, wherein a portion of the MEMS wafer is patterned to provide a first membrane for a microphone device and a second membrane for a pressure sensor device. A carrier wafer is bonded to the MEMS wafer, and the carrier wafer is etched to expose the first membrane for the microphone device to an ambient environment. A MEMS substrate is patterned and portions of a first sacrificial layer are removed of the MEMS wafer to form a MEMS structure. A cap wafer is bonded to a side of the MEMS wafer opposing the carrier wafer to form a first sealed cavity including the MEMS structure. A second sealed cavity and a cavity exposed to an ambient environment on opposing sides of the second membrane for the pressure sensor device are formed. | 09-18-2014 |
20140264744 | STACKED SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A stacked semiconductor device includes a first substrate. A multilayer interconnect is disposed over the first substrate. Metal sections are disposed over the multilayer interconnect. First bonding features are over the metal sections. A second substrate has a front surface. A cavity extends from the front surface into a depth D in the second substrate. The cavity has an interior surface. A stop layer is disposed over the interior surface of the cavity. A movable structure is disposed over the front surface of the second substrate and suspending over the cavity. The movable structure includes a dielectric membrane, metal units over the dielectric membrane and a cap dielectric layer over the metal units. Second bonding features are over the cap dielectric layer and bonded to the first bonding features. The second bonding features extend through the cap dielectric layer and electrically coupled to the metal units. | 09-18-2014 |
20140270272 | Structure and Method for Integrated Microphone - The present disclosure provides one embodiment of an integrated microphone structure. The integrated microphone structure includes a first silicon substrate patterned as a first plate; a silicon oxide layer formed on one side of the first silicon substrate; a second silicon substrate bonded to the first substrate through the silicon oxide layer such that the silicon oxide layer is sandwiched between the first and second silicon substrates; and a diaphragm secured on the silicon oxide layer and disposed between the first and second silicon substrates, wherein the first plate and the diaphragm are configured to form a capacitive microphone. | 09-18-2014 |
20140272719 | SURFACE MODIFICATION, FUNCTIONALIZATION AND INTEGRATION OF MICROFLUIDICS AND BIOSENSOR TO FORM A BIOCHIP - The present disclosure provides methods of fabricating a biochip. The biochip includes a fluidic part, having through-substrate holes as inlets and outlets, and a sensing part bonded together using a bonding material. One or both of the parts has microfluidic channel patterns and one or more patterned surface modification layers formed using different methods to provide surface property for binding bioreceptors and for flowing analytes. The patterning includes lithography, etching, washing, selective depositing using printing or self-assembly of surface chemistry. | 09-18-2014 |
20140273281 | METHOD FOR FORMING BIOCHIPS AND BIOCHIPS WITH NON-ORGANIC LANDINGS FOR IMPROVED THERMAL BUDGET - The present disclosure provides biochips and methods of fabricating biochips. The method includes combining three portions: a transparent substrate, a first substrate with microfluidic channels therein, and a second substrate. Through-holes for inlet and outlet are formed in the transparent substrate or the second substrate. Various non-organic landings with support medium for bio-materials to attach are formed on the first substrate and the second substrate before they are combined. In other embodiments, the microfluidic channel is formed of an adhesion layer between a transparent substrate and a second substrate with landings on the substrates. | 09-18-2014 |
20140319631 | MEMS Integrated Pressure Sensor Devices having Isotropic Cavities and Methods of Forming Same - A method embodiment includes providing a MEMS wafer comprising an oxide layer, a MEMS substrate, a polysilicon layer. A carrier wafer comprising a first cavity formed using isotropic etching is bonded to the MEMS, wherein the first cavity is aligned with an exposed first portion of the polysilicon layer. The MEMS substrate is patterned, and portions of the sacrificial oxide layer are removed to form a first and second MEMS structure. A cap wafer including a second cavity is bonded to the MEMS wafer, wherein the bonding creates a first sealed cavity including the second cavity aligned to the first MEMS structure, and wherein the second MEMS structure is disposed between a second portion of the polysilicon layer and the cap wafer. Portions of the carrier wafer are removed so that first cavity acts as a channel to ambient pressure for the first MEMS structure. | 10-30-2014 |
20140357007 | METHOD OF FORMING A BOND RING FOR A FIRST AND SECOND SUBSTRATE - One method includes providing a first substrate; the first substrate may include a first MEMS device and a second MEMS device. A second substrate is also provided. The first substrate is bonded to the second substrate. The bonding may include forming a first bond ring around the first MEMS device and forming a second bond ring around the second MEMS device, wherein the second bond ring also encircles the first bond ring. In an embodiment, the eutectic point of the materials of the second bond ring is not reached during the bonding. | 12-04-2014 |
20150053925 | Top-Down Fabrication Method for Forming a Nanowire Transistor Device - The present disclosure relates to a top-down method of forming a nanowire structure extending between source and drain regions of a nanowire transistor device, and an associated apparatus. In some embodiments, the method provides a substrate having a device layer disposed over a first dielectric layer. The device layer has a source region and a drain region separated by a device material. The first dielectric layer has an embedded gate structure abutting the device layer. One or more masking layers are selectively formed over the device layer to define a nanowire structure. The device layer is then selectively etched according to the one or more masking layers to form a nanowire structure at a position between the source region and the drain region. By forming the nanowire structure through a masking and etch process, the nanowire structure is automatically connected to the source and drain regions. | 02-26-2015 |
20150060954 | CMOS-MEMS Integrated Flow for Making a Pressure Sensitive Transducer - A sensor is made up of two substrates which are adhered together. A first substrate includes a pressure-sensitive micro-electrical-mechanical (MEMS) structure and a conductive contact structure that protrudes outwardly beyond a first face of the first substrate. A second substrate includes a complementary metal oxide semiconductor (CMOS) device and a receiving structure made up of sidewalls that meet a conductive surface which is recessed from a first face of the second substrate. A conductive bonding material physically adheres the conductive contact structure to the conductive surface and electrically couples the MEMS structure to the CMOS device. | 03-05-2015 |
20150076710 | INTEGRATED SEMICONDUCTOR DEVICE AND WAFER LEVEL METHOD OF FABRICATING THE SAME - The present disclosure provides one embodiment of a stacked semiconductor device. The stacked semiconductor device includes a first substrate; a first bond pad over the first substrate; a second substrate including a second electrical device fabricated thereon; a second bond pad over the second electrical device over the second substrate, the second bond pad electrically connecting to the second electrical device; a second insulation layer over the second bond pad having a top surface, the second insulation layer being bonded toward the first bond pad of the first substrate; and a through-substrate-via (“TSV”) extending from a surface opposite to the first bond pad through the first substrate and through the top surface of the second insulation layer to the second bond pad. | 03-19-2015 |
20150079704 | FLUID DEPOSITION APPARTUS AND METHOD - The present disclosure relates to a micro-fluidic probe card that deposits a fluidic chemical onto a substrate with a minimal amount of fluidic chemical waste, and an associated method of operation. In some embodiments, the micro-fluidic probe card has a probe card body with a first side and a second side. A sealant element, which contacts a substrate, is connected to the second side of the probe card body in a manner that forms a cavity within an interior of the sealant element. A fluid inlet, which provides a fluid from a processing tool to the cavity, is a first conduit extending between the first side and the second side of the probe card body. A fluid outlet, which removes the fluid from the cavity, is a second conduit extending between the first side and the second side of the probe card body. | 03-19-2015 |
20150091153 | WAFER LEVEL SEALING METHODS WITH DIFFERENT VACUUM LEVELS FOR MEMS SENSORS - The present disclosure relates to a method of forming a plurality of MEMs device having a plurality of cavities with different pressures on a wafer package system, and an associated apparatus. In some embodiments, the method is performed by providing a work-piece having a plurality of microelectromechanical system (MEMs) devices. A cap wafer is bonded onto the work-piece in a first ambient environment having a first pressure. The bonding forms a plurality of cavities abutting the plurality of MEMs devices, which are held at the first pressure. One or more openings are formed in one or more of the plurality of cavities leading to a gas flow path that could be held at a pressure level different from the first pressure. The one or more openings in the one or more of the plurality of cavities are then sealed in a different ambient environment having a different pressure, thereby causing the one or more of the plurality of cavities to be held at the different pressure. | 04-02-2015 |
20150097215 | MECHANISMS FOR FORMING MICRO-ELECTRO MECHANICAL SYSTEM DEVICE - Embodiments of mechanisms for forming a micro-electro mechanical system (MEMS) device are provided. The MEMS device includes a CMOS substrate and a MEMS substrate bonded with the CMOS substrate. The CMOS substrate includes a semiconductor substrate, a first dielectric layer formed over the semiconductor substrate, and a plurality of conductive pads formed in the first dielectric layer. The MEMS substrate includes a semiconductor layer having a movable element and a second dielectric layer formed between the semiconductor layer and the CMOS substrate. The MEMS substrate also includes a closed chamber surrounding the movable element. The MEMS substrate further includes a blocking layer formed between the closed chamber and the first dielectric layer of the CMOS substrate. The blocking layer is configured to block gas, coming from the first dielectric layer, from entering the closed chamber. | 04-09-2015 |
20150125872 | FET SENSING CELL AND METHOD OF IMPROVING SENSITIVITY OF THE SAME - The present disclosure provides a device, such as a FET sensing cell, which includes a first dielectric layer over a substrate, an active layer over the first dielectric layer, a source region in the active layer, a drain region in the active layer, a channel region in the active layer situated between the source region and the drain region, a sensing film over the channel region, a second dielectric layer over the active layer, wherein an opening is formed in the second dielectric layer and the sensing film is located within the opening, a first electrode located within the second dielectric layer and a fluidic gate region located over the second dielectric layer and extending into the opening. The present disclosure also provides a method for improving the sensitivity of a device by adjusting a sensing value. | 05-07-2015 |
20150129936 | Biosensor Device and Related Method - A device includes a biosensor, a sensing circuit electrically connected to the biosensor, a quantizer electrically connected to the sensing circuit, a digital filter electrically connected to the quantizer, a selective window electrically connected to the digital filter, and a decision unit electrically connected to the selective window. | 05-14-2015 |
20150137276 | MECHANISMS FOR FORMING MICRO-ELECTRO MECHANICAL SYSTEM DEVICE - Embodiments of mechanisms for forming a micro-electro mechanical system (MEMS) device are provided. The MEMS device includes a CMOS substrate, a cap substrate, and a MEMS substrate bonded between the CMOS substrate and the cap substrate. The MEMS substrate includes a first movable element and a second movable element. The MEMS device also includes a first closed chamber and a second closed chamber, which are between the MEMS substrate and the cap substrate. The first movable element is in the first closed chamber, and the second movable element is in the second closed chamber. A first pressure of the first closed chamber is higher than a second pressure of the second closed chamber. | 05-21-2015 |
20150137280 | STRUCTURES AND FORMATION METHODS OF MICRO-ELECTRO MECHANICAL SYSTEM DEVICE - A structure and a formation method of a micro-electro mechanical system (MEMS) device are provided. The MEMS device includes a cap substrate and a MEMS substrate bonded with the cap substrate. The MEMS substrate includes a first movable element and a second movable element. The MEMS device also includes a first enclosed space surrounded by the MEMS substrate and the cap substrate, and the first movable element is in the first enclosed space. The MEMS device further includes a second enclosed space surrounded by the MEMS substrate and the cap substrate, and the second movable element is in the second enclosed space. In addition, the MEMS device includes a pressure-changing layer in the first enclosed space. | 05-21-2015 |
20150137283 | MEMS Devices, Packaged MEMS Devices, and Methods of Manufacture Thereof - MEMS devices, packaged MEMS devices, and methods of manufacture thereof are disclosed. In one embodiment, a microelectromechanical system (MEMS) device includes a first MEMS functional structure and a second MEMS functional structure. An interior region of the second MEMS functional structure has a pressure that is different than a pressure of an interior region of the first MEMS functional structure. | 05-21-2015 |
20150139857 | BIOCHIP WITH BIOSENSORS AND FLUIDIC DEVICES - A biochip includes a substrate, where the substrate includes at least one hole extending from a first surface of the substrate to a second surface of the substrate opposite the first surface, and where the substrate comprises a microfluidic channel pattern. The biochip further includes a surface modification layer over the substrate. Additionally, the biochip includes a sensing wafer bonded to the substrate, where the sensing wafer has one or more modified surface patterns having different surface properties from each other. | 05-21-2015 |
20150160323 | Biosensor Calibration System and Related Method - A device includes a first biosensor of a biosensor array; a second biosensor of a biosensor array; a readout circuit electrically connected to the biosensor array; a decoder electrically connected to the biosensor array; a voltage generator electrically connected to the biosensor array; and a decision system electrically connected to the voltage generator and the readout circuit. | 06-11-2015 |
20150175407 | MICRO ELECTROMECHANICAL SYSTEM SENSOR AND METHOD OF FORMING THE SAME - A micro electromechanical system (MEMS) device includes a MEMS section attached to a substrate, and a cap bonded to a first surface of the substrate. The MEMS device further includes a carrier bonded to a second surface of the substrate opposite the first surface, wherein the carrier is free of active devices, and the cap and the carrier define a vacuum region surrounding the MEMS section. The MEMS device further includes a bond pad on a surface of the carrier opposite the MEMS section, wherein the bond pad is electrically connected to the MEMS section. | 06-25-2015 |
20150197419 | MEMS DEVICES AND METHODS FOR FORMING SAME - An embodiment is MEMS device including a first MEMS die having a first cavity at a first pressure, a second MEMS die having a second cavity at a second pressure, the second pressure being different from the first pressure, and a molding material surrounding the first MEMS die and the second MEMS die, the molding material having a first surface over the first and the second MEMS dies. The device further includes a first set of electrical connectors in the molding material, each of the first set of electrical connectors coupling at least one of the first and the second MEMS dies to the first surface of the molding material, and a second set of electrical connectors over the first surface of the molding material, each of the second set of electrical connectors being coupled to at least one of the first set of electrical connectors. | 07-16-2015 |
20150246807 | MEMS Integrated Pressure Sensor Devices and Methods of Forming Same - A method embodiment includes providing a micro-electromechanical (MEMS) wafer including a polysilicon layer having a first and a second portion. A carrier wafer is bonded to a first surface of the MEMS wafer. Bonding the carrier wafer creates a first cavity. A first surface of the first portion of the polysilicon layer is exposed to a pressure level of the first cavity. A cap wafer is bonded to a second surface of the MEMS wafer opposite the first surface of the MEMS wafer. The bonding the cap wafer creates a second cavity comprising the second portion of the polysilicon layer and a third cavity. A second surface of the first portion of the polysilicon layer is exposed to a pressure level of the third cavity. The first cavity or the third cavity is exposed to an ambient environment. | 09-03-2015 |
20150251895 | STACKED SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME - A stacked semiconductor structure includes a first substrate. A multilayer interconnect is disposed over the first substrate. Metal sections are disposed over the multilayer interconnect. First bonding features are over the metal sections. A second substrate has a front surface. A cavity extends from the front surface into a depth D in the second substrate. A movable structure is disposed over the front surface of the second substrate and suspending over the cavity. The movable structure includes a dielectric membrane, metal units over the dielectric membrane and a cap dielectric layer over the metal units. Second bonding features are over the cap dielectric layer and bonded to the first bonding features. The second bonding features extend through the cap dielectric layer and electrically coupled to the metal units. | 09-10-2015 |
20150251900 | SEMICONDUCTOR ARRANGEMENT WITH STRESS RELEASE CONFIGURATION - Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided herein. A semiconductor arrangement comprises a cap wafer, a microelectromechanical systems (MEMS) wafer, and a complementary metal-oxide-semiconductor (CMOS) wafer. The cap wafer comprises a first spring structure and the MEMS wafer comprises a second spring structure. The first spring structure and the second spring structure relieve stress as portions of the semiconductor arrangement, such as a membrane and a poly layer, move. An ambient pressure chamber is formed between the CMOS wafer and the MEMS wafer as a thermal insulation air gap to protect the MEMS wafer from heat originating from the CMOS wafer. The ambient pressure chamber is connected to ambient air, such as for CMOS outgassing relief. | 09-10-2015 |
20150251901 | SEMICONDUCTOR ARRANGEMENT WITH STRESS RELEASE AND THERMAL INSULATION - Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided herein. A semiconductor arrangement comprises a cap wafer, a microelectromechanical systems (MEMS) wafer, and a complementary metal-oxide-semiconductor (CMOS) wafer. The cap wafer comprises one or more spring structures, such as a first spring structure and a second spring structure. The first spring structure and the second spring structure relieve stress as portions of the semiconductor arrangement, such as a membrane and a poly layer, move. An ambient pressure chamber is formed between the CMOS wafer and the MEMS wafer, such as for CMOS outgassing relief. One or more thermal insulator structures are formed between the CMOS wafer and the MEMS wafer to protect the MEMS wafer from heat originating from the CMOS wafer. | 09-10-2015 |
20150266722 | MEMS Structures and Methods for Forming the Same - A method includes forming a MEMS device, forming a bond layer adjacent the MEMS device, and forming a protection layer over the bond layer. The steps of forming the bond layer and the protection layer include in-situ deposition of the bond layer and the protection layer | 09-24-2015 |
20150274513 | SEMICONDUCTOR ARRANGEMENT WITH THERMAL INSULATION CONFIGURATION - Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided herein. A semiconductor arrangement comprises a cap wafer, a microelectromechanical systems (MEMS) wafer, and a complementary metal-oxide-semiconductor (CMOS) wafer. The MEMS wafer comprises a thermal insulator air gap formed between a sensing layer and a membrane. An ambient pressure chamber is formed between the CMOS wafer and the membrane of the MEMS wafer. The ambient pressure chamber is configured as a second thermal insulator air gap. The thermal insulator air gap and the second thermal insulator air gap protect portions of the semiconductor arrangement, such as the MEMS wafer, from heat originating from the CMOS wafer, which can otherwise damage such portions of the semiconductor arrangement. In some embodiments, one or more buffer layers are formed over the cap wafer as stress buffers. | 10-01-2015 |
20150284240 | STRUCTURES AND FORMATION METHODS OF MICRO-ELECTRO MECHANICAL SYSTEM DEVICE - A micro-electro mechanical system (MEMS) device is provided. The MEMS device includes a cap substrate and a MEMS substrate bonded with the cap substrate. The MEMS substrate includes a first movable element and a second movable element. The MEMS device also includes a first closed chamber between the MEMS substrate and the cap substrate, and the first movable element is in the first closed chamber. The MEMS device further includes an outgassing layer in the first closed chamber. In addition, the MEMS device includes a second closed chamber between the MEMS substrate and the cap substrate, and the second movable element is in the second closed chamber. | 10-08-2015 |
20150307346 | MEMS Devices and Methods for Forming Same - Embodiments of the present disclosure include MEMS devices and methods for forming MEMS devices. An embodiment is a method for forming a microelectromechanical system (MEMS) device, the method including forming a MEMS wafer having a first cavity, the first cavity having a first pressure, and bonding a carrier wafer to a first side of the MEMS wafer, the bonding forming a second cavity, the second cavity having a second pressure, the second pressure being greater than the first pressure. The method further includes bonding a cap wafer to a second side of the MEMS wafer, the second side being opposite the first side, the bonding forming a third cavity, the third cavity having a third pressure, the third pressure being greater than the first pressure and less than the second pressure. | 10-29-2015 |
20150315015 | Stacked Semiconductor Device and Method of Forming the Same Related Cases - A stacked semiconductor device includes a CMOS device and a MEMS device. The CMOS device includes a multilayer interconnect with metal elements disposed over the multilayer interconnect. The MEMS device includes metal sections with a first dielectric layer disposed over the metal sections. A cavity in the first dielectric layer exposes portions of the metal sections. A dielectric stop layer is disposed at least over the interior surface of the cavity. A movable structure is disposed over a front surface of the first dielectric layer and suspending over the cavity. The movable structure includes a second dielectric layer over the front surface of the first dielectric layer and suspending over the cavity, metal features over the second dielectric layer, and a flexible dielectric membrane over the metal features. The CMOS device is bonded to the MEMS device with the metal elements toward the flexible dielectric membrane. | 11-05-2015 |
20150329351 | Vacuum Sealed MEMS and CMOS Package - A vacuum sealed MEMS and CMOS package and a process for making the same may include a capping wafer having a surface with a plurality of first cavities, a first device having a first surface with a second plurality of second cavities, a hermetic seal between the first surface of the first device and the surface of the capping wafer, and a second device having a first surface bonded to a second surface of the first device. The second device is a CMOS device with conductive through vias connecting the first device to a second surface of the second device, and conductive bumps on the second surface of the second device. Conductive bumps connect to the conductive through vias and wherein a plurality of conductive bumps connect to the second device. The hermetic seal forms a plurality of micro chambers between the capping wafer and the first device. | 11-19-2015 |
20150329353 | SENSOR INTEGRATION WITH AN OUTGASSING BARRIER AND A STABLE ELECTRICAL SIGNAL PATH - The present disclosure relates to a structure and method of forming a MEMS-CMOS integrated circuit with an outgassing barrier and a stable electrical signal path. An additional poly or metal layer is embedded within the MEMS die to prevent outgassing from the CMOS die. Patterned conductors formed by a damascene process and a direct bonding between the two dies provide a stable electrical signal path. | 11-19-2015 |
20150338435 | Methods and Apparatus for MEMS Devices with Increased Sensitivity - Methods and apparatus for forming MEMS devices. An apparatus includes at least a portion of a semiconductor substrate having a first thickness and patterned to form a moveable mass; a moving sense electrode forming the first plate of a first capacitance; at least one anchor patterned from the semiconductor substrate and having a portion that forms the second plate of the first capacitance and spaced by a first gap from the first plate; a layer of semiconductor material of a second thickness patterned to form a first electrode forming a first plate of a second capacitance and further patterned to form a second electrode overlying the at least one anchor and forming a second plate spaced by a second gap that is less than the first gap; wherein a total capacitance is formed that is the sum of the first capacitance and the second capacitance. Methods are disclosed. | 11-26-2015 |
20150340341 | PACKAGE SYSTEMS - A package system includes a first substrate; and a second substrate electrically coupled with the first substrate. The package system further includes a semiconductor material between the first substrate and the second substrate. The semiconductor material includes a pad, and at least one guard ring surrounding the pad and spaced from the pad. The package system further includes a metallic material bonded to the semiconductor material, wherein the metallic material at least partially fills at least one opening in at least one of the first substrate or the second substrate. | 11-26-2015 |
20150364363 | VHF ETCH BARRIER FOR SEMICONDUCTOR INTEGRATED MICROSYSTEM - The present disclosure relates to an integrated microsystem with a protection barrier structure, and an associated method. In some embodiments, the integrated microsystem comprises a first die having a plurality of CMOS devices disposed thereon, a second die having a plurality of MEMS devices disposed thereon and a vapor hydrofluoric acid (vHF) etch barrier structure disposed between the first die and the second die. The second die is bonded to the first die at a bond interface region. The vHF etch barrier structure comprises a vHF barrier layer over an upper surface of the first die, and a stress reduction layer arranged between the vHF etch barrier layer and the upper surface of the first die. | 12-17-2015 |
20160002027 | SEMICONDUCTOR DEVICE WITH THROUGH MOLDING VIAS AND METHOD OF MAKING THE SAME - A method of forming a semiconductor device includes bonding a capping wafer and a base wafer to form a wafer package. The base wafer includes a first chip package portion, a second chip package portion, and a third chip package portion. The capping wafer includes a plurality of isolation trenches. Each isolation trench of the plurality of isolation trenches is substantially aligned with a corresponding trench region of one of the first chip package portion, the second chip package portion or the third chip package portion. The method also includes removing a portion of the capping wafer to expose a first chip package portion contact, a second chip package portion contact, and a third chip package portion contact. The method further includes separating the wafer package into a first chip package configured to perform a first operation, a second chip package configured to perform a second operation, and a third chip package configured to perform a third operation. | 01-07-2016 |
20160031703 | METHOD FOR MANUFACTURING A MICROELECTROMECHANICAL SYSTEMS (MEMS) DEVICE WITH DIFFERENT ELECTRICAL POTENTIALS AND AN ETCH STOP - A semiconductor structure for a microelectromechanical systems (MEMS) device is provided. A first substrate region includes an electrical isolation layer arranged over a top surface of the first substrate region. A second substrate region is arranged over the electrical isolation layer and includes a MEMS device structure arranged within the second substrate region. The MEMS device structure includes a fixed mass and a proof mass. A dielectric region is arranged over the electrical isolation layer around the fixed mass. A fixed mass electrode is arranged around the dielectric region, and extends through the second substrate region to the electrical isolation layer. An isolated electrode extends through the second substrate region and the electrical isolation layer to the first substrate region on an opposite side of the proof mass as the fixed mass electrode. The method of forming the semiconductor structure is also provided. | 02-04-2016 |
20160031704 | CAPACITOR WITH PLANARIZED BONDING FOR CMOS-MEMS INTEGRATION - An integrated circuit (IC) structure is provided. The IC structure includes an IC substrate including active devices which are coupled together through a conductive interconnect structure arranged thereover. The conductive interconnect structure includes a series of horizontal conductive layers and dielectric regions arranged between neighboring horizontal conductive layers. The conductive interconnect structure includes an uppermost conductive horizontal region with a planar top surface region. A MEMS substrate is arranged over the IC substrate and includes a flexible or moveable structure that flexes or moves commensurate with a force applied to the flexible or moveable structure. The active devices of the IC substrate are arranged to establish analysis circuitry to facilitate electrical measurement of a capacitance between the uppermost conductive horizontal region and the flexible or moveable structure. | 02-04-2016 |
20160046483 | METHODS FOR PACKAGING A MICROELECTROMECHANICAL SYSTEM (MEMS) WAFER AND APPLICATION-SPECIFIC INTEGRATED CIRCUIT (ASIC) DIES USING THROUGH MOLD VIAS (TMVS) - A method for packaging a microelectromechanical system (MEMS) device with an integrated circuit die using through mold vias (TMVs) is provided. According to the method, a MEMS substrate having a MEMS device is provided. A cap substrate is secured to a top surface of the MEMS substrate. The cap substrate includes a recess corresponding to the MEMS device in a bottom surface of the cap substrate. An integrated circuit die is secured to a top surface of the cap substrate over the recess. A housing covering the MEMS substrate, the cap substrate, and the integrated circuit die is formed. A through mold via (TMV) electrically coupled with the integrated circuit die and extending between a top surface of the housing and the integrated circuit die is formed. The structure resulting from application of the method is also provided. | 02-18-2016 |
20160046484 | METHODS FOR PACKAGING A MICROELECTROMECHANICAL SYSTEM (MEMS) WAFER AND APPLICATION-SPECIFIC INTEGRATED CIRCUIT (ASIC) DIES USING WIRE BONDING - A method for packaging a microelectromechanical system (MEMS) device with an integrated circuit die using wire bonds is provided. According to the method, a MEMS substrate having a MEMS device is provided. A cap substrate is secured to a top surface of the MEMS substrate. The cap substrate includes a recess corresponding to the MEMS device in a bottom surface of the cap substrate. An integrated circuit die is secured to a top surface of the cap substrate over the recess. A conductive stud or external wire bond electrically coupled with the integrated circuit die and extending vertically up is formed. A housing covering the MEMS substrate, the cap substrate, and the integrated circuit die, and with a top surface approximately coplanar with a top surface of the conductive stud or external wire bond, is formed. The structure resulting from application of the method is also provided. | 02-18-2016 |
20160054401 | MAGNETIC SENSOR AND FORMING METHOD - The present disclosure relates to a MEMS device with a magnetic film disposed on a first substrate, and an associated method of formation. In some embodiments, the magnetic film is disposed on a planar front surface of the first substrate such that depositing and patterning processes of the magnetic film is improved. A sensing gap of a MEMS device associated with the magnetic film is located between the magnetic film and a recessed lateral surface of a second substrate. The second substrate is bonded to the first substrate at front surfaces of the first and second substrate. Forming the magnetic film on the planar front allows for patterning of the magnetic film without leaving unwanted residues of magnetic material. Without the unwanted residue of magnetic material, less contamination from the magnetic material is introduced after dry etching and passivation processes, improving yield and reliability of the MEMS device. | 02-25-2016 |