Patent application number | Description | Published |
20120299177 | SEMICONDUCTOR COMPONENT AND METHOD OF FABRICATING THE SAME - A semiconductor component structure is provided, which includes a body formed with openings, an insulating layer formed on surfaces of the body and the openings, conductive bumps formed in the openings, and a re-distributed circuit formed by conductive traces electrically connecting the conductive bumps, wherein the conductive traces are formed on a portion of the insulating layer on the body. As the conductive traces and the conductive bumps are formed on and in the body prior to the formation of the re-distributed circuit. The process for fabricating the semiconductor component structure is simplified and the reliability of the semiconductor component structure is enhanced. A method for fabricating the semiconductor component is also provided. | 11-29-2012 |
20140021617 | SEMICONDUCTOR SUBSTRATE AND METHOD OF FABRICATING THE SAME - A semiconductor substrate is provided, including: a substrate; a plurality of conductive through vias embedded in the substrate; a first dielectric layer formed on the substrate; a metal layer formed on the first dielectric layer; and a second dielectric layer formed on the metal layer. As such, when a packaging substrate is disposed on the second dielectric layer, the metal layer provides a reverse stress to balance thermal stresses caused by the first and second dielectric layers, thereby preventing warpage of the semiconductor substrate. | 01-23-2014 |
20140117538 | PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF - A fabrication method of a package structure is provided, which includes the steps of: providing an interposer having a plurality of recess holes; forming a conductive bump in a lower portion of each of the recess holes; forming a conductive through hole on the conductive bump in each of the recess holes; removing a portion of the interposer so as for the conductive bumps to protrude from the interposer; and mounting at least a first external element on the conductive bumps, thereby simplifying the fabrication process, shortening the process time and reducing the material cost. | 05-01-2014 |
20140217605 | INTERCONNECTION STRUCTURE FOR PACKAGE AND FABRICATION METHOD THEREOF - An interconnection structure for a package is disclosed. The interconnection structure includes a substrate body having a conductive portion formed on a surface thereof; a first photosensitive dielectric layer formed on the surface of the substrate body and having a via for exposing the conductive potion; a conductive via formed in the via; a second photosensitive dielectric layer formed on the first photosensitive dielectric layer and having a opening for exposing the conductive via and a portion of the first photosensitive dielectric layer; and a conductive trace layer formed in the opening of the second photosensitive dielectric layer so as to be electrically connected to the conductive portion through the conductive via, thereby simplifying the fabrication process and reducing the fabrication cost and time. | 08-07-2014 |
Patent application number | Description | Published |
20100039597 | Liquid Crystal Display Panel and Method for Manufacturing Thereof and Liquid Crystal Display Incorporating the Same - A liquid crystal display panel including several first electrode portions, several second electrode portions, and a smectic liquid crystal layer is provided. The first electrode portions and the second electrode portions are disposed on a first substrate. When an AC voltage is applied on the first electrode portions and the second electrode portions, the direction of a horizontal electrical field formed between each first electrode portion and the adjacent second electrode portion is parallel to the surface of the first substrate. The smectic liquid crystal layer is interposed between the first substrate and a second substrate. During the phase change of a liquid crystal molecule of the smectic liquid crystal layer, the horizontal electrical field generated by applying the AC voltage on the first electrode portions and the second electrode portions facilitates the alignment of the liquid crystal molecule of the smectic liquid crystal layer. | 02-18-2010 |
20100139856 | Method for Manufacturing a Liquid Crystal Display - A method for manufacturing a transflective LCD panel having a transmissive region and a reflective region includes steps of providing an upper substrate and a lower substrate in parallel, forming a first alignment film on the upper substrate, forming a reflective layer on the reflective region of the lower substrate, forming an first insulating layer to cover the reflective layer and the lower substrate, forming a second insulating layer to cover the first insulating layer, forming positive and negative driving electrodes wrapped in the second insulating layer, forming a coplanar second alignment film to cover the second insulating layer, packaging the upper substrate and the lower substrate, and filling liquid crystal molecules. | 06-10-2010 |
Patent application number | Description | Published |
20090113670 | ENCLOSED HINDE DEVICE WITH A READILY CENTER-ALIGNED MECHANISM - The present invention discloses an enclosed hinge device with a readily center-aligned mechanism, employing two protruded blocks of a locking retainer engaged into and fastened with two notch grooves of an arresting part to form two positioning points, such that the locking retainer and the arresting part are not slidable therebetween along with the advantage of easy assembly. Further, the securingly connection between the enclosing part, the arresting part, and the locking retainer also enhances the structural strength, thereby reducing the rotational shaking of the pivotal axle. | 05-07-2009 |
20090158556 | COVERED ROTATION SHAFT STRUCTURE HAVING AUTO LOCKING FUNCTION - The present invention relates to a covered rotation shaft structure having auto locking function, includes: a cover member having a covering end, and one lateral side of the cover member is provided with a bump; a pivotal shaft having a first shaft section and a second shaft section, the first shaft section is pivotally provided on the covering end and the second shaft section is pivotally provided on a through hole of a retaining unit; a cam member composed by the above mentioned retaining unit and a rotating unit, the retaining unit has the above mentioned through hole and a concave slot, and the concave slot is served to mount the bump, so the retaining unit is retained on one side of the cover member, and the through hole is disposed adjacent to the covering end; and the rotating unit is provided on the second shaft section of the pivotal shaft and is provided against the retaining unit; at least one resilient member provided on the second shaft section of the pivotal shaft, and a screw nut is provided at the end of the second shaft section; when rotating the pivotal shaft, the rotating unit is released from a locking position, and the resilient member is pressed by the rotating unit, when reversely rotating the pivotal shaft, the rotating unit is moved toward the locking position and when the rotating unit is close to the locking position, the rotating unit is pushed to the locking position by the resilient member. | 06-25-2009 |
20090235489 | Sheath Type Rotating Axel Structure with Automatic Locking Mechanism - The present invention discloses a sheath type rotating axle structure with automatic locking mechanism, comprising a sheath device, a retainer, a pivotal axle, a locking fastener, a locking rotator, a resilient body, and a screw nut. The first axle segment of the pivotal axle is pivoted to the sheath of the sheath device to realize the function of “easy opening and firm closing,” and the sheath device is disposed with a retainer on one end to achieve the “anti-shaking” function. The second axle segment of the pivotal axle is pivoted to the through hole of the retainer and embeddingly inserted into a locking fastener and a locking rotator. The locking fastener is disposed with a pin to be securingly fixed with a pin hole formed on the retainer, and a screw nut is used to securingly fix a plurality of resilient discs or a spring. When the pivotal axle is rotated to drive the locking fastener departing from the locked position, the resilient discs (or spring) are compressed by the locking rotator. Also, when the pivotal axle is rotated back to drive the locking rotator returning to the locked position, the resilient discs (or spring) press the locking rotator back to the locked position, so as to achieve the function of “automatic locking.” | 09-24-2009 |
Patent application number | Description | Published |
20130056830 | Semiconductor Structure and Method - An embodiment is a semiconductor structure. The semiconductor structure comprises at least two gate structures on a substrate. The gate structures define a recess between the gate structures, and the recess is defined by a depth in a vertical direction. The depth is from a top surface of at least one of the gate structures to below a top surface of the substrate, and the depth extends in an isolation region in the substrate. The semiconductor structure further comprises a filler material in the recess. The filler material has a first thickness in the vertical direction. The semiconductor structure also comprises an inter-layer dielectric layer in the recess and over the filler material. The inter-layer dielectric layer has a second thickness in the vertical direction below the top surface of the at least one of the gate structures. The first thickness is greater than the second thickness. | 03-07-2013 |
20130092985 | Spacer for Semiconductor Structure Contact - An embodiment is a semiconductor structure. The semiconductor structure comprises an epitaxial region, a gate structure, a contact spacer, and an etch stop layer. The epitaxial region is in a substrate. A top surface of the epitaxial region is elevated from a top surface of the substrate, and the epitaxial region has a facet between the top surface of the substrate and the top surface of the epitaxial region. The gate structure is on the substrate. The contact spacer is laterally between the facet of the epitaxial region and the gate structure. The etch stop layer is over and adjoins each of the contact spacer and the top surface of the epitaxial region. A ratio of an etch selectivity of the contact spacer to an etch selectivity of the etch stop layer is equal to or less than 3:1. | 04-18-2013 |
20130178039 | INTEGRATED CIRCUIT RESISTOR FABRICATION WITH DUMMY GATE REMOVAL - Methods of fabricating a semiconductor device including a metal gate transistor and a resistor are provided. A method includes providing a substrate including a transistor device region and an isolation region, forming a dummy gate over the transistor device region and a resistor over the isolation region, and implanting the resistor with a dopant. The method further includes wet etching the dummy gate to remove the dummy gate, and then forming a metal gate over the transistor device region to replace the dummy gate. | 07-11-2013 |
20140162432 | Semiconductor Structure and Method - An embodiment is a semiconductor structure. The semiconductor structure comprises at least two gate structures on a substrate. The gate structures define a recess between the gate structures, and the recess is defined by a depth in a vertical direction. The depth is from a top surface of at least one of the gate structures to below a top surface of the substrate, and the depth extends in an isolation region in the substrate. The semiconductor structure further comprises a filler material in the recess. The filler material has a first thickness in the vertical direction. The semiconductor structure also comprises an inter-layer dielectric layer in the recess and over the filler material. The inter-layer dielectric layer has a second thickness in the vertical direction below the top surface of the at least one of the gate structures. The first thickness is greater than the second thickness. | 06-12-2014 |
Patent application number | Description | Published |
20090203217 | NOVEL SELF-ALIGNED ETCH METHOD FOR PATTERNING SMALL CRITICAL DIMENSIONS - A method is disclosed for etching an integrated circuit structure within a trench. A layer to be etched is applied over the structure and within the trench. A CF-based polymer is deposited over the layer to be etched followed by deposition of a capping layer of SiOCl-based polymer. The CF-based polymer reduces the width of the trench to such an extent that little or no SiOCl-based polymer is deposited at the bottom of the trench. An O | 08-13-2009 |
20100006974 | STORAGE NITRIDE ENCAPSULATION FOR NON-PLANAR SONOS NAND FLASH CHARGE RETENTION - The present disclosure provides a method of manufacturing a microelectronic device. The method includes forming recessed shallow trench isolation (STI) features in a semiconductor substrate, defining a semiconductor region between adjacent two of the recessed STI features; forming a tunnel dielectric feature within the semiconductor region; forming a nitride layer on the recessed STI features and the tunnel dielectric feature; etching the nitride layer to form nitride openings within the recessed STI features; partially removing the recessed STI features through the nitride openings, resulting in gaps between the nitride layer and the recessed STI features; and forming a first dielectric material on surfaces of the nitride layer, sealing the nitride openings. | 01-14-2010 |
20130102136 | METHOD OF FORMING AN INTEGRATED CIRCUIT - A method of forming an integrated circuit is disclosed. A second material layer is formed on a first material layer. A patterned mask layer having a plurality of first features with a first pitch P | 04-25-2013 |
20130203247 | METHOD OF FABRICATING A SEMICONDUCTOR STRUCTURE - An embodiment of the current disclosure includes a method of providing a substrate, forming a polysilicon layer over the substrate, forming a first photoresist layer on the polysislicon layer, creating a first pattern on the first photoresistlayer, wherein some portions of the polysilicon layer are covered by the first photoresist layer and some portions of the polysilicon layer are not covered by the first photoresist layer, implanting ions into the portions of the polysilicon layer that are not covered by the first photoresist layer, removing the first photoresist layer from the polysilicon layer, forming a second photoresist layer on the polysilicon layer, creating a second pattern on the second photoresistlayer, and implanting ions into the portions of the polysilicon layer that are not covered by the second photoresist layer, removing the second photoresist layer from the polysilicon layer, and removing portions of the polysilicon layer using an etchant. | 08-08-2013 |
20140295654 | METHOD OF FORMING AN INTEGRATED CIRCUIT - A method of forming an integrated circuit includes forming a patterned mask layer on a material layer, the patterned mask layer having a plurality of first features with a first pitch. The method includes patterning the material layer by using the patterned mask layer as a mask to form the first features in the material layer. The method includes trimming the patterned mask layer, after patterning the material layer, to form a trimmed patterned mask layer. The method further includes introducing a plurality of dopants into the material layer exposed by the trimmed patterned mask layer to form doped regions having a second pitch, wherein the second pitch is different from the first pitch. The method further includes removing the trimmed patterned mask layer to expose un-doped regions in the material layer; and removing the un-doped regions to form a plurality of second features corresponding to the respective doped regions. | 10-02-2014 |
20150243504 | METHOD OF FORMING AN INTEGRATED CIRCUIT - A method of forming an integrated circuit includes forming a patterned mask layer on a material layer, wherein the patterned mask layer has a plurality of first features, and a first distance between adjacent first features of the plurality of first features. The method further includes patterning the material layer to form the first features in the material layer. The method further includes increasing the first distance between adjacent first features of the plurality of first features to a second distance. The method further includes treating portions of the material layer exposed by the patterned mask layer. The method further includes removing the patterned mask layer; and removing non-treated portions of the material layer. | 08-27-2015 |
20150332935 | METHOD OF FABRICATING A SEMICONDUCTOR STRUCTURE - A method of making a semiconductor structure, the method including forming a conductive layer over a substrate. The method further includes forming a first imaging layer over the conductive layer, where the first imaging layer comprises a plurality of layers. The method further includes forming openings in the first imaging layer to expose a first set of areas of the conductive layer. The method further includes implanting ions into each area of the first set of area. The method further includes forming a second imaging layer over the conductive layer. The method further includes forming openings in the second imaging layer to expose a second set of areas of the conductive layer, wherein the second set of areas is different from the first set of areas. The method further includes implanting ions into the each area of the second set of areas. | 11-19-2015 |
Patent application number | Description | Published |
20080286884 | METHOD FOR IN-SITU REPAIRING PLASMA DAMAGE AND METHOD FOR FABRICATING TRANSISTOR DEVICE - A method for in-situ repairing plasma damage, suitable for a substrate, is provided. A component is formed on the substrate. The formation steps of the component include a main etching process containing plasma. The method involves performing a soft plasma etching process in the apparatus of the main etching process containing plasma to remove a portion of the substrate. The soft plasma etching process is less than 30% of the power used in the main etching process. | 11-20-2008 |
20080305635 | METHOD FOR FABRICATING A PATTERN - A method for fabricating a patter is provided as followed. First, a material layer is provided, whereon a patterned hard mask layer is formed. A spacer is deposited on the sidewalls of the patterned hard mask layer. Then, the patterned hard mask layer is removed, and an opening is formed between the adjacent spacers. Afterwards, a portion of the material layer is removed to form a patterned material layer by using the spacer as mask. | 12-11-2008 |
20100096683 | Structure of semiconductor device - A structure of a semiconductor device including a substrate and a patterned layer is provided. The patterned layer being patterned to have an open area and a dense area is disposed on the substrate. The patterned layer includes, in the dense area, a first pattern adjacent to the open area and a second pattern. The first pattern has a first bottom. The second pattern has a second bottom width. The bottom of the first pattern includes a recess facing the open area, so that the first bottom width is close to the second bottom width. | 04-22-2010 |
20150125788 | MULTI-LINE WIDTH PATTERN CREATED USING PHOTOLITHOGRAPHY - Systems and methods are provided for forming features through photolithography. A polymer layer is formed over a substrate. The polymer layer is patterned to form a first feature and a second feature, the first feature and the second feature being separated at a first distance. A rinse material is applied to the polymer layer including the first feature and the second feature. The rinse material is removed from the polymer layer including the first feature and the second feature to cause the first feature and the second feature to come into contact with each other. A third feature is formed based on the first feature and the second feature being in contact with each other. | 05-07-2015 |
20150194497 | METHOD OF FORMING CHANNEL OF GATE STRUCTURE - A method of forming a channel of a gate structure is provided. A first epitaxial channel layer is formed within a first trench of the gate structure. A dry etching process is performed on the first epitaxial channel layer to form a second trench. A second epitaxial channel layer is formed within the second trench. | 07-09-2015 |
20150228483 | METHOD OF FORMING MOSFET STRUCTURE - A method of forming a MOSFET structure is provided. In the method, an epitaxial layer is formed. A cap layer is formed above the epitaxial layer. A first trench is formed above the epitaxial layer. A protection layer is deposited within the first trench. The protection layer is a material selected from the group consisting of germanium and silicon-germanium. | 08-13-2015 |
20150228759 | VERTICAL DEVICE AND METHOD OF FORMING THE SAME - According to an exemplary embodiment, a method of forming a vertical device is provided. The method includes the following operations: providing a vertical structure over a substrate; forming a first dielectric layer over the vertical structure and the substrate; laterally etching a sidewall of the first dielectric layer; replacing a portion of the first dielectric layer over the vertical structure with a second dielectric layer; and etching a portion of the first dielectric layer to expose the lateral surface of the vertical structure. | 08-13-2015 |
20160033871 | MULTI-LINE WIDTH PATTERN CREATED USING PHOTOLITHOGRAPHY - Systems and methods are provided for forming features through photolithography. A polymer layer is formed over a substrate. The polymer layer is patterned to form a first feature and a second feature, the first feature and the second feature being separated at a first distance. A rinse material is applied to the polymer layer including the first feature and the second feature. The rinse material is removed from the polymer layer including the first feature and the second feature to cause the first feature and the second feature to come into contact with each other. A third feature is formed based on the first feature and the second feature being in contact with each other. | 02-04-2016 |
20160111523 | METHOD OF FORMING A VERTICAL DEVICE - According to an exemplary embodiment, a method of forming a vertical device is provided. The method includes: providing a protrusion over a substrate; forming an etch stop layer over the protrusion; laterally etching a sidewall of the etch stop layer; forming an insulating layer over the etch stop layer; forming a film layer over the insulating layer and the etch stop layer; performing chemical mechanical polishing on the film layer and exposing the etch stop layer; etching a portion of the etch stop layer to expose a top surface of the protrusion; forming an oxide layer over the protrusion and the film layer; and performing chemical mechanical polishing on the oxide layer and exposing the film layer. | 04-21-2016 |
Patent application number | Description | Published |
20120063468 | ELECTRONIC DEVICE WITH NETWORK CONNECTION FUNCTIONALITY AND METHOD APPLIED TO THE ELECTRONIC DEVICE - An electronic device with network connection functionality includes a transceiver chip and a processing circuit. The transceiver chip is utilized for processing a data corresponding to a physical (PHY) layer. The processing circuit is externally connected to the transceiver chip, for processing a data corresponding to a media access control (MAC) layer. When the transceiver chip receives a designated packet, the transceiver chip generates a notification signal to notify at least one portion of the processing circuit to be switched from a first operating mode to a second operating mode. | 03-15-2012 |
20120137162 | NETWORK DEVICE AND NETWORK CONNECTING METHOD FOR BUILDING UP NETWORK CONNECTION VIA HIGH DEFINITION MULTIMEDIA INTERFACE - A network device for building up a network connection via a high-definition multimedia interface, includes a scrambler, a descrambler, a comparator and a control unit. The scrambler is utilized for generating a transmission signal according to a first seed. The descrambler is for decoding a receiving signal to generate a second seed. The comparator is for generating a comparing result according to the first seed and the second seed. The control unit is for controlling the network connection according to the comparing result. | 05-31-2012 |
20120173785 | NETWORK INTERFACE CARD, NETWORK SYSTEM, AND METHOD FOR BUILDING NETWORK CONNECTIONS WITH A REMOTE NETWORK APPARATUS VIA HDMI - A network interface card includes a receiving unit and a capturing unit. The receiving unit is used for receiving a first hot-plug signal transmitted from a remote network apparatus via an HDMI. The capturing unit is coupled to the receiving unit, for capturing a physical address of the remote network apparatus via the HDMI. After the physical address of the remote network apparatus is captured by the capturing unit, the network interface card communicates with the remote network apparatus by using the HDMI. | 07-05-2012 |
20120213306 | APPARATUS AND METHOD FOR CROSS CLOCK DOMAIN INTERFERENCE CANCELLATION - An apparatus and method for cross clock domain interference cancellation is provided to a communication system which includes a transmitter operated in a first clock domain and a receiver operated in a second clock domain. The apparatus comprises a First-In-First-Out (FIFO) circuit and a cancellation signal generator. The FIFO circuit receives a digital transmission signal of the transmitter in the first clock domain, and outputs the digital transmission signal in the second clock domain according to an accumulated timing difference between the first and second clock domains. The cancellation signal generator generates a cancellation signal for canceling an interference signal received by the receiver according to the digital transmission signal outputted by the FIFO circuit. The interference signal is generated in response to the digital transmission signal. The cancellation signal generator adjusts the cancellation signal according to a phase difference between the interference signal and the cancellation signal. | 08-23-2012 |
20140177698 | Signal transmission device performing compensation by filtering characteristics and method thereof, and signal reception device offsetting compensation and method thereof - The present invention discloses a signal transmission device performing compensation by filtering characteristics for generating a transmission signal according to a pulse amplitude modulation signal. The signal transmission device comprises: a filtering characteristic compensation circuit for generating a compensation signal according to the pulse amplitude modulation signal and a filtering function; a filter coupled to the filtering characteristic compensation circuit for generating a filtered signal through filtering the compensation signal according to the aforementioned filtering function; and an analog front-end circuit for generating the transmission signal according to the filtered signal. | 06-26-2014 |
20140200866 | METHOD AND SYSTEM FOR ESTABLISHING PARAMETRIC MODEL - A method for establishing a parametric model of a semiconductor process is provided. A first intermediate result is generated according to layout data and a non-parametric model of the semiconductor process. A first response is obtained according to the first intermediate result. A specific mathematical function is selected from a plurality of mathematical functions, and the parametric model is obtained according to the specific mathematical function. A second intermediate result is generated according to the layout data and the parametric model. A second response is obtained according to the second intermediate result. It is determined whether the parametric model is an optimal model according to the first and second responses. | 07-17-2014 |
Patent application number | Description | Published |
20080296701 | ONE-TIME PROGRAMMABLE READ-ONLY MEMORY - A one-time programmable read-only memory (OTP-ROM) including a substrate, a first doped region, a second doped region, a gate dielectric layer, a first gate and a second gate. The substrate is of a first conductive type. The first doped region and the second doped region are of a second conductive type and are separately disposed in the substrate. The gate dielectric layer is disposed on the substrate between the first doped region and the second doped region. The first gate and the second gate are disposed on the gate dielectric layer, respectively. The first gate is adjacent to the first doped region, while the second gate is adjacent to the second doped region. Here, the first gate is electrically coupled grounded, and the OTP-ROM is programmed through a breakdown effect. | 12-04-2008 |
20100073985 | METHOD FOR OPERATING ONE-TIME PROGRAMMABLE READ-ONLY MEMORY - A method for operating a one-time programmable read-only memory (OTP-ROM) is provided. The OTP-ROM comprises a first gate and a second gate respectively disposed on a gate dielectric layer between a first doped region and a second doped region on a substrate, wherein the first gate is adjacent to the first doped region and coupled to the first doped region, the second gate is adjacent to the second doped region, the first gate is electrically coupled grounded, and the OTP-ROM is programmed through a breakdown effect. The method comprises a step of programming the OTP-ROM under the conditions that a voltage of the second doped region is higher than a voltage of the first doped region, the voltage of the second gate is higher than a threshold voltage to pass the voltage of the second doped region, and the first doped region and the substrate are at a reference voltage. | 03-25-2010 |
Patent application number | Description | Published |
20120188766 | LED LAMP - The LED lamp includes a heat dissipating base, an LED module, a hood and a sealant. The heat dissipating base has a mount board including a first surface and a second surface. The first and second surfaces are provided with an annular trough and fins, respectively. The LED module is fixed on the mount board and surrounded by the annular trough. The hood is formed with a flange which is embedded into the annular trough to cloak the LED module. The sealant is filled in the annular trough to seal up. | 07-26-2012 |
20130176733 | LED LAMP - The LED lamp includes a heat dissipating base, an LED module, a hood and a sealant. The heat dissipating base has a mount board including a first surface and a second surface. The first and second surfaces are provided with an annular trough and fins, respectively. The LED module is fixed on the mount board and surrounded by the annular trough. The hood is formed with a flange which is embedded into the annular trough to cloak the LED module. The sealant is filled in the annular trough to seal up. | 07-11-2013 |
20140032109 | ROUTE RECOMMENDATION SYSTEM AND METHOD THEREOF - A route recommendation system is provided. The system has: a data querying apparatus configured to generate query information according to a location; and a data analyzing apparatus, connected to the data querying apparatus, having: a database configured to store at least one candidate data, wherein each candidate data has a candidate location, at least one recommended location corresponding to the candidate location, and a recommended staying time of each recommended location; a data receiving unit configured to receive the query information; and a processing unit configured to generate at least one recommended route according to the query information and the candidate data, and transmit the at least one recommended route to the data querying apparatus, wherein the recommended route comprises a path from the location to the at least one recommended location, and the recommended staying time corresponding to each recommended location. | 01-30-2014 |
20140059060 | SYSTEMS AND METHODS FOR PRESENTING POINT OF INTEREST (POI) INFORMATION IN AN ELECTRONIC MAP, AND STORAGE MEDIUM - A map system for presenting Point of Interest (POI) information is provided with an interface module, a storage unit, and a processing module. The interface module is coupled to a display device and provides an operation interface for receiving a search query and a condition of time period. The storage unit stores a plurality of POIs data and verified data of the POIs each corresponding to a respective one of different time periods. The processing module filters the POIs and the verified data according to the search query and the condition of time period to generate an electronic map, and displays the electronic map to present the filtered POIs via the interface module and the display device. | 02-27-2014 |
20140211485 | BAY LAMP WITH COOLING PLATE - Disclosed is a bay lamp with a cooling plate. The bay lamp includes a metal lampholder and at least one cooling plate. Each cooling plate includes a vertical plate extended from the metal lampholder, a transverse plate bent and extended from the vertical plate, and a spacing formed between the transverse plate and the metal lampholder. The cooling plate is integrally formed with the metal lampholder and extended from the metal lampholder to substitute a conventional fin, so as to reduce the cost and weight of the bay lamp. | 07-31-2014 |
20140240983 | LED STREET LAMP - An LED street structures includes a pair of frames, a plurality of LED modules, an electrical box, a side cover and a back cover. Each frame has a cover plate, a supporting plate and a blocking plate. The LED modules are arranged between the frames. Two sides of the LED modules are fixed on the supporting plate. The electrical box disposed by a lateral side of the LED modules covers one side of the frames. The side cover covers another side of the frames. The back cover positioned between the frames covers the LED modules. | 08-28-2014 |
20140265867 | SMART LIGHT EMITTING DIODE DRIVING APPARATUS - A smart light emitting diode driving apparatus includes a micro processing unit and a light emitting diode driving circuit. An optical detection equipment is configured to send an optics characteristic signal to a computer after an optics characteristic of a light emitting diode is detected by the optical detection equipment. The computer is configured to send a control signal to the micro processing unit after the optics characteristic signal is processed by the computer. The micro processing unit is configured to record the control signal. The micro processing unit is configured to control the light emitting diode driving circuit in accordance with the control signal. The light emitting diode driving circuit is configured to output a driving current to drive the light emitting diode. | 09-18-2014 |
20140372459 | SOCIAL DATA FILTERING SYSTEM, METHOD AND NON-TRANSITORY COMPUTER READABLE STORAGE MEDIUM OF THE SAME - A social data filtering system is provided. The social data filter system comprises a database, a retrieving module, a filtering module and a determining module. The database stores personal data and corresponding identification information. The retrieving module retrieves the personal data and the identification information corresponding to a designated person and generates search information accordingly to retrieve user information and corresponding social interaction information from a plurality of social data sources accordingly to the search information The filtering module performs filtering on the user information and the social interaction information according to the personal data to retrieve filtered information. The determining module determines at least one key word corresponding to the designated person according to the filtered information. | 12-18-2014 |
20150312993 | ILLUMINANT DEVICE AND CONTROLLING MODULE THEREOF - A controlling module controls illuminant state of an illuminant module according to a controlling signal sent form a wireless controller. The controlling module is electrically connected to the illuminant module and includes a microprocessor, a wireless receiver, a regulator, and a driving unit. The wireless receiver is electrically connected to the microprocessor and receives the controlling signal sent form the wireless controller. The regulator is electrically connected to the microprocessor. The driving unit is electrically connected to the microprocessor and the illuminant module. | 10-29-2015 |
Patent application number | Description | Published |
20120224328 | INNER-LAYER HEAT-DISSIPATING BOARD, MULTI-CHIP STACK PACKAGE STRUCTURE HAVING THE INNER LAYER HEAT-DISSIPATING BOARD AND FABRICATION METHOD THEREOF - An inner-layer heat-dissipating board and a multi-chip stack package structure having the inner-layer heat-dissipating board are disclosed. The inner-layer heat-dissipating board includes a metal board body formed with a plurality of penetrating conductive through holes each comprising a plurality of nano wires and an oxidative block having nano apertures filled with the nano wires. The multi-chip stack package structure includes a first chip and an electronic component respectively disposed on the inner-layer heat-dissipating board to thereby facilitate heat dissipation in the multi-chip stack structure as well as increase the overall package rigidity. | 09-06-2012 |
20130326873 | METHOD OF FABRICATING MULTI-CHIP STACK PACKAGE STRUCTURE HAVING INNER LAYER HEAT-DISSIPATING BOARD - An inner-layer heat-dissipating board and a multi-chip stack package structure having the inner-layer heat-dissipating board are disclosed. The inner-layer heat-dissipating board includes a metal board body formed with a plurality of penetrating conductive through holes each comprising a plurality of nano wires and an oxidative block having nano apertures filled with the nano wires. The multi-chip stack package structure includes a first chip and an electronic component respectively disposed on the inner-layer heat-dissipating board to thereby facilitate heat dissipation in the multi-chip stack structure as well as increase the overall package rigidity. | 12-12-2013 |
20150035163 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - The present invention provides a semiconductor package and a method of fabricating the same, including: placing a semiconductor element in a groove of a carrier; forming a dielectric layer on the semiconductor element; forming on the dielectric layer a circuit layer electrically connected to the semiconductor element; and removing a first portion of the carrier below the groove to keep a second of the carrier on a sidewall of the groove intact for the second portion to function as a supporting part. The present invention does not require formation of a silicon interposer, therefore the overall cost of the final product is much reduced. | 02-05-2015 |
20150035164 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - The present invention provides a semiconductor package and a method of fabricating the same, including: placing in a groove of a carrier a semiconductor element having opposing active and non-active surfaces, and side surfaces abutting the active surface and the non-active surface; applying an adhesive material in the groove and around a periphery of the side surfaces of the semiconductor element; forming a dielectric layer on the adhesive material and the active surface of the semiconductor element; forming on the dielectric layer a circuit layer electrically connected to the semiconductor element; and removing a first portion of the carrier below the groove to keep a second portion of the carrier on a side wall of the groove intact for the second portion to function as a supporting member. The present invention does not require formation of a silicon interposer, and therefore the overall cost of a final product is much reduced. | 02-05-2015 |
20150303139 | SUBSTRATE HAVING ELECTRICAL INTERCONNECTION STRUCTURES AND FABRICATION METHOD THEREOF - A method for fabricating a substrate having an electrical interconnection structure is provided, which includes the steps of: providing a substrate body having a plurality of conductive pads and first and second passivation layers sequentially formed on the substrate body and exposing the conductive pads; forming a seed layer on the second passivation layer and the conductive pads; forming a first metal layer on each of the conductive pads, wherein the first metal layer is embedded in the first and second passivation layers without being protruded from the second passivation layer; and forming on the first metal layer a second metal layer protruded from the second passivation layer. As such, when the seed layer on the second passivation layer is removed by etching using an etchant, the etchant will not erode the first metal layer, thereby preventing an undercut structure from being formed underneath the second metal layer. | 10-22-2015 |
20160005695 | PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF - A method for fabricating a package structure is provided, which includes the steps of: providing a base portion having at least an electronic element embedded therein and at least a positioning unit formed around a periphery of the electronic element, wherein the positioning unit protrudes from or is flush with a surface of the base portion; and forming at least a circuit layer on the surface of the base portion and the electronic element. The circuit layer is aligned and connected to the electronic element through the positioning unit. | 01-07-2016 |
20160050753 | INTERPOSER AND FABRICATION METHOD THEREOF - A method for fabricating an interposer is provided, which includes the steps of: providing a substrate body having opposite first and second sides and a plurality of conductive through holes communicating the first and second sides; forming an insulating layer on the first side of the substrate body, wherein the insulating layer has a plurality of openings correspondingly exposing the conductive through holes; and forming a plurality of conductive pads in the openings of the insulating layer, wherein the conductive pads are electrically connected to the corresponding conductive through holes, thereby dispensing with the conventional wet etching process and hence preventing an undercut structure from being formed under the conductive pads. | 02-18-2016 |
20160141255 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package is provided, which includes: a circuit structure having a first bottom surface and a first top surface opposite to the first bottom surface; at least a semiconductor element disposed on the first top surface of the circuit structure and electrically connected to the circuit structure; an encapsulant formed on the first top surface of the circuit structure to encapsulate the semiconductor element, wherein the encapsulant has a second bottom surface facing the first top surface of the circuit structure and a second top surface opposite to the second bottom surface; and a strengthening layer formed on the second top surface of the encapsulant, or formed between the circuit structure and the encapsulant, or formed on the first bottom surface of the circuit structure, thereby effectively preventing the encapsulant from warping and the semiconductor element from cracking. | 05-19-2016 |
Patent application number | Description | Published |
20150106773 | METHODOLOGY FOR PATTERN CORRECTION - The present disclosure relates to a method of integrated chip (IC) design pattern correction that reduces pattern correction cycle time by separately correcting main feature shapes and dummy shapes of the IC design, and an associated apparatus. In some embodiments, the method is performed by forming an IC design having a plurality of main feature shapes. A plurality of dummy shapes are added to the IC design to improve a process window of the IC design. The plurality of main feature shapes are corrected using a first pattern correction process. One or more of the plurality of dummy shapes are subsequently corrected using a second pattern correction process separate from the first pattern correction process. By separately correcting dummy shapes and main feature shapes, the dummy shapes can be subjected to a different pattern correction process having lower time/resource demands, thereby reducing the pattern correction cycle time. | 04-16-2015 |
20150106779 | METHODOLOGY FOR PATTERN DENSITY OPTIMIZATION - The present disclosure relates to a method of improving pattern density with a low OPC (optical proximity correction) cycle time, and an associated apparatus. In some embodiments, the method is performed by forming an integrated chip (IC) design that is a graphical representation of an integrated chip. One or more low-pattern-density areas of the IC design are identified having a pattern density that results in a processing failure. The low-pattern-density areas are a subset of the IC design. The pattern density is adjusted within the low-pattern-density area by adding one or more dummy shapes within the low-pattern-density areas. A data preparation process is then performed on the IC design to modify shapes of the one or more dummy shapes within the low-pattern-density areas. By introducing dummy shapes into a local area, rather than into an entire integrated chip design, the demands of the subsequent data preparation process are reduced. | 04-16-2015 |
20150310158 | Method for Integrated Circuit Manufacturing - Provided is an integrated circuit (IC) manufacturing method. The method includes receiving a design layout of an IC, wherein the design layout includes a plurality of non-overlapping IC regions and each of the IC regions includes a same initial IC pattern. The method further includes dividing the IC regions into a plurality of groups based on a location effect analysis such that all IC regions in a respective one of the groups are to have substantially same location effect. The method further includes performing a correction to one IC region in each of the groups using a correction model that includes location effect; and copying the corrected IC region to other IC regions in the respective group. The method further includes storing the corrected IC design layout in a tangible computer-readable medium for use by a further IC process stage. | 10-29-2015 |
Patent application number | Description | Published |
20120316164 | METHOD FOR INHIBITING THE GROWTH OF CANCER STEM CELLS - The present invention provides a method for inhibiting the growth of cancer stem cells, particularly colorectal cancer stem cells, liver cancer stem cells, lung cancer stem cells or breast cancer stem cells, comprising administering to a subject in need thereof a therapeutically effective amount of a compound of antimycin A or a pharmaceutically acceptable salt thereof, together with a pharmaceutically acceptable carrier. | 12-13-2012 |
20140045841 | METHOD FOR INHIBITING THE GROWTH OF CANCER STEM CELL - The present invention provides a method for inhibiting the growth of cancer stem cells, particularly colorectal cancer stem cells, liver cancer stem cells, lung cancer stem cells or breast cancer stem cells, comprising administering to a subject in need thereof a therapeutically effective amount of a compound of antimycin A or a pharmaceutically acceptable salt thereof, together with a pharmaceutically acceptable carrier. | 02-13-2014 |
20150314569 | STEEL SHEET AND FABRICATION METHOD THEREOF - Provided is a steel sheet including an. iron-based material, a first coating layer disposed on the iron-based material, and a second coating layer disposed on the first coating layer, wherein the first coating layer includes a zinc alloy and the second coating layer consists essentially of chromium and carbon. | 11-05-2015 |
Patent application number | Description | Published |
20140209211 | ENERGY-STORAGE PEN IMPLEMENT SHARPENER - An energy-storage pen implement includes a base, a spiral knife assembly, a rotating plate, an elastic device and a pressing block. The base includes a first groove and a second groove, and the first groove is provided for inserting a pen implement. The spiral knife assembly is disposed at the first groove. The rotating plate is disposed at the first groove and connected to the spiral knife assembly. The elastic device is disposed at the second groove. One end of the pressing block is connected to the rotating plate, and another end of the pressing block is connected to the elastic device. When the elastic device moves resiliently to push the pressing block, the pressing block drives the rotating plate and the spiral knife assembly to rotate, thereby allowing the spiral knife to sharpen the tip of the pen implement. | 07-31-2014 |
20140214106 | BUTTSTOCK - A buttstock includes a main body and a protecting member. The main body includes a shell member and an automated external defibrillator disposed in the shell member. The protecting member is movably connecting with the shell member of the main body so as to move relative to the shell member between a first position and a second position, wherein the protecting member shields the automated external defibrillator at the first position and exposes the automated external defibrillator at the second position respectively. | 07-31-2014 |
20150099162 | CONTINUABLE POWER MODULE AND ELECTRIC DEVICE INCLUDING THE SAME - A continuable power module includes at least one battery. The battery includes a main body, a first electrode terminal, a second electrode terminal and a conducting terminal. The main body includes a connecting end and a continuing end opposite to the connecting end. The first electrode terminal is disposed at the connecting end, and the second electrode terminal is disposed at the continuing end. The structure of the second electrode terminal matches that of the first electrode terminal. The conducting terminal includes a secured end and a free end. The secured end is disposed at the continuing end, and the free end is detachably connected to the first electrode terminal. The conducting terminal is connected electrically to the first electrode terminal via the free end thereof, such that the continuing end of the one battery is connected to the connecting end of another battery. | 04-09-2015 |
20150208786 | COATING DEVICE - A coating device includes a body and a thermoelectric cooling plate. The body defines a receiving space and a storage groove and includes a contact plane and a feeding pipe. The contact plane includes a cooling region and a heating region which are cooled and heated by the thermoelectric plate, respectively. The storage groove is provided for storing a coating material. The storage groove communicates with outside of the body through the feeding pipe. When the body is moved from a first position to a second position of the target object, the coating material is heated by the heating region, cooled by the cooling region, and coated on the surface of target object. | 07-30-2015 |
20150224329 | HEADREST STRUCTURE - A headrest structure is provided and includes a body and two supporting rods. The body includes a covering cushion and an automated external defibrillator (AED). The AED is enclosed by the covering cushion. Each of the supporting rods includes a linking end and a combining end opposite to the linking end, and each of the supporting rods is connected to the body with the linking end so as to support the body. Based on this, the AED is assembled in the body to improve the applicability of the AED, so that patients experiencing cardiac arrest can be treated properly and instantly. | 08-13-2015 |
20150263448 | CONTINUABLE WATERPROOF CABLE, CONTINUABLE WATERPROOF POWER MODULE, AND WATERPROOF TERMINAL ASSEMBLY - A continuable waterproof cable includes a cable body, first, second and third transmitting members, and first and second waterproof elastic members. The cable body has a connecting end and a continuing end opposite to the connecting end. The first transmitting member and the first waterproof elastic member are disposed at the connecting end. The second transmitting member is disposed at the continuing end, coupled to the first transmitting member, and adapted to a first end of the first transmitting member. The second waterproof elastic member is disposed at the continuing end. The third transmitting member is in the cable body and has a fixed end and a free end. The fixed end is at the continuing end, the free end is detachably coupled to the first transmitting member and capable to be apart from the transmitting member by a force. | 09-17-2015 |
20160096029 | BUTTSTOCK - A buttstock includes a main body and a protecting member. The main body includes a shell member and an automated external defibrillator disposed in the shell member. The protecting member is movably connecting with the shell member of the main body so as to move relative to the shell member between a first position and a second position, wherein the protecting member shields the automated external defibrillator at the first position and exposes the automated external defibrillator at the second position respectively. | 04-07-2016 |