Patent application number | Description | Published |
20080282107 | Method and Apparatus for Repairing Memory - Methods and apparatuses are disclosed in which a repair instruction, such as from a tester, causes an integrated circuit undergoing testing to substitute defective locations of a first set of memory cells in the integrated circuit with a second set of memory cells in the integrated circuit, despite the repair instruction omitting the defective locations of the first set of memory cells of the integrated circuit. | 11-13-2008 |
20090016116 | Method of Programming and Erasing a Non-Volatile Memory Array - A method of processing an array of non-volatile memory cells to program or erase the same, by applying a voltage to the same through a program and verify pulse application circuit. The process includes a first step of selecting a voltage to be applied. Then, the maximum number of memory cells that can be processed simultaneously is determined, based on the selected voltage and characteristics of the memory cells and the circuit. The array is divided into processing groups, each group having a number of cells less than or equal to the maximum determined number. Finally, the voltage is applied to the cells. | 01-15-2009 |
20090021994 | MEMORY AND METHOD FOR PROGRAMMING THE SAME - A method for programming a memory, which includes multiple multi-level cells each having a left half cell and a right half cell, includes the following steps. First, a target address corresponding to 2n-group data to be stored is provided, wherein n is a positive integer. Next, the 2n-group data is sequentially programmed into the multi-level cells based upon the target address in a programming loop so that the data stored in the left half cells and the data stored in the right half cells are from different groups of the 2n-group data. | 01-22-2009 |
20090046521 | Memory structure, programming method and reading method therefor, and memory control circuit thereof - The memory structure improves a sensing accuracy of memory cells by dividing the main array into a number of memory units and sensing memory cells of each memory units with an appropriate set of reference currents. Each of the memory units corresponds to a reference group bit value, which indicates the appropriate set of reference currents. The appropriate set of reference currents is chosen from a number of sets of selective reference currents according to the threshold voltage distribution of each of the memory units. Thus each of the memory units of the memory structure of the present invention is sensed with its own appropriate set of reference currents correctly, and the improvement of sensing accuracy is therefore achieved. | 02-19-2009 |
20090063918 | APPARATUS AND METHOD FOR DETECTING WORD LINE LEAKAGE IN MEMORY DEVICES - A method for detecting word line leakage in a memory device includes coupling a first plurality of word lines in the memory device to a voltage source while grounding a second plurality of word lines. Each of the second plurality of word lines is adjacent to a corresponding one of the first plurality of word lines. The method includes waiting for a period of time to allow the word lines to reach a predetermined read voltage level. The method also includes decoupling the first plurality of word lines from the voltage source and waiting for a second predetermined period of time to allow the first plurality of word lines to discharge. The method further includes sensing a current associated with the word lines, and comparing the current with a predetermined reference current which is selected for identifying a word line leakage condition associated with the first plurality of word lines. | 03-05-2009 |
20090121780 | MULTIPLE-STAGE CHARGE PUMP WITH CHARGE RECYCLE CIRCUIT - A multiple-stage charge pump circuit comprises first and second pump capacitors, first and second transfer circuits, first and second driving circuits, and a charge recycle circuit. The first pump capacitor, the first transfer circuit, and the first driving circuit form a first stage circuit and the second pump capacitor, the second transfer circuit, and the second driving circuit form a second stage circuit. The first and the second stage circuits operate 180 degree out of phase with each other. The charge recycle circuit transfers the charge at the second end of the first pump capacitor to the second end of the second pump capacitor in a first time interval, and transferring the charge at the second end of the second pump capacitor to the second end of the first pump capacitor in a second time interval. | 05-14-2009 |
20090147799 | CIRCUIT AND METHOD FOR TRANSMITTING DATA STREAM - A circuit including a first data selection circuit and a second data selection circuit for transmitting a data stream is provided. The first data selection circuit having first controllable channels turns on a first operating channel being one of the first controllable channels in an odd-numbered period and turns off the first controllable channels in an even-numbered period adjacent to the odd-numbered period for transmitting a first bit datum of the data stream. The second data selection circuit having second controllable channels turns off the second controllable channels in the odd-numbered period and turns on a second operating channel being one of the second controllable channels in the even-numbered period for transmitting a second bit datum of the data stream. | 06-11-2009 |
20090201731 | Method and Apparatus for Accessing Memory With Read Error By Changing Comparison - In response to a disagreement between a previously generated check code associated with previously programmed data bits and a more recently generated check code generated in response to a read command, the comparison process is changed, between i) a value representing accessed data and ii) a reference applied to such accesses to distinguish between logical levels. For example, the read bias arrangement and/or a read reference of a memory integrated circuit is changed. | 08-13-2009 |
20090273999 | SENSE AMPLIFIER AND DATA SENSING METHOD THEREOF - A data sensing method for sensing data stored in first and second memory cells includes the steps of: setting a first voltage according to a bit-line voltage corresponding to the first memory cell in response to an enabled level of a first clock signal; providing the first voltage as a sensing voltage in response to a disabled level of the first clock signal; comparing the sensing voltage with a reference voltage to generate a first output voltage; setting a second voltage according to a bit-line voltage corresponding to the second memory cell in response to an enabled level of a second clock signal, a phase difference between the first and second clock signals being 180 degrees; providing the second voltage as the sensing voltage in response to a disabled level of the second clock signal; and comparing the sensing voltage with the reference voltage to generate a second output voltage. | 11-05-2009 |
20090296506 | SENSE AMPLIFIER AND DATA SENSING METHOD THEREOF - A data sensing method for sensing storage data stored in a memory cell includes the steps of: biasing a sensing node and a reference node to a first voltage in response to a first control signal; discharging the sensing node and the reference node via the memory cell and a reference memory cell, respectively; enabling a latch circuit to amplify a voltage difference between the sensing node and the reference node. | 12-03-2009 |
20090310423 | METHOD OF PROGRAMMING AND ERASING A NON-VOLATILE MEMORY ARRAY - A method of processing an array of non-volatile memory cells to program or erase the same, by applying a voltage to the same through a program and verify pulse application circuit. The process includes a first step of selecting a voltage to be applied. Then, the maximum number of memory cells that can be processed simultaneously is determined, based on the selected voltage and characteristics of the memory cells and the circuit. The array is divided into processing groups, each group having a number of cells less than or equal to the maximum determined number. Finally, the voltage is applied to the cells. | 12-17-2009 |
20100007380 | LEVEL SHIFTER AND LEVEL SHIFTING METHOD THEREOF - A level shifter includes a first level-switching device and a second level-switching device. The first level-switching device includes a first switch device, a second switch device, a first control switch and a third switch device. The first switch device is for receiving the input voltage and outputting a first voltage. The second switch device is coupled to the first switch device for outputting a first operational voltage as the output voltage according to the first voltage. The first control switch is coupled to the first switch device for receiving the first voltage. The third switch device is coupled between the first control switch and the first operational voltage and controlled by the output voltage. The second level-switching device is coupled to the first level-switching device for receiving the input voltage and accordingly outputting a second operational voltage as the output voltage. | 01-14-2010 |
20100054045 | Memory and Reading Method Thereof - A memory includes many memory regions each including a target memory cell, a source line, a bit line and a reading control circuit. The source line is coupled to a first terminal of the target memory cell. The bit line is coupled to a second terminal of the target memory cell. The reading control circuit is for selectively applying a working voltage to the source line. | 03-04-2010 |
20100061174 | Y-DECODER AND DECODING METHOD THEREOF - AY-decoder includes a selection unit and a Y-MUX. The selection unit is coupled to the memory array for selecting the column lines. The Y-MUX is coupled to the selection unit for supplying a voltage to the selected column line. The Y-MUX includes a first switch, a second switch, a third switch and a fourth switch coupled in parallel. The first switch and the second switch are respectively for receiving a first shielding voltage and a second shielding voltage. The third switch and the fourth switch are respectively for receiving a first sensing voltage and a second sensing voltage. | 03-11-2010 |
20100082880 | PRE-CODE DEVICE, AND PRE-CODE SYSTEM AND PRE-CODING METHOD THEREROF - A pre-code device includes firstly memory circuit, an address decoder, and an alternative logic circuit. The first memory circuit includes a number of memory blocks and at east a replacing block. The memory blocks are pointed by a number of respective physical addresses. The replacing block is pointed by a replacing address. The address decoder decodes an input address to provide a pre-code address. The alternative logic circuit looks up an address mapping table, which maps defect physical address among the physical addresses to the replacing address, to map the pre-code address to the replacing address when the pre-code address corresponds to the defect physical address. The alternative logic circuit correspondingly pre-codes the pre-code data to the replacing block. | 04-01-2010 |
20100103738 | MEMORY AND OPERATING METHOD THEREOF - A method of programming data stored in a memory, which comprises a number of user-defined blocks, a number of manufacture-defined blocks, and an information block, includes the following steps. A programming address pointing to a user-defined block in the memory and programming data is obtained. After that, it is determined whether there is an empty manufacture-defined block among a number of user-defined blocks in the memory. If so, an information block in the memory is programmed to store the programming address and a replacing address pointing to the empty manufacture-defined block. The empty manufacture-defined block is programmed to store the programming data. | 04-29-2010 |
20100149893 | METHOD AND APPARATUS FOR PROTECTION OF NON-VOLATILE MEMORY IN PRESENCE OF OUT-OF-SPECIFICATION OPERATING VOLTAGE - A method and apparatus for protecting non-volatile memory is described. A write command is processed only when an operating voltage is between specified operating limits and when a data pattern stored in the non-volatile memory is repeatedly read successfully. | 06-17-2010 |
20100182834 | TWISTED DATA LINES TO AVOID OVER-ERASE CELL RESULT COUPLING TO NORMAL CELL RESULT - Over-erasure induced noise on a data line in a nonvolatile memory that couples into an adjacent data line is mitigated by using twisted data lines and differential sensing amplifiers. Noise coupled into data lines is compensated by similar noise coupled into reference data lines and cancelled in the differential sensing amplifiers. | 07-22-2010 |
20100182842 | Sense Amplifier and Data Sensing Method Thereof - A data sensing method for sensing data stored in first and second memory cells includes the steps of: setting a first voltage according to a bit-line voltage corresponding to the first memory cell in response to an enabled level of a first clock signal; providing the first voltage as a sensing voltage in response to a disabled level of the first clock signal; comparing the sensing voltage with a reference voltage to generate a first output voltage; setting a second voltage according to a bit-line voltage corresponding to the second memory cell in response to an enabled level of a second clock signal, a phase difference between the first and second clock signals being 180 degrees; providing the second voltage as the sensing voltage in response to a disabled level of the second clock signal; and comparing the sensing voltage with the reference voltage to generate a second output voltage. | 07-22-2010 |
20100301918 | Level Shifter and Level Shifting Method Thereof - A level shifter includes a first level-switching device and a second level-switching device. The first level-switching device includes a first switch device, a second switch device, a first control switch and a third switch device. The first switch device is for receiving the input voltage and outputting a first voltage. The second switch device is coupled to the first switch device for outputting a first operational voltage as the output voltage according to the first voltage. The first control switch is coupled to the first switch device for receiving the first voltage. The third switch device is coupled between the first control switch and the first operational voltage and controlled by the output voltage. The second level-switching device is coupled to the first level-switching device for receiving the input voltage and accordingly outputting a second operational voltage as the output voltage. | 12-02-2010 |
20110016291 | Serial Memory Interface for Extended Address Space - An integrated circuit memory device has a memory array and control logic with at least a first addressing mode in which the instruction includes a first instruction code and an address of a first length; and a second addressing mode in which the instruction includes the first instruction code and an address of a second length. The first length of the address is different from the second length of the address. | 01-20-2011 |
20110019456 | SENSE AMPLIFIER WITH SHIELDING CIRCUIT - A sense amplifier comprises a sense node, a reference node, a memory input stage circuit, a reference input stage circuit, an output stage circuit, and a shielding circuit. The memory input stage circuit comprises first input node for maintaining a first sense voltage established by a cell current and establishes a second sense voltage on the sense node in response to the first sense voltage. The reference input stage circuit comprises an output node and a second input node, which is for maintaining a first reference voltage established by the reference current and establishes a second reference voltage on the reference node in response to the first reference voltage. The output stage circuit obtains a sense result in response to the second reference voltage and the second sense voltage. The first shielding circuit shields the output node from being interfered with the second reference voltage on the reference node. | 01-27-2011 |
20110019473 | MEMORY ARRAY AND METHOD OF OPERATING ONE OF A PLURALITY OF MEMORY CELLS - An embodiment of the invention provides a memory array including a plurality of bit lines, a plurality of memory cells and a device. Each of the plurality of memory cells has a first node, a second node and a third node, wherein the third node is coupled to one of the plurality of bit lines. The device couples the plurality of bit lines together to form a common node for one of the plurality of memory cells. | 01-27-2011 |
20110019487 | APPARATUS AND METHOD FOR DETECTING WORD LINE LEAKAGE IN MEMORY DEVICES - According to an embodiment of the present invention, a method for detecting word line leakage in a memory device includes coupling a first word line in the memory device to a voltage source while coupling a second word line in the memory device to a ground level voltage. Next, the first word line is decoupled from the voltage source. The method also includes comparing a current of the first word line with a predetermined reference current for determining a leakage condition of the word line. | 01-27-2011 |
20110060962 | Method and Apparatus for Accessing Memory With Read Error By Changing Comparison - In response to a disagreement between a previously generated check code associated with previously programmed data bits and a more recently generated check code generated in response to a read command, the comparison process is changed, between i) a value representing accessed data and ii) a reference applied to such accesses to distinguish between logical levels. For example, the ratio of resistances characterizing input circuits of a sense amplifier and/or the read bias arrangement and/or a read reference of a memory integrated circuit is/are changed. | 03-10-2011 |
20110069544 | METHOD AND APPARATUS FOR PROGRAMMING A MULTI-LEVEL MEMORY - A method of programming a memory device comprising a plurality of memory cells may include verifying a first memory cell targeted to a first level with a first preliminary voltage of a first program phase (PPV | 03-24-2011 |
20110069571 | Word Line Decoder Circuit Apparatus and Method - One embodiment of the technology is an apparatus, a memory integrated circuit. The memory integrated circuit has word line address decoding circuitry. The circuit allows selection of a single word line to have an erase voltage. A decoder circuit includes an inverter and logic. The inverter has an input, and an output controlling a word line to perform the erase operation. A voltage range of the input extends between a first voltage reference and a second voltage reference. Examples of voltages references are a voltage supply and a ground. In some embodiments, this wide voltage range results from the input being free of a threshold voltage drop from preceding circuitry limiting the voltage range of the input. The logic of the decoder is circuit is controlled by a word line address to determine a value of the input of the inverter during the erase operation. | 03-24-2011 |
20110122721 | Y-Decoder and Decoding Method Thereof - A Y-decoder includes a selection unit and a Y-MUX. The selection unit is coupled to the memory array for selecting the column lines. The Y-MUX is coupled to the selection unit for supplying a voltage to the selected column line. The Y-MUX includes a first switch, a second switch, a third switch and a fourth switch coupled in parallel. The first switch and the second switch are respectively for receiving a first shielding voltage and a second shielding voltage. The third switch and the fourth switch are respectively for receiving a first sensing voltage and a second sensing voltage. | 05-26-2011 |
20110133804 | CLOCK INTEGRATED CIRCUIT - The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise. | 06-09-2011 |
20110138213 | Clock Integrated Circuit - The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise. | 06-09-2011 |
20110138216 | Clock Integrated Circuit - The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise. | 06-09-2011 |
20110149669 | Sense Amplifier and Data Sensing Method Thereof - A data sensing method for sensing storage data stored in a memory cell includes the steps of: biasing a sensing node and a reference node to a first voltage in response to a first control signal; discharging the sensing node and the reference node via the memory cell and a reference memory cell, respectively; enabling a latch circuit to amplify a voltage difference between the sensing node and the reference node. | 06-23-2011 |
20110161750 | Pre-Code Device, and Pre-Code System and Pre-Coding Method Thereof - A pre-code device includes firstly memory circuit, an address decoder, and an alternative logic circuit. The first memory circuit includes a number of memory blocks and at east a replacing block. The memory blocks are pointed by a number of respective physical addresses. The replacing block is pointed by a replacing address. The address decoder decodes an input address to provide a pre-code address. The alternative logic circuit looks up an address mapping table, which maps defect physical address among the physical addresses to the replacing address, to map the pre-code address to the replacing address when the pre-code address corresponds to the defect physical address. The alternative logic circuit correspondingly pre-codes the pre-code data to the replacing block. | 06-30-2011 |
20110210776 | Clock Integrated Circuit - The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise. | 09-01-2011 |
20110215837 | CLOCK GENERATOR CIRCUITS FOR GENERATING CLOCK SIGNALS - The present invention relates to a circuit for generating a clock signal. The circuit comprises a current source to generate a reference current and provide a first voltage V | 09-08-2011 |
20110216607 | METHOD AND APPARATUS FOR PROTECTION OF NON-VOLATILE MEMORY IN PRESENCE OF OUT-OF-SPECIFICATION OPERATING VOLTAGE - A method and apparatus for protecting non-volatile memory is described. A write command is processed only when an operating voltage is between specified operating limits and when a data pattern stored in the non-volatile memory is repeatedly read successfully. | 09-08-2011 |
20120007167 | 3D Memory Array With Improved SSL and BL Contact Layout - A 3D memory device includes a plurality of ridges, in some embodiments ridge-shaped, in the form of multiple strips of conductive material separated by insulating material, arranged as bit lines which can be coupled through decoding circuits to sense amplifiers. The strips of conductive material have side surfaces on the sides of the stacks. A plurality of conductive lines arranged as word lines which can be coupled to row decoders, extends orthogonally over the plurality of stacks. The conductive lines conform to the surface of the stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the semiconductor material strips on the stacks and the conductive lines. The memory elements are programmable, like the anti-fuses or charge trapping structures. In some embodiments, the 3D memory is made using only two critical masks for multiple layers. Some embodiments include a staircase-shaped structure positioned at ends of the semiconductor material strips. Some embodiments include SSL interconnects on a metal layer parallel to the semiconductor material strips, and further SSL interconnects on a higher metal layer, parallel to the word lines. | 01-12-2012 |
20120019232 | Current Source with Tunable Voltage-Current Coefficient - A current source providing an output current with a fixed current range includes a bias circuit, a resistor, a current mirror, and a controller. The bias circuit provides a first voltage weighted with a first tunable coefficient and a second voltage weighted with a second tunable coefficient. The resistor has a tunable resistance for determining a bias current according to a voltage difference between the first and the second voltages and the tunable resistance. The current mirror generates the output current according to the bias current. The controller adjusts the tunable resistance and one of the first and the second tunable coefficients to achieve a voltage-current coefficient with different values, while the bias current and the output current are kept within a fixed current range. | 01-26-2012 |
20120063232 | METHOD AND APPARATUS FOR REDUCING READ DISTURB IN MEMORY - Various aspects of a NAND memory include have multiple versions of a high threshold voltage distribution—a version with a reduced maximum, and another version. The version with a reduced maximum has a reduced word line pass voltage. | 03-15-2012 |
20120092937 | Method and System for A Serial Peripheral Interface - A method for dual I/O data read in an integrated circuit which includes a serial peripheral interface memory device. In an embodiment, the memory device includes a clock signal, a plurality of pins, and a configuration register. In an embodiment, the configuration register includes a wait cycle count. The method includes transmitting a read address to the memory device using a first input/output pin and a second input/output pin concurrently. In an embodiment, the read address includes at least a first address bit and a second address bit, the first address bit being transmitted using the first input/output pin, and the second address bit being transmitted using the second input/output pin. The method includes accessing the memory device for data associated with the address and waiting a predetermined number clock cycles associated with the wait cycle count. The method includes transferring the data from the memory device using the first input/output pin and the second input/output pin concurrently. | 04-19-2012 |
20120198298 | On-the-Fly Repair Method for Memory - An on-the-fly repair method for a memory includes: performing a block erase operation on the memory; checking whether the block erase operation is passed or not; finding whether there is any available and healthy redundancy block in the memory if the block erase operation is not passed; programming an address of a failed block to be repaired, an enable bit and at least one error correction bit into both first and second redundancy information regions in a redundancy information set of the memory; checking whether error in the first and the second redundancy information regions is recoverable based on the error correction bit; and if the error is recoverable, then programming the redundancy information set as effective to replace the failed block by the redundancy block related to the effective redundancy information set. | 08-02-2012 |
20120224443 | SENSE AMPLIFIER WITH SHIELDING CIRCUIT - A sense amplifier includes a first transistor, a second transistor, an output circuit, and a shielding circuit. The first transistor has a gate bias established by a cell current, and the second transistor has a gate bias established by a reference current. The output circuit is coupled to the first and the second transistor. The shielding circuit is located between the second transistor and the output circuit. | 09-06-2012 |
20120262987 | METHOD AND APPARATUS FOR LEAKAGE SUPPRESSION IN FLASH MEMORY IN RESPONSE TO EXTERNAL COMMANDS - Techniques are described herein for detecting and recovering over-erased memory cells in a flash memory device. In one embodiment, a flash memory device includes a memory array including a plurality of blocks of memory cells. The device also includes a command interface to receive a command from a source external to the memory device. The device also includes a controller including logic to perform a leakage-suppression process in response to the command. The leakage-suppression process includes performing a soft program operation to increase a threshold voltage of one or more over-erased memory cells in a given block of memory cells and establish an erased state. | 10-18-2012 |
20120262988 | METHOD AND APPARATUS FOR LEAKAGE SUPPRESSION IN FLASH MEMORY - Techniques are described herein for detecting and recovering over-erased memory cells in a flash memory device. In one embodiment, a flash memory device is described including a memory array including a plurality of blocks of memory cells. The device also includes a controller to perform a leakage-suppression process. The leakage-suppression process includes determining that a given block of memory cells includes one or more over-erased memory cells. Upon the determination, the leakage-suppression process also includes performing a soft program operation to increase the threshold voltage of the over-erased memory cells in the given block. | 10-18-2012 |
20120265923 | Program Method, Data Recovery Method, and Flash Memory Using the Same - A program method for a multi-level cell (MLC) flash memory is provided. The memory array includes a plurality of pages and a plurality of paired pages, which correspond to the respective pages. The program method includes the following steps. Firstly, a program address command is obtained. Next, whether the program address command corresponding to any one of the paired pages is determined. When the program address command corresponds to a first paired page, which corresponds to a first page among the pages, among the paired pages, data stored in the first page to a non-volatile memory are copied. After that, the first paired page is programmed. | 10-18-2012 |
20120281471 | Memory Page Buffer - Various embodiments address various difficulties with source side sensing difficulties in various memory architectures, such as 3D vertical gate flash and multilevel cell memory. One such difficulty is that with source side sensing, the signal amplitude is significantly smaller than drain side sensing. Another such difficulty is the noise and reduced sensing margins associated with multilevel cell memory. In some embodiments the bit line is selectively discharged prior to applying the read bias arrangement. | 11-08-2012 |
20120300553 | Method and Apparatus of Performing An Erase Operation On A Memory Integrated Circuit - Various discussed approaches improve the over erase issue and the coupling effect, and include (A) multilevel contacts between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line; (B) a sufficient separation distance between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line. These are examples of electrically isolating (i) the first outer selected word line of an erase group, from (ii) the first unselected word line outside the ease group neighboring the first outer selected word line. | 11-29-2012 |
20120319756 | Clock Integrated Circuit - The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise. | 12-20-2012 |
20120327722 | Method and System for a Serial Peripheral Interface - An integrated circuit includes a serial peripheral interface memory device. In an embodiment, the memory device includes a clock signal, a plurality of pins, and a configuration register. In an embodiment, the configuration register includes a wait cycle count. The method includes transmitting a read address to the memory device using a first input/output pin and a second input/output pin concurrently. In an embodiment, the read address includes at least a first address bit and a second address bit, the first address bit being transmitted using the first input/output pin, and the second address bit being transmitted using the second input/output pin. The method includes accessing the memory device for data associated with the address and waiting a predetermined number clock cycles associated with the wait cycle count. The method includes transferring the data from the memory device using the first input/output pin and the second input/output pin concurrently. | 12-27-2012 |
20130094319 | Method and Apparatus of Addressing A Memory Integrated Circuit - A memory integrated circuit has control circuitry that accesses memory cells of the memory integrated circuit. The control circuitry is responsive to commands including a first command and a second command. The first command specifies a high order set of address bits. The second command specifies a low order set of address bits. The high order set of address bits and the low order set of address bits constitute a complete access address of the memory integrated circuit. The first command and the second command have different in command codes. | 04-18-2013 |
20130100745 | Method and Apparatus of Performing An Erase Operation On A Memory Integrated Circuit - Various discussed approaches include an improved grouping of edge word lines and center word lines of an erase group during erase verify and erase sub-operations of an erase operation. In another approach, changed voltage levels of edge word lines to address the over-erase issue of the erase group, and also improve erase time performance. Another approach uses dummy word lines. | 04-25-2013 |
20130100758 | LOCAL WORD LINE DRIVER - A memory circuit with a word line driver and control circuitry is disclosed. The word line driver receives a first voltage reference signal, a second voltage reference signal, and an input signal. The word line driver has an output coupled to a word line. The control circuitry is configured to deselect the word line by applying the input signal to the input of the word line driver. For example, in a program operation the word line is deselected to indicate that the word line is not programmed, and another word line is selected to be programmed. During an operation in which the word line is deselected and another word line is selected, the word line discharges through both of a first p-type transistor and a first n-type transistor of the word line driver. | 04-25-2013 |
20130107637 | Memory Program Discharge Circuit of Bit Lines With Multiple Discharge Paths | 05-02-2013 |
20130128670 | MEMORY ACCESS METHOD AND FLASH MEMORY USING THE SAME - A memory access method is applied in a memory controller for accessing an NAND memory array, including a number of respective select switches globally controlled with a string select signal. The memory access method includes the following steps. A stream bias signal and a selected word line signal are respectively provided on a selected stream and on a selected cell of the selected stream, and the rest of memory cells are turned on as pass transistors, in the setup phase. A discharge path is provided to eliminate coupling charge presented on unselected streams, in the setup phase. Then, the string select signal is enabled to have the selected stream connected to a sense unit via a metal bit line and according read the selected cell in a voltage sensing scheme, in a read phase, which does not overlap with the setup phase. | 05-23-2013 |
20130145201 | AUTOMATIC INTERNAL TRIMMING CALIBRATION METHOD TO COMPENSATE PROCESS VARIATION - A method is described for performing an automatic internal trimming operation that can compensate process variation and supply voltage variation in an integrated circuit. A reference signal is applied when the integrated circuit is in an automatic internal trimming mode, and integrated circuit timing is trimmed into a predetermined target range after applying predefined reference cycles. | 06-06-2013 |
20130148445 | LOCAL WORD LINE DRIVER - A memory circuit with a word line driver and control circuitry is disclosed. The plurality of word line drivers are coupled to a plurality of word lines. Word line drivers include a CMOS inverter, which can have an input and an output, and a p-type transistor and an n-type transistor. The output of the CMOS inverter is coupled to one of the plurality of word lines. The control circuitry has multiple modes, including at least a first mode to discharge a particular word line of the plurality of word lines via a first discharge path such as at least a first transistor type of the CMOS inverter; and a second mode to discharge the particular word line of the plurality of word lines via a second discharge path such as at least the a second transistor type of the CMOS inverter. | 06-13-2013 |
20130208552 | Method and Apparatus for Adjusting Drain Bias of A Memory Cell With Addressed and Neighbor Bits - The storage layer such as a nitride layer of a nonvolatile memory cell has two storage parts storing separately addressable data, typically respectively proximate to the source terminal and the drain terminal. The applied drain voltage while sensing the data of one of the storage parts depends on the data stored at the other storage part. If the data stored at the other storage part is represented by a threshold voltage exceeding a minimum threshold voltage, then the applied drain voltage is raised. This technology is useful in read operations and program verify operations to widen the threshold voltage window. | 08-15-2013 |
20130214820 | APPARATUS AND METHOD TO TOLERATE FLOATING INPUT PIN FOR INPUT BUFFER - An integrated circuit device includes a pad adapted to receive a signal from an internal or external driver, and an input buffer circuit including an input terminal coupled to the pad. The input buffer circuit includes a pass transistor having a control terminal, a first conduction terminal connected to the pad, and a second conduction terminal connected to a first voltage. The input buffer circuit also includes a latch having a terminal electrically coupled to the control terminal of the pass transistor. The input buffer circuit further includes circuitry coupled to the latch, the circuitry including a feedback transistor having a control terminal electrically coupled to the pad, a first conduction terminal electrically coupled to a second voltage, and a second conduction terminal coupled to the latch. | 08-22-2013 |
20130215687 | Method and Apparatus for Dynamic Sensing Window in Memory - A memory array is characterized by a threshold definition, which includes threshold voltage ranges representing data values stored by a part of the memory array, and a set of sense windows separating the threshold voltage ranges. The threshold definition is varied, responsive to at least one of program operations and erase operations. Such operations change a distribution of the data values stored in the memory group. | 08-22-2013 |
20130235674 | MEMORY PAGE BUFFER - Various embodiments address various difficulties with source side sensing difficulties in various memory architectures, such as 3D vertical gate flash and multilevel cell memory. One such difficulty is that with source side sensing, the signal amplitude is significantly smaller than drain side sensing. Another such difficulty is the noise and reduced sensing margins associated with multilevel cell memory. In some embodiments the bit line is selectively discharged prior to applying the read bias arrangement. | 09-12-2013 |
20130250675 | Method and Apparatus for Reducing Erase Disturb of Memory By Using Recovery Bias - A nonvolatile memory array is divided into multiple memory groups. The nonvolatile memory array receives an erase command to erase a first set of the memory groups, and not a second set of the memory groups. The control circuitry is responsive to the erase command to erase the first set of memory groups, by applying a recovery bias arrangement that adjusts threshold voltages of memory cells in at least one memory group of the second set of memory groups. By applying the recovery bias arrangement to memory cells in at least one memory group of the second set of memory groups, erase disturb is corrected during the recovery bias arrangement, at least in part. | 09-26-2013 |
20130285737 | Charge Pump System - In one aspect, a first charge pump has serially arranged charge pump stages. Inter-stage nodes between adjacent stages are pumped by a second charge pump. In another aspect, timing of the charge pump stages is controlled by at a command clock signal. The command clock signal and command data are communicated between a integrated circuit with the charge pump and an external circuit. | 10-31-2013 |
20130286744 | Bit Line Bias Circuit With Varying Voltage Drop - A bit line bias circuit of a memory architecture includes a varying voltage drop. In some embodiments, the voltage drop can depend on the threshold voltage of the memory cell selected to be read, or on the sense current flowing through the memory cell selected to be read. | 10-31-2013 |
20130294155 | PLURAL OPERATION OF MEMORY DEVICE - An integrated circuit device comprises a semiconductor substrate, a first memory block on the substrate comprising NAND memory cells, a second memory block on the substrate comprising NAND memory cells, and controller circuitry. The first and second memory blocks are configurable to store data for a first pattern of data usage in response to a first operation algorithm to read, program and erase data, and for a second pattern of data usage in response to a second operation algorithm to read, program and erase data, respectively. The controller circuitry is coupled to the first and second memory blocks, and is configured to execute the first and second operation algorithms, wherein a word line pass voltage for read operations applied in the first operation algorithm is at a lower voltage level than a second word line pass voltage for read operations applied in the second operation algorithm. | 11-07-2013 |
20130294173 | METHOD AND APPARATUS FOR THE ERASE SUSPEND OPERATION - Various aspects of a nonvolatile memory have an improved erase suspend procedure. A bias arrangement is applied to word lines of an erase sector undergoing an erase procedure interrupted by an erase suspend procedure. As a result, another operation performed during erase suspend, such as a read operation or program operation, has more accurate results due to decreased leakage current from any over-erased nonvolatile memory cells of the erase sector. | 11-07-2013 |
20130314997 | Memory Access Method and Flash Memory Using the Same - A memory access method is applied in a memory controller for accessing a memory array, including a number of respective select switches globally controlled with a string select signal. The memory access method includes: enabling the string select signal and disabling the string select signal before a read phase. | 11-28-2013 |
20130326184 | MEMORY APPARATUS - A memory apparatus includes a host device and a slave device. The host device stores verification data. The slave device includes a memory unit, a control unit, and a logic unit. The control unit drives the memory unit to provide storage data in a data transmission sub-period, and further provides a control signal, indicating the first verification data, in a dummy sub-period. The logic unit provides first preamble data, indicating substantially a same data value as the verification data, in the dummy sub-period in response to the first control signal. The preamble data and the storage data are transmitted according to an internal clock signal. The host device samples the first preamble data according to an external clock signal, and determines whether the external and the internal clock signals are synchronized by comparing the first preamble data and the first verification data. | 12-05-2013 |
20140021935 | VOLTAGE BUFFER APPARATUS - The present invention relates to an apparatus of bandgap buffer which comprising a voltage processing module to produce a bandgap buffer voltage in response to an input voltage and a feedback signal and a symmetry circuit coupled to the voltage processing module for producing the feedback signal and regulating the feedback signal in response to the input voltage. | 01-23-2014 |
20140055187 | CLOCK INTEGRATED CIRCUIT - The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise. | 02-27-2014 |
20140075265 | Outputting Information of ECC Corrected Bits - The present invention provides a method of operating a memory device storing error correcting codes ECCs for corresponding data and including ECC logic to correct errors using the ECCs. The method includes correcting data using ECCs for the data on the memory device, and producing information on the memory device about the use of the ECCs. The method provides the ECC information on an output port of the device in response to a command received on an input port from a process external to the memory device. The present invention also provides a method of controlling a memory device. The method includes sending a command to the memory device requesting ECC information corresponding to data in the memory device, and receiving the ECC information from the memory device in response to the command. The method includes performing a memory management function using the ECC information. | 03-13-2014 |
20140098616 | METHOD AND APPARATUS FOR REDUCING READ DISTURB IN MEMORY - Various aspects of a NAND memory include a control circuit that applies a read bias arrangement to a plurality of word lines to read a selected data value stored on a plurality of memory cells by measuring current flowing between the first end and the second end of the series of memory cells. The read bias arrangement is applied to word lines of the plurality of word lines applies only word line voltages less than a second maximum of a second threshold voltage distribution. | 04-10-2014 |
20140141583 | MEMORY ARCHITECTURE OF 3D ARRAY WITH DIODE IN MEMORY STRING - A 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of conductive material separated by insulating material, arranged as strings which can be coupled through decoding circuits to sense amplifiers. Diodes are connected to the bit line structures at either the string select of common source select ends of the strings. The strips of conductive material have side surfaces on the sides of the ridge-shaped stacks. A plurality of conductive lines arranged as word lines which can be coupled to row decoders, extends orthogonally over the plurality of ridge-shaped stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the conductive strips on the stacks and the conductive lines. | 05-22-2014 |
20140146611 | MEMORY DEVICE AND METHOD FOR PROGRAMMING MEMORY CELL OF MEMORY DEVICE - A method for programming a memory cell of a memory device includes the following steps. A plurality of cycle number ranges are set up. A specific one of the plurality of cycle number ranges, in which the memory cell having a drain terminal passes a program-verification, is determined. A bias voltage is applied to the drain terminal for programming the memory cell, wherein the bias voltage varies with the specific cycle number range. | 05-29-2014 |
20140210522 | DRIVE CIRCUITRY COMPENSATED FOR MANUFACTURING AND ENVIRONMENTAL VARIATION - Current drivers and biasing circuitry at least partly compensate for manufacturing variations and environmental variations such as supply voltage, temperature, and fabrication process. | 07-31-2014 |
20140241070 | REFERENCE AND SENSING WITH BIT LINE STEPPING METHOD OF MEMORY - A sensing method for a memory is provided. The memory includes: a memory cell; a reference circuit generating a reference voltage and a clamp voltage; and a current supplying circuit receiving the clamp voltage to develop a cell current passing through the memory cell to form a cell voltage, wherein the cell voltage is used for incorporating with the reference voltage to determine the information stored in the memory. | 08-28-2014 |
20140254257 | Memory And Memory Managing Method - A method for managing memory includes setting a state of a first memory cell to a first state representing a first data and setting a state of a second memory cell to a second state representing the first data. If the state of the second memory cell has changed to a third state representing a second data different from the first data, the method also includes changing the state of the second memory cell back to the second state. | 09-11-2014 |
20140254284 | WORD LINE DRIVER CIRCUIT FOR SELECTING AND DESELECTING WORD LINES - A memory circuit includes word lines coupled to a memory array, including a first set of one or more word lines deselected in an erase operation, and a second set of one or more word lines selected in the erase operation. Control circuitry couples the first set of one or more word lines deselected in the erase operation to a reference voltage, responsive to receiving an erase command for the erase operation. Some examples further include a first transistor that switchably couples a word line to a global word line, and a second transistor that switchably couples the word line to a ground voltage. The control circuitry is coupled to the first transistor and the second transistor, wherein the control circuitry has a plurality of modes including at least an erase operation. In a first mode, the first transistor couples the word line to the global word line, and the second transistor decouples the word line from the ground voltage. In a second mode, the first transistor decouples the word line from the global word line, and the second transistor couples the word line to the ground voltage. | 09-11-2014 |
20140254297 | METHOD AND APPARATUS FOR MEMORY REPAIR - An integrated circuit includes an array of memory cells that is arranged into rows, main columns, and redundant columns that perform repairs in the array. The main columns and the redundant columns are divided into row blocks. Bit lines couple the main columns to status memory indicating repair statuses of the repairs by the redundant columns. The integrated circuit receives a command, and performs an update on the status memory with the repair statuses specific to particular ones of the row blocks in a portion of the memory accessed by the command. Alternatively or in combination, the status memory has insufficient size to store the repair statuses of multiple ones of the row blocks of the main columns. | 09-11-2014 |
20140258794 | MEMORY PAGE BUFFER - Counting status circuits are electrically coupled to corresponding status elements. The status elements selectably store a bit status of a bit line coupled to a memory array. The bit status can indicate one of at least pass and fail. The counting status circuits are electrically coupled to each other in a sequential order. Control logic causes processing of the counting status circuits in the sequential order to determine a total of the memory elements that store the bit status. The total number of memory elements that store the bit status indicate the number of error bits or non-error bits, which can help determine whether there are too many errors to be fixed by error correction codes. | 09-11-2014 |
20140258811 | STORAGE SCHEME FOR BUILT-IN ECC OPERATIONS - A device includes a memory array storing data and error correcting codes ECCs corresponding to the data, and a multi-level buffer structure between the memory array and an input/output data path. The memory array includes a plurality of data lines for page mode operations. The buffer structure includes a first buffer having storage cells connected to respective data lines in the plurality of data lines for a page of data, a second buffer coupled to the storage cells in the first buffer for storing at least one page of data, and a third buffer coupled to the second buffer and to the input/output data path. The device includes logic coupled to the multi-level buffer to perform a logical process over pages of data during movement between the memory array and the input/output path through the multi-level buffer for at least one of page read and page write operations. | 09-11-2014 |
20140269074 | MANAGEMENT OF NON-VOLATILE MEMORY - A method for programming a non-volatile memory including a plurality of blocks, each block including a plurality of sections, each section including at least one page, and each page including a plurality of memory cells. The method includes checking a current section of the plurality of sections against a damaged section table to determine whether the current section is damaged. The damaged section table records information about whether a section in the memory is good or damaged. The method further includes using the current section for programming if the current section is not damaged. | 09-18-2014 |
20140269127 | Memory Operation Latency Control - An integrated circuit with memory can operate with reduced latency between consecutive operations such as read operations. At a first time, a first operation command is finished on a memory array on an integrated circuit. At a second time, a second operation command is begun on the memory array. A regulated output voltage from the charge pump is coupled to word lines in the memory array. From the first time to the second time, a regulated output voltage is maintained at about a word line operation voltage such as a read voltage. | 09-18-2014 |
20140281150 | DIFFERENCE L2P METHOD - A method for maintaining a data set includes storing a base copy of the data set in a first non-volatile memory having a first writing speed, storing changes to the data set in a first change data set in a second non-volatile memory having a second writing speed, and generating a current copy of the data set by reading the base copy and the changes. If a threshold number of entries in the first change data set is reached, then part or all of the first change data set is moved into a second change data set in the first non-volatile memory, where the generating step includes reading the second change data set. If a threshold number of entries in the second change data set is reached, then the current copy is generated by reading the base copy and the changes in the first and the second non-volatile memory. | 09-18-2014 |
20140281175 | Program Method, Data Recovery Method, and Flash Memory Using the Same - A program method for a multi-level cell (MLC) flash memory is provided. The memory array includes a plurality of pages and a plurality of paired pages, which correspond to the respective pages. The program method includes the following steps. Firstly, a program address command is obtained. Next, whether the program address command corresponding to any one of the paired pages is determined. When the program address command corresponds to a first paired page, which corresponds to a first page among the pages, among the paired pages, data stored in the first page to a non-volatile memory are copied. After that, the first paired page is programmed. | 09-18-2014 |
20140286097 | THERMALLY ASSISTED FLASH MEMORY WITH DIODE STRAPPING - A memory includes an array of memory cells including rows and columns. The memory includes circuitry coupled to the word lines applying a first bias voltage to a first set of spaced-apart locations on a word line or word lines in the array, while applying a second bias voltage different than the first bias voltage, to a second set of spaced-apart locations on the word line or word lines, locations in the first set of spaced-apart locations being interleaved among locations in the second set of spaced-apart locations, whereby current flow is induced between locations in the first and second sets of locations that cause heating of the word line or word lines. | 09-25-2014 |
20140361824 | CLOCK INTEGRATED CIRCUIT - The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise. | 12-11-2014 |
20150054057 | 3D MEMORY ARRAY WITH IMPROVED SSL AND BL CONTACT LAYOUT - A 3D memory device includes a plurality of ridges, in some embodiments ridge-shaped, in the form of multiple strips of conductive material separated by insulating material, arranged as bit lines which can be coupled through decoding circuits to sense amplifiers. The strips of conductive material have side surfaces on the sides of the stacks. A plurality of conductive lines arranged as word lines which can be coupled to row decoders, extends orthogonally over the plurality of stacks. The conductive lines conform to the surface of the stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the semiconductor material strips on the stacks and the conductive lines. The memory elements are programmable, like the anti-fuses or charge trapping structures. In some embodiments, the 3D memory is made using only two critical masks for multiple layers. Some embodiments include a staircase-shaped structure positioned at ends of the semiconductor material strips. Some embodiments include SSL interconnects on a metal layer parallel to the semiconductor material strips, and further SSL interconnects on a higher metal layer, parallel to the word lines. | 02-26-2015 |
20150055412 | METHOD AND APPARATUS FOR REDUCING ERASE DISTURB OF MEMORY BY USING RECOVERY BIAS - A nonvolatile memory array is divided into multiple memory groups. The nonvolatile memory array receives an erase command to erase a first set of the memory groups, and not a second set of the memory groups. The control circuitry is responsive to the erase command to erase the first set of memory groups, by applying a recovery bias arrangement that adjusts threshold voltages of memory cells in at least one memory group of the second set of memory groups. By applying the recovery bias arrangement to memory cells in at least one memory group of the second set of memory groups, erase disturb is corrected during the recovery bias arrangement, at least in part. | 02-26-2015 |
20150063023 | PLURAL OPERATION OF MEMORY DEVICE - An integrated circuit device comprises a semiconductor substrate, a first memory block on the substrate comprising NAND memory cells, a second memory block on the substrate comprising NAND memory cells, and controller circuitry. The first and second memory blocks are configurable to store data for a first pattern of data usage in response to a first operation algorithm to read, program and erase data, and for a second pattern of data usage in response to a second operation algorithm to read, program and erase data, respectively. The controller circuitry is coupled to the first and second memory blocks, and is configured to execute the first and second operation algorithms, wherein a word line pass voltage for read operations applied in the first operation algorithm is at a lower voltage level than a second word line pass voltage for read operations applied in the second operation algorithm. | 03-05-2015 |
20150085588 | METHOD AND APPARATUS FOR ADJUSTING DRAIN BIAS OF A MEMORY CELL WITH ADDRESSED AND NEIGHBOR BITS - The storage layer such as a nitride layer of a nonvolatile memory cell has two storage parts storing separately addressable data, typically respectively proximate to the source terminal and the drain terminal. The applied drain voltage while sensing the data of one of the storage parts depends on the data stored at the other storage part. If the data stored at the other storage part is represented by a threshold voltage exceeding a minimum threshold voltage, then the applied drain voltage is raised. This technology is useful in read operations and program verify operations to widen the threshold voltage window. | 03-26-2015 |