Patent application number | Description | Published |
20120267423 | Methods and Apparatus for Thin Die Processing - A vacuum tip and methods for processing thin integrated circuit dies. A vacuum tip for attaching to an integrated circuit die is disclosed comprising a vacuum port configured to connect to a vacuum supply on an upper surface and having a bottom surface; and at least one vacuum hole extending through the vacuum tip and exposed at the bottom surface of the vacuum tip; wherein the vacuum tip is configured to physically contact a surface of an integrated circuit die. Methods for processing integrated circuit dies are disclosed. | 10-25-2012 |
20120299181 | Package-on-Package Process for Applying Molding Compound - A method of packaging includes placing a package component over a release film, wherein solder balls on a surface of the package component are in physical contact with the release film. Next, A molding compound filled between the release film and the package component is cured, wherein during the step of curing, the solder balls remain in physical contact with the release film. | 11-29-2012 |
20130062761 | Packaging Methods and Structures for Semiconductor Devices - Packaging methods and structures for semiconductor devices are disclosed. In one embodiment, a packaged semiconductor device includes a redistribution layer (RDL) having a first surface and a second surface opposite the first surface. At least one integrated circuit is coupled to the first surface of the RDL, and a plurality of metal bumps is coupled to the second surface of the RDL. A molding compound is disposed over the at least one integrated circuit and the first surface of the RDL. | 03-14-2013 |
20130075921 | Forming Packages Having Polymer-Based Substrates - A method includes applying a polymer-comprising material over a carrier, and forming a via over the carrier. The via is located inside the polymer-comprising material, and substantially penetrates through the polymer-comprising material. A first redistribution line is formed on a first side of the polymer-comprising material. A second redistribution line is formed on a second side of the polymer-comprising material opposite to the first side. The first redistribution line is electrically coupled to the second redistribution line through the via. | 03-28-2013 |
20130089952 | Packaging Process Tools and Packaging Methods for Semiconductor Devices - Packaging process tools and packaging methods for semiconductor devices are disclosed. In one embodiment, a packaging process tool for semiconductor devices includes a mechanical structure including a frame. The frame includes a plurality of apertures adapted to retain a plurality of integrated circuit dies therein. The frame includes at least one hollow region. | 04-11-2013 |
20130095608 | Methods for Forming 3DIC Package - A method includes dispensing an underfill between a first package component and a second package component, wherein the first package component is placed on a lower jig, and the second package component is over and bonded to the first package component. A through-opening is in the lower jig and under the first package component. The underfill is cured, wherein during the step of curing the underfill, a force is applied to flatten the first package component. The force is applied by performing an action selected from the group consisting of vacuuming and air blowing through the through-opening. | 04-18-2013 |
20130095611 | Packaging Methods for Semiconductor Devices - Packaging methods for semiconductor devices are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a workpiece including a plurality of packaging substrates. A portion of the workpiece is removed between the plurality of packaging substrates. A die is attached to each of the plurality of packaging substrates. | 04-18-2013 |
20130099370 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a workpiece with a conductive trace and a chip with a conductive pillar. The chip is attached to the workpiece and a solder joint region is formed between the conductive pillar and the conductive trace. The distance between the conductive pillar and the conductive trace is less than or equal to about 16 μm. | 04-25-2013 |
20130099385 | Packages and Methods for Forming the Same - A device includes a package component having conductive features on a top surface, and a polymer region molded over the top surface of the first package component. A plurality of openings extends from a top surface of the polymer region into the polymer region, wherein each of the conductive features is exposed through one of the plurality of openings. The plurality of openings includes a first opening having a first horizontal size, and a second opening having a second horizontal size different from the first horizontal size. | 04-25-2013 |
20130115735 | Apparatus and Methods for Molded Underfills in Flip Chip Packaging - Methods and apparatus for a forming molded underfills. A method is disclosed including loading a flip chip substrate into a selected one of the upper mold chase and lower mold chase of a mold press at a first temperature; positioning a molded underfill material in the at least one of the upper and lower mold chases while maintaining the first temperature which is lower than a melting temperature of the molded underfill material; forming a sealed mold cavity and creating a vacuum in the mold cavity; raising the temperature of the molded underfill material to a second temperature greater than the melting point to cause the molded underfill material to flow over the flip chip substrate forming an underfill layer and forming an overmolded layer; and cooling the flip chip substrate to a third temperature substantially lower than the melting temperature of the molded underfill material. An apparatus is disclosed. | 05-09-2013 |
20130143361 | Packaging Process Tools and Systems, and Packaging Methods for Semiconductor Devices - Packaging process tools and systems, and packaging methods for semiconductor devices are disclosed. In one embodiment, a packaging process tool for semiconductor devices includes a mechanical structure for supporting package substrates or integrated circuit die during a packaging process for the integrated circuit die. The mechanical structure includes a low thermal conductivity material disposed thereon. | 06-06-2013 |
20130143364 | METHOD OF PROCESSING SOLDER BUMP BY VACUUM ANNEALING - A method includes vacuum annealing on a substrate having at least one solder bump to reduce voids at an interface of the at least one solder bump. A die is mounted over the substrate. | 06-06-2013 |
20130154086 | Exposing Connectors in Packages Through Selective Treatment - A method includes performing an etching step on a package. The package includes a package component, a connector on a top surface of the package component, a die bonded to the top surface of the package component, and a molding material molded over the top surface of the package component. The molding material covers the connector, wherein a portion of the molding material covering the connector is removed by the etching step, and the connector is exposed. | 06-20-2013 |
20130187268 | Semiconductor Packaging Structure and Method - A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A post-contact material is formed on the first contact in order to adjust the height of a joint between the contact pad a conductive bump. In another embodiment a conductive pillar is utilized to control the height of the joint between the contact pad and external connections. | 07-25-2013 |
20130214401 | System and Method for Fine Pitch PoP Structure - A fine pitch package-on-package (PoP), and a method of forming, are provided. The PoP may be formed by placing connections, e.g., solder balls, on a first substrate having a semiconductor die attached thereto. A first reflow process is performed to elongate the solder balls. Thereafter, a second substrate having another semiconductor die attached thereto is connected to the solder balls. A second reflow process is performed to form an hourglass connection. | 08-22-2013 |
20130234317 | Packaging Methods and Packaged Semiconductor Devices - Packaging methods and packaged semiconductor devices are disclosed. In one embodiment, a packaging method includes providing a first die, partially packaging the first die, and forming a plurality of solder balls on a surface of the partially packaged first die. An epoxy flux is disposed over the plurality of solder balls. A second die is provided, and the second die is partially packaged. The plurality of solder balls is coupled to the partially packaged second die. | 09-12-2013 |
20130260535 | METHOD AND APPARATUS FOR REDUCING PACKAGE WARPAGE - Embodiments of mechanisms for flattening a packaged structure are provided. The mechanisms involve a flattening apparatus and the utilization of protection layer(s) between the packaged structure and the surface(s) of the flattening apparatus. The protection layer(s) is made of a soft and non-sticking material to allow protecting exposed fragile elements of the packaged structure and easy separation after processing. The embodiments of flattening process involve flattening the warped packaged structure by pressure under elevated processing temperature. Processing under elevated temperature allows the package structure to be flattened within a reasonable processing time. | 10-03-2013 |
20140042622 | Fine Pitch Package-on-Package Structure - A package-on-package (PoP) device including a substrate having an array of contact pads arranged around a periphery of the substrate, a logic chip mounted to the substrate inward of the array of contact pads, and non-solder bump structures mounted on less than an entirety of the contact pads available. | 02-13-2014 |
20140048934 | METHOD TO CONTROL UNDERFILL FILLET WIDTH - A semiconductor device assembly includes a substrate having an area of the surface treated to form a surface roughness. A die is mounted on the substrate by a plurality of coupling members. An underfill substantially fills a gap disposed between the substrate and the die, wherein a fillet width of the underfill is substantially limited to the area of surface roughness. | 02-20-2014 |
20140072406 | FAN STRUCTURE WITH EASY ASSEMBLY - A fan structure includes at least one installation standoff, a fan and a fixing frame. An end of the at least one installation standoff is installed on a substrate, and a positioning slot is formed on the other end of the at least one installation standoff. The fixing frame is installed on the fan and includes at least one positioning hook for engaging with the positioning slot of the at least one installation standoff, so as to fix the fixing frame on the substrate. A guiding slot is formed on at least one side of the fixing frame for guiding the at least one installation standoff to move on the fixing frame. The fixing frame further includes at least one resilient portion connected to the at least one positioning hook for driving the at least one positioning hook to separate from the at least one positioning slot. | 03-13-2014 |
20140091509 | Methods for Forming 3DIC Package - A method includes dispensing an underfill between a first package component and a second package component, wherein the first package component is placed on a lower jig, and the second package component is over and bonded to the first package component. A through-opening is in the lower jig and under the first package component. The underfill is cured, wherein during the step of curing the underfill, a force is applied to flatten the first package component. The force is applied by performing an action selected from the group consisting of vacuuming and air blowing through the through-opening. | 04-03-2014 |
20140131896 | Exposing Connectors in Packages Through Selective Treatment - A method includes performing an etching step on a package. The package includes a package component, a connector on a top surface of the package component, a die bonded to the top surface of the package component, and a molding material molded over the top surface of the package component. The molding material covers the connector, wherein a portion of the molding material covering the connector is removed by the etching step, and the connector is exposed. | 05-15-2014 |
20140151878 | System and Method for Fine Pitch PoP Structure - A fine pitch package-on-package (PoP), and a method of forming, are provided. The PoP may be formed by placing connections, e.g., solder balls, on a first substrate having a semiconductor die attached thereto. A first reflow process is performed to elongate the solder balls. Thereafter, a second substrate having another semiconductor die attached thereto is connected to the solder balls. A second reflow process is performed to form an hourglass connection. | 06-05-2014 |
20140231988 | Packaging Methods and Packaged Semiconductor Devices - Packaging methods and packaged semiconductor devices are disclosed. In one embodiment, a packaging method includes providing a first die, partially packaging the first die, and forming a plurality of solder balls on a surface of the partially packaged first die. An epoxy flux is disposed over the plurality of solder balls. A second die is provided, and the second die is partially packaged. The plurality of solder balls is coupled to the partially packaged second die. | 08-21-2014 |
20140264849 | Package-on-Package Structure - A device comprises a bottom package mounted on a printed circuit board, wherein the bottom package comprises a plurality of first bumps formed between the bottom package and the printed circuit board, a first underfill layer formed between the printed circuit board and the bottom package, a semiconductor die mounted on the bottom package and a top package bonded on the bottom package, wherein the top package comprises a plurality of second bumps and the top package and the bottom package form a ladder shaped structure. The device further comprises a second underfill layer formed between the bottom package and the top package, wherein the second underfill layer is formed of a same material as the first underfill layer. | 09-18-2014 |
20140264858 | Package-on-Package Joint Structure with Molding Open Bumps - A device comprises a bottom package comprising a plurality of metal bumps formed on a first side of the bottom package and a plurality of first bumps formed on a second side of the bottom package, a top package bonded on the bottom package, wherein the top package comprises a plurality of second bumps, and wherein second bumps and respective metal bumps form a joint structure and an underfill layer formed between the top package and the bottom package, wherein the metal bumps are embedded in the underfill layer. | 09-18-2014 |
20140331462 | Packaging Process Tools and Packaging Methods for Semiconductor Devices - Packaging process tools and packaging methods for semiconductor devices are disclosed. In one embodiment, a packaging process tool for semiconductor devices includes a mechanical structure including a frame. The frame includes a plurality of apertures adapted to retain a plurality of integrated circuit dies therein. The frame includes at least one hollow region. | 11-13-2014 |
20140370659 | SINGULATION APPARATUS AND METHOD - A singulation apparatus includes a carrier having a plurality of singulation sites and a scribe line between each of the plurality of singulation sites and an adjacent singulation site. The carrier has a top surface configured to receive a semiconductor substrate thereon. Each of the plurality of singulation sites includes a deformable portion and at least one vacuum hole. The at least one vacuum hole and the deformable portion is configured to form a seal around the at least one vacuum holes when a force is applied. The present disclosure further includes a method of manufacturing semiconductor devices, especially for a singulation process. | 12-18-2014 |
20150044819 | Packaging Methods and Structures for Semiconductor Devices - Packaging methods and structures for semiconductor devices are disclosed. In one embodiment, a packaged semiconductor device includes a redistribution layer (RDL) having a first surface and a second surface opposite the first surface. At least one integrated circuit is coupled to the first surface of the RDL, and a plurality of metal bumps is coupled to the second surface of the RDL. A molding compound is disposed over the at least one integrated circuit and the first surface of the RDL. | 02-12-2015 |