Patent application number | Description | Published |
20080240168 | PROCESSING WIRELESS AND BROADBAND SIGNALS USING RESOURCE SHARING - Methods and structures are described for processing signals formatted according to a plurality of different wireless and broadband standards. In some embodiments, network resources are shared to enable energy efficient, pseudo-simultaneous processing. In some embodiments, a timestamp is prepended to input data to remove jitter associated with time division multiplexed processing using shared resources. Systems according to embodiments of the invention are also disclosed. | 10-02-2008 |
20110276861 | DEVICE, SYSTEM AND METHOD OF DECODING WIRELESS TRANSMISSIONS - Some demonstrative embodiments include devices, systems and/or methods of turbo decoding. For example, a device may include a turbo decoder to decode a turbo-encoded input according to a turbo code, the turbo-encoded input including a plurality of soft-decision information-bit values and a plurality of soft-decision parity-bit values corresponding to the soft-decision information bit values, wherein the turbo decoder is to output a plurality of extrinsic soft-decision parity-bit values corresponding to the plurality soft-decision parity-bit values. Other embodiments are described and claimed. | 11-10-2011 |
20140071069 | TECHNIQUES FOR TOUCH AND NON-TOUCH USER INTERACTION INPUT - Various embodiments are generally directed a method and apparatus having a touch screen module to receive first input data from a touch screen sensor based on one or more detected touch inputs at a first location of a virtual object displayed on a display. In addition, an ultrasonic module may receive second input data from an ultrasonic sensor based on detected non-touch motion associated with the virtual object. The detected non-touch motion may be tracked from the first location to a second location in a direction away from the first location based on the second input data and used to determine the second location for the virtual object based on the tracking. | 03-13-2014 |
20140089399 | DETERMINING AND COMMUNICATING USER'S EMOTIONAL STATE - According to various aspects of the present disclosure, a system and associated method and functions to determine an emotional state of a user are disclosed. In some embodiments, the disclosed system includes a data acquisition unit, an emotion determination unit, and an emotion reporting unit. The data acquisition unit is configured to detect user information including physiological and non-physiological data associated with the user. The emotion determination unit is operatively connected to the data acquisition unit, and is configured to process the user information to determine an emotional state of the user. The emotion reporting unit is configured to communicate the emotional state based on a predetermined reporting preference to an application of a communication device, e.g., a social-networking application to share the emotional state of the user such that other members of the social network associated with the user are notified of the user's emotional state. | 03-27-2014 |
20140095420 | PERSONAL ADVOCATE - According to various aspects of the present disclosure, a system and associated method and functions to anticipate a need of a user are disclosed. In some embodiments, the disclosed system includes a data acquisition unit, a prediction unit, and an operation unit. The data acquisition unit is configured to detect user information, the user information including physiological and non-physiological data associated with the user. The prediction unit is operatively connected to the data acquisition unit to receive the user information, and is configured to anticipate a user need (e.g., need for medical assistance, need for language translation support, etc.) based on pre-defined user preferences, as well as on the physiological data or the non-physiological data or both. And, the operation unit is configured to automatically perform an operation, without user input, to address the user need (e.g., contact a medical facility, provide a language translation application to the user, etc.). | 04-03-2014 |
20140185655 | METHOD AND APPARATUS FOR CORRECTING A REFERENCE CLOCK OF A GPS RECEIVER - An approach is provided for correcting a reference clock of a GPS receiver. The approach involves determining one or more frequency offset values. The approach also involves determining one or more codes associated with one or more satellites. The approach further involves determining a second code associated with the one or more satellites. The approach additionally involves determining one or more delay values between the second code and the one or more first codes. The approach also involves determining one or more proportional values based on the one or more delay values and a determined correlation. The approach further involves determining one or more correlation peak values and determining one or more estimated frequency offset error values based on the one or more correlation peak values. The approach additionally involves causing a calibrated reference clock frequency value to change to a recalibrated reference clock frequency value based on the estimated frequency offset error values. | 07-03-2014 |
20140218187 | ASSESSMENT AND MANAGEMENT OF EMOTIONAL STATE OF A VEHICLE OPERATOR - Devices, systems, and techniques are provided for assessment and management of an emotional state of a vehicle operator. Assessment of the emotional state of the vehicle can include accessing operational information indicative of performance of a vehicle, behavioral information indicative of behavior of an operator of the vehicle, and or wellness information indicative of a physical condition of the operator of the vehicle. In one aspect, these three types of information can be combined to generate a rich group set of data, metadata, and/or signaling that can be utilized or otherwise leveraged to generate a condition metric representative of the emotional state of the vehicle operator. Management of the emotional state can be customized to the specific context of the vehicle and/or the emotional state, and can be implemented proactively or reactively. | 08-07-2014 |
20150161986 | DEVICE-BASED PERSONAL SPEECH RECOGNITION TRAINING - In embodiments, apparatuses, methods and storage media for personalized speech recognition are described. In various embodiments, a personalized speech recognition system (“PSRS”) may receive personal speech recognition training data (“PTD”) that is associated with a user to facilitate recognition of speech from the user. The PSRS may train a speech recognition module using the received PTD. The user may provide the PTD using a mobile device under control of the user. The PTD may be generated and stored on the mobile device through actions of the user, such as by using the mobile device to record a corpus of speech examples by the user. The user may subsequently facilitate provisioning of the PTD to the PSRS using the mobile device, such as through a wired or wireless network. Other embodiments may be described and claimed. | 06-11-2015 |
Patent application number | Description | Published |
20140344513 | METHODS AND SYSTEMS FOR SMART REFRESH OF DYNAMIC RANDOM ACCESS MEMORY - Methods and devices for refreshing a dynamic memory device, (e.g., DRAM) to eliminate unnecessary page refresh operations. A value in a lookup table for the page may indicate whether valid data including all zeros is present in the page. When the page includes valid data of all zeros, the lookup table value may be set so that refresh, memory read, write and clear accesses of the page may be inhibited and a valid value may be returned. A second lookup table may contain a second value indicating whether a page has been accessed by a page read or write during the page refresh interval. A page refresh, by issuing an ACT−PRE command pair, and a page address may be performed according to the page refresh interval when the second value indicates that page access has not occurred. | 11-20-2014 |
20150046732 | SYSTEM AND METHOD FOR MEMORY CHANNEL INTERLEAVING WITH SELECTIVE POWER OR PERFORMANCE OPTIMIZATION - Systems and methods are disclosed for providing memory channel interleaving with selective power or performance optimization. One such method involves configuring a memory address map for two or more memory devices accessed via two or more respective memory channels with an interleaved region and a linear region. The interleaved region comprises an interleaved address space for relatively higher performance use cases. The linear region comprises a linear address space for relatively lower power use cases. Memory requests are received from one or more clients. The memory requests comprise a preference for power savings or performance. Received memory requests are assigned to the linear region or the interleaved region according to the preference for power savings or performance. | 02-12-2015 |
20150089112 | SYSTEM AND METHOD FOR CONSERVING MEMORY POWER USING DYNAMIC MEMORY I/O RESIZING - Systems and methods are disclosed for conserving power consumption in a memory system. One such system comprises a DRAM memory system and a system on chip (SoC). The SoC is coupled to the DRAM memory system via a memory bus. The SoC comprises one or more memory controllers for processing memory requests from one or more memory clients for accessing the DRAM memory system. The one or more memory controllers are configured to selectively conserve memory power consumption by dynamically resizing a bus width of the memory bus. | 03-26-2015 |
20150121096 | SYSTEM AND METHOD FOR CONSERVING POWER CONSUMPTION IN A MEMORY SYSTEM - Systems and methods are disclosed for conserving power consumption in a memory system. One such system comprises a system on chip (SoC) and an encoder. The SoC comprises one or more memory clients for accessing a dynamic random access memory (DRAM) memory system coupled to the SoC. The encoder resides on the SoC and is configured to reduce a data activity factor of memory data received from the memory clients by encoding the received memory data according to a compression scheme and providing the encoded memory data to the DRAM memory system. The DRAM memory system is configured to decode the encoded memory data according to the compression scheme into the received memory data. | 04-30-2015 |
20150121111 | SYSTEM AND METHOD FOR PROVIDING MULTI-USER POWER SAVING CODEBOOK OPTMIZATION - Systems and methods are disclosed for providing multi-user power saving codebook optimization. One such method comprises: generating a unique codebook for a plurality of computing devices, each unique codebook configured for encoding memory data in the corresponding computing device; providing the unique codebooks to the corresponding computing devices via a communications networks; receiving compression statistics from one or more of the computing devices via the communications network, the compression statistics related to the corresponding unique codebook; and generating an optimized codebook for at least one of the computing devices based on the received compression statistics. | 04-30-2015 |
20150127972 | METHOD AND APPARATUS FOR NON-VOLATILE RAM ERROR RE-MAPPING - A memory module comprising a non-volatile cell array and a re-mapper. A page map table is stored in the non-volatile cell array, and includes mappings of old page addresses to new page addresses. The re-mapper is configured to direct memory operations referencing an old page address to the new page address that the old page address is mapped to. The mappings are created when a memory cell is determined to be in a failure state. | 05-07-2015 |
20150134989 | SYSTEM AND METHOD FOR REDUCING MEMORY I/O POWER VIA DATA MASKING - Systems and methods are disclosed for reducing memory I/O power. One embodiment is a system comprising a system on chip (SoC), a DRAM memory device, and a data masking power reduction module. The SoC comprises a memory controller. The DRAM memory device is coupled to the memory controller via a plurality of DQ pins. The data masking power reduction module comprises logic configured to drive the DQ pins to a power saving state during a data masking operation. | 05-14-2015 |
20150143198 | METHOD AND APPARATUS FOR MULTIPLE-BIT DRAM ERROR RECOVERY - A system for replacing a page stored in system memory when reading the page incurs a multiple-bit error. Upon reading a page in system memory for which a multiple-bit error is detected, backup data in flash memory is loaded into a redundant page in the system memory, and a re-mapper is configured so that future accesses to the page are redirected to the redundant page. | 05-21-2015 |
20150302903 | SYSTEM AND METHOD FOR DEEP COALESCING MEMORY MANAGEMENT IN A PORTABLE COMPUTING DEVICE - Various embodiments of methods and systems for deep coalescing memory management (“DCMM”) in a portable computing device (“PCD”) are disclosed. Because multiple active multimedia (“MM”) clients running on the PCD may generate a random stream of mixed read and write requests associated with data stored at non-contiguous addresses in a double data rate (“DDR”) memory component, DCMM solutions triage the requests into dedicated deep coalescing (“DC”) cache buffers, sequentially ordering the requests and/or the DC buffers based on associated addresses for the data in the DDR, to optimize read and write transactions from and to the DDR memory component in blocks of contiguous data addresses. | 10-22-2015 |
Patent application number | Description | Published |
20120216084 | SERDES POWER THROTTLING AS A FUNCTION OF DETECTED ERROR RATE - A system involves a first SerDes link from a first integrated circuit (IC) to a second IC and a second link from the second IC to the first IC. Power consumption settings in circuitry of the first link are adjusted to control power consumption such that the bit error rate of the first link is maintained in a range, where the lower bound of the range is substantially greater than zero. Power consumption settings in circuitry for the second link are adjusted to control power consumption such that the bit error rate of the second link is maintained in range, where the lower bound of the range is substantially greater than zero. In one example, circuitry in the second IC detects errors in the first link and reports back via the second link. The first IC uses the reported information to determine a bit error rate for the first link. | 08-23-2012 |
20130271920 | HEAT DISSIPATION FEATURES, ELECTRONIC DEVICES INCORPORATING HEAT DISSIPATION FEATURES, AND METHODS OF MAKING HEAT DISSIPATION FEATURES - Electronic devices incorporating a heat dissipation feature include an enclosure, and at least one heat-generating component positioned within the enclosure. The heat dissipation feature is sufficiently coupled to the at least one heat-generating component to facilitate conductive heat transfer from the heat-generating component. The heat dissipation feature includes a plurality of protrusions exposed externally to the enclosure. A thermally insulating material may be disposed on at least a tip portion of at least some of the protrusions. The thermally insulating material is selected to provide a touch temperature that is below a predetermined threshold. In some instances, the thermally insulating material can provide such a touch temperature by selecting the material to include properties for thermal conductivity (k), density (ρ), and specific heat (C | 10-17-2013 |
20130326188 | INTER-CHIP MEMORY INTERFACE STRUCTURE - In an embodiment, a stacked package-on-package system has a memory die and a logic die. The memory die comprises a first memory and a second memory, each operated independently of the other, and each having an inter-chip interface electrically connected to the logic die. The logic die has two independent clock sources, one to provide a first clock signal to the first memory, and the other clock source to provide a second clock signal to the second memory. | 12-05-2013 |
20140098489 | HEAT DISSIPATING APPARATUS FOR FOLDING ELECTRONIC DEVICES - Some implementations provide a folding electronic device that includes a base portion, a cover portion and a coupler. The base portion includes a region configured to generate heat. The cover portion includes a display screen, a heat dissipating component, and a thermally insulating component. The heat dissipating component is coplanar to the display screen. The thermally insulating component is coplanar to the display screen. The thermally insulating component is located between the display screen and the heat dissipating component. The coupler is for thermally coupling the base portion to the cover portion. The coupler includes a first component and a second component. The first component is coupled to the region configured to generate heat. The second component is coupled to the heat dissipating component of the cover portion. The coupler provides a path for transferring heat. | 04-10-2014 |
20140129757 | SYSTEM AND METHOD FOR DYNAMIC MEMORY POWER MANAGEMENT - Various embodiments of methods and systems for hardware (“HW”) based dynamic memory management in a portable computing device (“PCD”) are disclosed. One exemplary method includes generating a lookup table (“LUT”) to track each memory page located across multiple portions of a volatile memory. The records in the LUT are updated to keep track of data locations. When the PCD enters a sleep state to conserve energy, the LUT may be queried to determine which specific memory pages in a first portion of volatile memory (e.g., an upper bank) contain data content and which pages in a second portion of volatile memory (e.g., a lower bank) are available for receipt of content. Based on the query, the location of the data in the memory pages of the upper bank is known and can be quickly migrated to memory pages in the lower bank which are identified for receipt of the data. | 05-08-2014 |
20140164689 | SYSTEM AND METHOD FOR MANAGING PERFORMANCE OF A COMPUTING DEVICE HAVING DISSIMILAR MEMORY TYPES - Systems and methods are provided for managing performance of a computing device having dissimilar memory types. An exemplary embodiment comprises a method for interleaving dissimilar memory devices. The method involves determining an interleave bandwidth ratio comprising a ratio of bandwidths for two or more dissimilar memory devices. The dissimilar memory devices are interleaved according to the interleave bandwidth ratio. Memory address requests are distributed from one or more processing units to the dissimilar memory devices according to the interleave bandwidth ratio. | 06-12-2014 |
20140164690 | SYSTEM AND METHOD FOR ALLOCATING MEMORY TO DISSIMILAR MEMORY DEVICES USING QUALITY OF SERVICE - Systems and methods are provided for allocating memory to dissimilar memory devices. An exemplary embodiment includes a method for allocating memory to dissimilar memory devices. An interleave bandwidth ratio is determined, which comprises a ratio of bandwidths for two or more dissimilar memory devices. The dissimilar memory devices are interleaved according to the interleave bandwidth ratio to define two or more memory zones having different performance levels. Memory address requests are allocated to the memory zones based on a quality of service (QoS). | 06-12-2014 |
20140164720 | SYSTEM AND METHOD FOR DYNAMICALLY ALLOCATING MEMORY IN A MEMORY SUBSYSTEM HAVING ASYMMETRIC MEMORY COMPONENTS - Systems and methods are provided for dynamically allocating a memory subsystem. An exemplary embodiment comprises a method for dynamically allocating a memory subsystem in a portable computing device. The method involves fully interleaving a first portion of a memory subsystem having memory components with asymmetric memory capacities. A second remaining portion of the memory subsystem is partial interleaved according to an interleave bandwidth ratio. The first portion of the memory subsystem is allocated to one or more high-performance memory clients. The second remaining portion is allocated to one or more relatively lower-performance memory clients. | 06-12-2014 |
20140253173 | METHOD AND APPARATUS FOR SELECTIVELY TERMINATING SIGNALS ON A BIDIRECTIONAL BUS BASED ON BUS SPEED - A method of controlling signal termination includes providing first logic for selectively terminating signals received at a first device on a bidirectional data bus, providing second logic for selectively terminating signals received at a second device on the bidirectional data bus, sending first signals from the first device to the second device on the bidirectional data bus at a first speed, stopping the sending of the first signals, after stopping the sending of the first signals, enabling the second logic and shifting a reference voltage of the second device from a first level to a second level, after enabling the second logic at the second device, sending second signals from the first device to the second device on the bidirectional data bus at a higher speed, and controlling the first logic based on a speed of signals received at the first device on the bidirectional data bus. | 09-11-2014 |
20140281328 | MEMORY INTERFACE OFFSET SIGNALING - A memory interface includes circuitry configured for applying a variable delay to a portion of a data signal and applying a variable delay to a data strobe. The delayed data strobe samples the delayed portion of the data signal. Delayed portions of the data signal are spaced away from non-delayed portions of the data signal by alternating the routing of delayed bits and non-delayed bits of the data signal. A training block determines and sets a value of the variable delay corresponding to a largest value of a number of recorded eye aperture widths. | 09-18-2014 |
20140330994 | SYNCHRONOUS DATA-LINK THROUGHPUT ENHANCEMENT TECHNIQUE BASED ON DATA SIGNAL DUTY-CYCLE AND PHASE MODULATION/DEMODULATION - A synchronous data-link throughput enhancement technique based on data signal duty-cycle and phase modulation demodulation is disclosed. A method includes receiving multiple bits to be transmitted, encoding the multiple bits to generate a multi-bit signal that represents the multiple bits, and transmitting, via a synchronous interface, the multi-bit signal during a time period that corresponds to one-half of a cycle of a synchronization signal. | 11-06-2014 |
20140337560 | System and Method for High Performance and Low Cost Flash Translation Layer - Aspects include systems and methods for increasing performance of a flash translation layer (FTL) of a flash memory device. A copy of FTL tables stored on a flash memory device may be copied to a memory of a host device. The copy of the FTL tables may be directly accessed by the flash memory device to translate between logical addresses provided by the host device for read/write operations from/to a flash memory of the flash memory device, and the respective physical addresses of the flash memory. The flash memory device is granted direct memory access to a portion of the memory of the host device where the copy of the FTL tables is stored. The flash memory device bus masters communication busses connecting the flash memory device to the memory of the host device. | 11-13-2014 |
20150039848 | METHODS AND APPARATUSES FOR IN-SYSTEM FIELD REPAIR AND RECOVERY FROM MEMORY FAILURES - In a particular embodiment, a device includes memory address remapping circuitry and a remapping engine. The memory address remapping circuitry includes a comparison circuit to compare a received memory address to one or more remapped addresses. The memory address remapping circuitry also includes a selection circuit responsive to the comparison circuit to output a physical address. The physical address corresponds to a location in a random-access memory (RAM). The remapping engine is configured to update the one or more remapped addresses to include a particular address in response to detecting that a number of occurrences of errors at a particular location satisfies a threshold. | 02-05-2015 |
20150286565 | SYSTEM AND METHOD FOR ALLOCATING MEMORY TO DISSIMILAR MEMORY DEVICES USING QUALITY OF SERVICE - Systems and methods are provided for allocating memory to dissimilar memory devices. An exemplary embodiment includes a method for allocating memory to dissimilar memory devices. An interleave bandwidth ratio is determined, which comprises a ratio of bandwidths for two or more dissimilar memory devices. The dissimilar memory devices are interleaved according to the interleave bandwidth ratio to define two or more memory zones having different performance levels. Memory address requests are allocated to the memory zones based on a quality of service (QoS). | 10-08-2015 |
Patent application number | Description | Published |
20140264836 | SYSTEM-IN-PACKAGE WITH INTERPOSER PITCH ADAPTER - An integrated circuit package is disclosed that includes a first-pitch die and a second-pitch die. The second-pitch die interconnects to the second-pitch substrate through second-pitch substrates. The first-pitch die interconnects through first-pitch interconnects to an interposer adapter. The pitch of the first-pitch interconnects is too fine for the second-pitch substrate. But the interposer adapter interconnects through second-pitch interconnects to the second-pitch substrate and includes through substrate vias so that I/O signaling between the first-pitch die and the second-pitch die can be conducted through the second-pitch substrate and through the through substrate vias in the interposer adapter. | 09-18-2014 |
20150067234 | UNIFIED MEMORY CONTROLLER FOR HETEROGENEOUS MEMORY ON A MULTI-CHIP PACKAGE - An enhanced multi chip package (eMCP) is provided including a unified memory controller. The UMC is configured to manage different types of memory, such as NAND flash memory and DRAM on the eMCP. The UMC provides storage memory management, DRAM management, DRAM accessibility for storage memory management, and storage memory accessibility for DRAM management. The UMC also facilitates direct data copying from DRAM to storage memory and vice versa. The direct copying may be initiated by the UMC without interaction from a host, or may be initiated by a host. | 03-05-2015 |
20150186267 | METHOD AND APPARATUS FOR DRAM SPATIAL COALESCING WITHIN A SINGLE CHANNEL - Aspects include computing devices, systems, and methods for reorganizing the storage of data in memory to energize less than all of the memory devices of a memory module for read or write transactions. The memory devices may be connected to individual select lines such that a re-order logic may determine the memory devices to energize for a transaction according to a re-ordered memory map. The re-order logic may re-order memory addresses such that memory address provided by a processor for a transaction are converted to the re-ordered memory address according to the re-ordered memory map without the processor having to change its memory address scheme. The re-ordered memory map may provide for reduced energy consumption by the memory devices, or a balance of energy consumption and performance speed for latency tolerant processes. | 07-02-2015 |
20150194197 | DYNAMIC RANDOM ACCESS MEMORY (DRAM) BACKCHANNEL COMMUNICATION SYSTEMS AND METHODS - Dynamic random access memory (DRAM) backchannel communication systems and methods are disclosed. In one aspect, a backchannel communication system allows a DRAM to communicate error correction information and refresh alert information to a System on a Chip (SoC), applications processor (AP), or other memory controller. | 07-09-2015 |
20150194959 | METHOD AND APPARATUS FOR SELECTIVELY TERMINATING SIGNALS ON A BIDIRECTIONAL BUS BASED ON BUS SPEED - A method of controlling signal termination includes providing first logic for selectively terminating signals received at a first device on a bidirectional data bus, providing second logic for selectively terminating signals received at a second device on the bidirectional data bus, sending first signals from the first device to the second device on the bidirectional data bus at a first speed, stopping the sending of the first signals, after stopping the sending of the first signals, enabling the second logic and shifting a reference voltage of the second device from a first level to a second level, after enabling the second logic at the second device, sending second signals from the first device to the second device on the bidirectional data bus at a higher speed, and controlling the first logic based on a speed of signals received at the first device on the bidirectional data bus. | 07-09-2015 |
20150213849 | PROVIDING MEMORY TRAINING OF DYNAMIC RANDOM ACCESS MEMORY (DRAM) SYSTEMS USING PORT-TO-PORT LOOPBACKS, AND RELATED METHODS, SYSTEMS, AND APPARATUSES - Providing memory training of dynamic random access memory (DRAM) systems using port-to-port loopbacks, and related methods, systems, and apparatuses are disclosed. In one aspect, a first port within a DRAM system is coupled to a second port via a loopback connection. A training signal is sent to the first port from a System-on-Chip (SoC), and passed to the second port through the loopback connection. The training signal is then returned to the SoC, where it may be examined by a closed-loop training engine of the SoC. A training result corresponding to a hardware parameter may be recorded, and the process may be repeated until an optimal result for the hardware parameter is achieved at the closed-loop training engine. By using a port-to-port loopback configuration, the DRAM system parameters regarding timing, power, and other parameters associated with the DRAM system may be trained more quickly and with lower boot memory usage. | 07-30-2015 |
20150213850 | SERIAL DATA TRANSMISSION FOR DYNAMIC RANDOM ACCESS MEMORY (DRAM) INTERFACES - Serial data transmission for dynamic random access memory (DRAM) interfaces is disclosed. Instead of the parallel data transmission that gives rise to skew concerns, exemplary aspects of the present disclosure transmit the bits of a word serially over a single lane of the bus. Because the bus is a high speed bus, even though the bits come in one after another (i.e., serially), the time between arrival of the first bit and arrival of the last bit of the word is still relatively short. Likewise, because the bits arrive serially, skew between bits becomes irrelevant. The bits are aggregated within a given amount of time and loaded into the memory array. | 07-30-2015 |
20150242213 | SYSTEM AND METHOD FOR MODIFICATION OF CODED INSTRUCTIONS IN READ-ONLY MEMORY USING ONE-TIME PROGRAMMABLE MEMORY - Various embodiments of methods and systems for flexible read only memory (“ROM”) storage of coded instructions in a portable computing device (“PCD”) are disclosed. Because certain instructions and/or data associated with a primary boot loader (“PBL”) may be defective or in need of modification after manufacture of a mask ROM component, embodiments of flexible ROM storage (“FRS”) systems and methods use a closely coupled one-time programmable (“OTP”) memory component to store modified instructions and/or data. Advantageously, because the OTP memory component may be manufactured “blank” and programmed at a later time, modifications to code and/or data stored in an unchangeable mask ROM may be accomplished via pointers in fuses of a security controller that branch the request to the OTP and bypass the mask ROM. | 08-27-2015 |
20150243373 | KERNEL MASKING OF DRAM DEFECTS - Systems, methods, and computer programs are disclosed for kernel masking dynamic random access memory (DRAM) defects. One such method comprises: detecting and correcting a single-bit error associated with a physical address in a dynamic random access memory (DRAM); receiving error data associated with the physical address from the DRAM; storing the received error data in a failed address table located in a non-volatile memory; and retiring a kernel page corresponding to the physical address if a number of errors associated with the physical address exceeds an error count threshold. | 08-27-2015 |
20150261632 | SYSTEMS AND METHODS FOR REDUCING MEMORY FAILURES - Methods and systems for an in-system repair process that repairs or attempts to repair random bit failures in a memory device are provided. In some examples, an in-system repair process may select alternative steps depending on whether the failure is correctable or uncorrectable. In these examples, the process uses communications between a system on chip and the memory to fix the failures during normal operation. | 09-17-2015 |
20150268704 | MULTI-LAYER HEAT DISSIPATING APPARATUS FOR AN ELECTRONIC DEVICE - Some implementations provide a multi-layer heat dissipating device that includes a first heat spreader layer, a first support structure, and a second heat spreader layer. The first heat spreader layer includes a first spreader surface and a second spreader surface. The first support structure includes a first support surface and a second support surface. The first support surface of the first support structure is coupled to the second spreader surface of the first heat spreader. The second heat spreader layer includes a third spreader surface and a fourth spreader surface. The third spreader surface of the second heat spreader layer is coupled to the second support surface of the first support structure. In some implementations, the first support structure is a thermally conductive adhesive layer. In some implementations, the first heat spreader layer has a first thermal conductivity, and the first support structure has a second thermal conductivity. | 09-24-2015 |
20150293822 | SYSTEMS AND METHODS FOR RECOVERING FROM UNCORRECTED DRAM BIT ERRORS - Systems, methods, and computer programs are disclosed for recovering from dynamic random access memory (DRAM) defects. One method comprises determining that an uncorrected bit error has occurred for a physical codeword address associated with a dynamic random access memory (DRAM) device coupled to a system on chip (SoC). A kernel page associated with a DRAM page comprising the physical codeword address is identified as a bad page. Recovery from the uncorrected bit error is provided by rebooting a system comprising the SoC and the DRAM device. In response to the rebooting, the identified kernel page is excluded from being allocated for DRAM operation. | 10-15-2015 |
20150332735 | DYNAMIC CONTROL OF SIGNALING POWER BASED ON AN ERROR RATE - Writing to and reading from dynamic random access memory (DRAM) by a system on chip (SoC) over a multiphase multilane memory bus has power consumption optimized based on bit error rate (BER) and one or more thresholds. The bit error rate (BER) may be measured and used to control parameters to achieve optimal balance between power consumption and accuracy. The bit error rate (BER) measurement, purposely adding jitter, and checking against the thresholds is performed during normal mission-mode operation with live traffic. Error detection may cover every memory data transaction that has a block of binary data. | 11-19-2015 |
20160054928 | SYSTEMS AND METHODS FOR EXPANDING MEMORY FOR A SYSTEM ON CHIP - Systems and methods are disclosed for expanding memory for a system on chip (SoC). A memory card is loaded in an expandable memory socket electrically and is coupled to a system on chip (SoC) via an expansion bus. The memory card comprises a first volatile memory device. In response to detecting the memory card, an expanded virtual memory map is configured. The expanded virtual memory map comprises a first virtual memory space associated the first volatile memory device and a second virtual memory space associated with a second volatile memory device electrically coupled to the SoC via a memory bus. One or more peripheral images associated with the second virtual memory space are relocated to a first portion of the first virtual memory space. A second portion of the first virtual memory space is configured as a block device for performing swap operations associated with the second virtual memory space. | 02-25-2016 |
20160093345 | DYNAMIC RANDOM ACCESS MEMORY TIMING ADJUSTMENTS - A method includes detecting, at a controller, a rate-of-change between first data traffic to be sent to a dynamic random access memory (DRAM) at a first time and second data traffic to be sent to the DRAM at a second time. The method also includes adjusting a data rate of the second data traffic in response to a determination that the rate-of-change satisfies a threshold. | 03-31-2016 |
20160093403 | METHOD AND APPARATUS FOR IN-SYSTEM REPAIR OF MEMORY IN BURST REFRESH - In a repair of a random access memory (RAM), an error information is received, a fail address of the RAM identified, and a one-time programming applied to a portion of the redundancy circuit while a content of the RAM is valid. Optionally, the RAM is a dynamic access RAM (DRAM), a refresh burst is applied to the DRAM, followed by a non-refresh interval, and the one-time programming is performed during the non-refresh interval. | 03-31-2016 |
Patent application number | Description | Published |
20110040299 | Systems, Apparatus, Methods and Procedures for the Noninvasive Treatment of Tissue Using Microwave Energy - The present invention is directed to systems, apparatus, methods and procedures for the noninvasive treatment of tissue, including treatment using microwave energy. In one embodiment of the invention a medical device and associated apparatus and procedures are used to treat dermatological conditions using, for example, microwave energy. | 02-17-2011 |
20110196365 | Systems, Apparatus, Methods, and Procedures for the Non-Invasive Treatment of Tissue Using Microwave Energy - A system applies, in a non-invasive manner, energy to a targeted tissue region employing a controlled source of energy, a multiple use applicator, and a single use, applicator-tissue interface carried by the applicator. The system can generate and apply energy in a controlled fashion to form a predefined pattern of lesions that provide therapeutic benefit, e.g., to moderate or interrupt function of the sweat glands in the underarm (axilla). | 08-11-2011 |
20110313412 | TISSUE INTERFACE SYSTEM AND METHOD - An applicator-tissue interface is disclosed for use in connection with medical device treatment applicators. The interface provides a cover to protect applicator components against contamination and may be disposable or reusable. Also included are tissue acquisition features including a tissue receiving chamber defined by a bio-barrier with vacuum ports or channels for tissue acquisition. Vacuum balancing is provided to prevent contamination on the applicator side of the bio-barrier. Locking mechanisms are disclosed for ensuring secure attachment between the interface and applicator. Methods of using the applicator-tissue interface in connection with an applicator are also disclosed. | 12-22-2011 |
20130035680 | Applicator and Tissue Interface Module for Dermatological Device - An tissue interface module has an applicator chamber on a proximal side of the tissue interface module and a tissue acquisition chamber on a distal side of the tissue interface module. The applicator chamber may include: an opening adapted to receive the applicator; an attachment mechanism positioned in the applicator chamber and adapted to attach the tissue interface module to the applicator; a sealing member positioned at a proximal side of the applicator chamber; and a vacuum interface positioned at a proximal side of the applicator chamber and adapted to receive a vacuum inlet positioned on a distal end of the applicator. The invention also includes corresponding methods. | 02-07-2013 |
20150148792 | SYSTEMS, APPARATUS, METHODS, AND PROCEDURES FOR THE NON-INVASIVE TREATMENT OF TISSUE USING MICROWAVE ENERGY - A system applies, in a non-invasive manner, energy to a targeted tissue region employing a controlled source of energy, a multiple use applicator, and a single use, applicator-tissue interface carried by the applicator. The system can generate and apply energy in a controlled fashion to form a predefined pattern of lesions that provide therapeutic benefit, e.g., to moderate or interrupt function of the sweat glands in the underarm (axilla). | 05-28-2015 |
Patent application number | Description | Published |
20130026683 | LIQUID INKJETTABLE MATERIALS FOR THREE-DIMENSIONAL PRINTING - The present disclosure is drawn toward compositions, systems, and methods for printing of three-dimensional objects. In one embodiment, a liquid inkjettable material for 3-dimensional printing can comprise from 0.1 wt % to 10 wt % of a pigment, from 10 wt % to 90 wt % of a UV-curable polymer, and from 0.1 wt % to 70 wt % of a polymeric filler. Additionally, the liquid inkjettable material can be jettable from piezo electric inkjet printer nozzles and has acceptable decap performance measured by jetting a normal 50 picoliter ink drop within 10 electric firing pulses after the piezo electric inkjet printer nozzles have been fired and have been subsequently rested for 24 hours. | 01-31-2013 |
20130288175 | LIQUID ELECTROPHOTOGRAPHIC INKS - A liquid electrophotographic ink is disclosed. The liquid electrophotographic ink includes a carrier liquid, a polymer resin, and a pearlescent pigment particle. | 10-31-2013 |
20140147783 | LIQUID ELECTROPHOTOGRAPHIC INKS - A liquid electrophotographic ink is disclosed. The liquid electrophotographic ink includes a carrier liquid, a polymer resin, and a pearlescent pigment particle. | 05-29-2014 |
20140342279 | POLYMER-ENCAPSULATED METALLIC INK PARTICLES AND METALLIC ELECTROPHOTOGRAPHIC INKS - A method for making polymer-encapsulated metallic ink particles is disclosed herein. An ethylene-based polymeric resin powder is formed, and is mixed with a metallic pigment powder to form a powder mixture. The powder mixture is melted to form a metallic polymer melt. A non-polar carrier is added to the metallic polymer melt to form a slurry. The slurry is processed in a microfluidizer. | 11-20-2014 |
20150071665 | TECHNIQUES TO DETERMINE CONCENTRATION PARAMETERS OF CONDUCTIVE LIQUID ELECTROPHORETIC (LEP) INKS - Techniques to determine concentration parameters of conductive liquid electrophoretic (LEP) inks are illustrated herein. In an example, a layer of conductive LEP ink is formed on a developer roller using electrostatic forces acting on the conductive LEP ink. A current is generated in response to a voltage between a measurement electrode and a developer roller. The current flows through the conductive LEP ink layer. | 03-12-2015 |
20150111149 | MAKING A LIQUID ELECTROPHOTOGRAPHIC (LEP) PASTE - A method of making a liquid electrophotographic (LEP) paste is disclosed herein. A base paste is made by forming a dispersion of a pigment and a non-polar carrier, adding a transparent resin dispersion to the pigment dispersion to form a dispersion mixture, and homogenizing the dispersion mixture. The transparent resin dispersion includes a polymer dispersed in a non-aqueous carrier. The homogenizing may be accomplished by agitating the dispersion mixture at a frequency of less than 1 kHz, thereby forming the paste. | 04-23-2015 |
Patent application number | Description | Published |
20110105643 | POLYMER-ENCAPSULATED NANOPARTICLES - A polymer-encapsulated nanoparticle is disclosed herein. The polymer-encapsulated colorant nanoparticle includes a colorant nanoparticle core, and a polymer coating permanently established on the colorant nanoparticle core via covalent bonding or physical bonding, the polymer coating including in situ polymerized monomers or prepolymers of a discontinuous phase of an inverse emulsion. The polymer-encapsulated colorant nanoparticle has a size ranging from about 20 nm to about 1000 nm. | 05-05-2011 |
20110184095 | LIGHT FAST ENCAPSULATED PIGMENT - A light fast encapsulated pigment includes an inner core region that includes a pigment and an outer shell that includes a polymer comprising a UV absorber non-covalently incorporated therein. The light fast encapsulated pigment finds use in ink compositions. | 07-28-2011 |
20110184111 | POLYMER-ENCAPSULATED PIGMENT - A polymer-encapsulated pigment and a method of modifying a pigment use functional groups of an interface layer to attach a polymer to a pigment composition. The polymer-encapsulated pigment includes a pigment composition, a polymer and an interface layer. In the polymer-encapsulated pigment and the method, the interface layer is covalently attached to an outer surface of the pigment composition. The polymer is attached to the interface layer with a linking group. The linking group is attached to the interface layer by a covalent bond of a functional group. The linking group includes a nucleophilic carbon atom to which the polymer is covalently attached. | 07-28-2011 |
20120116006 | Polymer Encapsulation Of Particles - Methods of encapsulating particles ( | 05-10-2012 |
20120129092 | ELECTRICALLY CHARGEABLE ENCAPSULATED PARTICLES - Methods of encapsulating particles ( | 05-24-2012 |
20120157608 | SURFACE MODIFICATION OF POLYMER PARTICLES - Methods of surface modification of polymer particle are useful in the development of marking fluids. The surface modification includes saponifying one or more acrylic ester groups on a surface of the polymer particle. | 06-21-2012 |
20120232215 | SINGLE BATCH LATEX INK COMPOSITIONS AND METHODS - The present disclosure provides methods and composition directed to towards a single batch latex ink-jet ink. In one embodiment, a method of manufacturing a single batch latex ink-jet ink can comprise emulsifying a pigment and a monomer in a solvent, and polymerizing the monomer with a reaction condition sufficient to encapsulate the pigment and sufficient to form individual latex particulates thereby forming a single batch latex ink-jet ink. The ink can contain less than about 0.5 wt % of latex particulates having a diameter of 50 nm or less, can contain about 1 wt % to about 10 wt % of latex particulates having a diameter of about 100 nm to about 250 nm and can contain about 3 wt % to about 5 wt % of encapsulated pigment. | 09-13-2012 |
20120252960 | INK COMPOSITION AND METHOD OF PREPARING SAME - An ink composition includes a particulate pigment, a hydrocarbon vehicle, an organic polyamine and an organic polyacid. A ratio by weight percent of the organic polyamine to the organic polyacid in the hydrocarbon vehicle is sufficient to render a conductivity of the ink composition to equal to or less than 15 nanosiemens per centimeter. The ink composition is prepared by combining the particulate pigment with a composition that includes the hydrocarbon vehicle, the organic polyamine and the organic polyacid. The combination is subjected to conditions under which the particulate pigment becomes dispersed in the composition. | 10-04-2012 |
Patent application number | Description | Published |
20110079756 | POLYMER-ENCAPSULATED NANOPARTICLE SYSTEMS - A polymer-encapsulated nanoparticle system includes a non-aqueous medium; and polymer-encapsulated nanoparticles formed in situ in the non-aqueous medium. Each polymer-encapsulated particle has a diameter that is less than 1 micron, and includes a solid particle core, and a polymer coating established directly on the solid particle core. | 04-07-2011 |
20110242241 | INK COMPOSITION CONTAINING NON-VOC LIQUID CARRIER - Ink composition including non-VOC liquid carrier and method of making the same are disclosed. A disclosed example ink composition has a viscosity that is below about 70.0 cps and includes non-VOC liquid carrier, dispersing agents and pigment particles having an average size of less than about 10 μm. Also disclosed are method of use and method of making such ink composition containing non-VOC liquid carrier. | 10-06-2011 |
20110269901 | METHOD OF FORMING IONICALLY-CHARGED, ENCAPSULATED COLORANT NANOPARTICLES - A method of forming ionically-charged, colorant nanoparticles involves forming in-situ ionically-charged polyurethane monomers, and forming an emulsion including the ionically-charged polyurethane monomers and a colorant nanoparticle. The method further involves polymerizing or crosslinking the ionically-charged polyurethane monomers in the emulsion, where the polymerizing or crosslinking chemically attaches the ionically-charged polyurethane monomers to a surface of the colorant nanoparticle to form an ionically-charged encapsulation layer on the surface. | 11-03-2011 |
20120004345 | POLYMER-ENCAPSULATED COLORANT NANOPARTICLES - A polymer-encapsulated colorant nanoparticle includes a colorant nanoparticle core, and a polymer coating established on the colorant nanoparticle core. A negatively chargeable functional group is present on a surface of the polymer-encapsulated colorant nanoparticle. | 01-05-2012 |
20120105554 | INK FORMING METHOD - An ink forming method involves preparing a deagglomerated ink or a modified deagglomerated ink. The deagglomerated ink or the modified deagglomerated ink includes at least deagglomerated colorant particles and a liquid component. The deagglomerated colorant particles are chosen from pigment particles each encapsulated with a dispersant. The colorant particles have a particle size ranging from about 50 nm to about 500 nm. Prior to shipping and/or storing the deagglomerated ink or the modified deagglomerated ink, a portion of the liquid component is removed to form a concentrated ink that has a nonvolatile solids content ranging from about 40 wt % to about 90 wt % of the concentrated ink. | 05-03-2012 |
20120196222 | LIQUID ELECTROPHOTOGRAPHIC INK CONCENTRATES AND METHODS FOR PREPARING THE SAME - Liquid electrophotographic ink concentrates and methods of preparing the same are disclosed herein. An example of the method includes preparing a mixture of ink components using a first predetermined thermal profile. The ink components include a resin, a pigment, and a carrier. The method further includes preparing a microfluidizer with a composition at a temperature within a predetermined range and processing the mixture in the prepared microfluidizer to form the concentrate. Processing the mixture includes pressure-feeding the mixture into the prepared microfluidizer, passing the mixture through the prepared microfluidizer for a predetermined number of times, and utilizing a second predetermined thermal profile while passing the mixture through the prepared microfluidizer. A viscosity modifier is added to the mixture before and/or during the processing of the mixture. | 08-02-2012 |
20120199537 | APPARATUS, METHOD, AND SYSTEM FOR CONDUCTING SINGLE-PASS FILTRATION OF INK WASTE - An apparatus for conducting single-pass filtration of ink waste is disclosed. The apparatus includes: a filter connected to a housing unit and a plurality of absorbent layers within the housing unit, wherein the plurality of absorbent layers are in any order and include: a layer for removing metal and polar compounds, a layer for removing non-polar color impurities, a layer for removing acid functional components, a layer for removing additives with polar or protic functional groups, and a layer for removing residual water. A process and a system that include or utilize the apparatus are also disclosed. | 08-09-2012 |
20130016155 | INK SETAANM Tom; Howard S.AACI San JoseAAST CAAACO USAAGP Tom; Howard S. San Jose CA USAANM Chun; Doris Pik-YiuAACI Santa ClaraAAST CAAACO USAAGP Chun; Doris Pik-Yiu Santa Clara CA USAANM Ganapathiappan; SivapackiaAACI Los AltosAAST CAAACO USAAGP Ganapathiappan; Sivapackia Los Altos CA USAANM Ng; Hou T.AACI CampellAAST CAAACO USAAGP Ng; Hou T. Campell CA US - An ink set includes a first ink and a second ink, where each of the inks has a conductivity that is less than 200 pS/cm. The first ink includes a first pigment of a first color; a carrier fluid; and a concentration of a dispersant. The second ink includes a second pigment of a second color that is different from the first color; the same carrier fluid as the first ink; and substantially the same concentration of the dispersant as the first ink. | 01-17-2013 |
20130095239 | POLYMER-ENCAPSULATED NANOPARTICLE SYSTEMS - A method for forming a system including polymer-encapsulated nanoparticles includes forming an inverse mini-emulsion including a continuous phase of a non-aqueous medium and a discontinuous phase of at least: a plurality of nanoparticles having a polar surface, and at least one of i) a polar, water-soluble, or water-miscible monomer, or ii) a polar, water-soluble, or water-miscible pre-polymer. The method further includes initiating polymerization of the at least one of the monomer or the prepolymer to form a polymer coating on each of the plurality of nanoparticles in the non-aqueous medium. | 04-18-2013 |
20130230340 | LIQUID ELECTROPHOTOGRAPHIC INK CONCENTRATES AND METHODS FOR PREPARING THE SAME - A liquid electrophotographic ink concentrate includes non-volatile solids present in an amount ranging from about 20% to about 70% of the ink concentrate, the non-volatile solids including encapsulated pigment particles having a particle size ranging from about 500 nm to about 20 μm, and a viscosity modifier. The ink concentrate includes a balance of a liquid composition, the liquid composition including a carrier. The concentrate is dispersible in an ink vehicle to form a print-ready liquid electrophotographic ink having the non-volatile solids present in an amount ranging from about 0.5% to 5% of the print-ready liquid electrophotographic ink. | 09-05-2013 |
20130235132 | CONCENTRATED INKJET INK - A concentrated inkjet ink for packaging includes a liquid composition present in an amount that is less than 60 wt % of the concentrated inkjet ink, and nonvolatile solids present in an amount ranging from about 40 wt % to about 90 wt % of the concentrated inkjet ink. The nonvolatile solids include encapsulated pigment particles having a particle size ranging from about 50 nm to about 500 nm, and a dispersant. The concentrated inkjet ink is dispersible in an ink vehicle to form a print ready inkjet ink. | 09-12-2013 |
20130302733 | LIQUID ELECTROPHOTOGRAPHIC INK AND METHOD FOR MAKING THE SAME - A liquid electrophotographic ink is disclosed herein. One example of the liquid electrophotographic ink includes a non-polar carrier liquid; pigmented toner particles; a charge director; and polymer resin encapsulated metal oxide nanoparticles. A method for making the liquid electrophotographic ink is also disclosed herein. | 11-14-2013 |
Patent application number | Description | Published |
20100096725 | Semiconductor Package with Embedded Spiral Inductor - In some embodiments, the semiconductor package includes a substrate having multiple layers, from a first layer to a final layer, a die coupled to the first layer, an electrical connector such as a solder ball coupled to the final layer, and a spiral trace disposed and electrically coupled between the die and the electrical connector. Inductance of the spiral trace is selected such that the package has a predetermined impedance. Material, cross-sectional area, number and density of windings, and total overall length of the spiral trace are selected accordingly. In other embodiments, the semiconductor package includes a substrate with multiple layers; a die coupled to the first of the layers; an electrical connector coupled to the final layer; and a spiral trace, in or on the substrate. The spiral trace is near the die, and electrically coupled between the die and the electrical connector. | 04-22-2010 |
20100142607 | Methods and Systems for Transmitting Data by Modulating Transmitter Filter Coefficients - A signaling system supports main and auxiliary communication channels between integrated circuits in the same direction over a single link. An equalizing transmitter applies appropriate filter coefficients to minimize the impact of intersymbol interference when transmitting the main data over a communication channel. The transmitter modulates at least one of the filter coefficients with the auxiliary data to induce apparent ISI in the transmitted signal. A main receiver ignores the apparent ISI to recover the main data, while an auxiliary receiver detects and demodulates the apparent ISI to recover the auxiliary data. The auxiliary data may be encoded using spread-spectrum techniques to reduce the impact of the auxiliary data on the main data. | 06-10-2010 |
20100281289 | Bidirectional Memory Interface with Glitch Tolerant Bit Slice Circuits - A bit slice circuit having transmit and receive modes of operation is described. The bit slice circuit comprises: first transmit circuitry and first receive circuitry operating in a first clock domain, wherein the first circuitry receives a first clock signal; second transmit circuitry and second receive circuitry operating in a second clock domain, wherein the second circuitry receives a second clock signal; transmit transition circuitry and receive transition circuitry, the transmit transition circuitry coupling the first transmit circuitry to the second transmit circuitry, the receive transition circuitry coupling the first receive circuitry to the second receive circuitry, wherein the transition circuitry receives the first and second clock signals; and a single phase mixer that generates the second clock signal, wherein the second clock signal has a first phase in the transmit mode of operation and second phase in the receive mode of operation. | 11-04-2010 |
20120267756 | Semiconductor Package with Embedded Spiral Inductor - In some embodiments, the semiconductor package includes a substrate having multiple layers, from a first layer to a final layer, a die coupled to the first layer, an electrical connector such as a solder ball coupled to the final layer, and a spiral trace disposed and electrically coupled between the die and the electrical connector. Inductance of the spiral trace is selected such that the package has a predetermined impedance. Material, cross-sectional area, number and density of windings, and total overall length of the spiral trace are selected accordingly. In other embodiments, the semiconductor package includes a substrate with multiple layers; a die coupled to the first of the layers; an electrical connector coupled to the final layer; and a spiral trace, in or on the substrate. The spiral trace is near the die, and electrically coupled between the die and the electrical connector. | 10-25-2012 |
Patent application number | Description | Published |
20080241133 | Novel 25869, 25934, 26335, 50365, 21117, 38692, 46508, 16816, 16839, 49937, 49931 and 49933 molecules and uses therefor - The invention provides isolated nucleic acids molecules, designated 25869, 25934, 26335, 50365, 21117, 38692, 46508, 16816, 16839, 49937, 49931 and 49933 nucleic acid molecules. The invention also provides antisense nucleic acid molecules, recombinant expression vectors containing 25869, 25934, 26335, 50365, 21117, 38692, 46508, 16816, 16839, 49937, 49931 or 49933 nucleic acid molecules, host cells into which the expression vectors have been introduced, and nonhuman transgenic animals in which a 25869, 25934, 26335, 50365, 21117, 38692, 46508, 16816, 16839, 49937, 49931 or 49933 gene has been introduced or disrupted. The invention still further provides isolated 25869, 25934, 26335, 50365, 21117, 38692, 46508, 16816, 16839, 49937, 49931 or 49933 proteins, fusion proteins, antigenic peptides and anti-25869, 25934, 26335, 50365, 21117, 38692, 46508, 16816, 16839, 49937, 49931 or 49933 antibodies. Diagnostic and therapeutic methods utilizing compositions of the invention are also provided. | 10-02-2008 |
20110150860 | NOVEL 25869, 25934, 26335, 50365, 21117, 38692, 46508, 16816, 16839, 49937, 49931 AND 49933 MOLECULES AND USES THEREFOR - The invention provides isolated nucleic acids molecules, designated 25869, 25934, 26335, 50365, 21117, 38692, 46508, 16816, 16839, 49937, 49931 and 49933 nucleic acid molecules. The invention also provides antisense nucleic acid molecules, recombinant expression vectors containing 25869, 25934, 26335, 50365, 21117, 38692, 46508, 16816, 16839, 49937, 49931 or 49933 nucleic acid molecules, host cells into which the expression vectors have been introduced, and nonhuman transgenic animals in which a 25869, 25934, 26335, 50365, 21117, 38692, 46508, 16816, 16839, 49937, 49931 or 49933 gene has been introduced or disrupted. The invention still further provides isolated 25869, 25934, 26335, 50365, 21117, 38692, 46508, 16816, 16839, 49937, 49931 or 49933 proteins, fusion proteins, antigenic peptides and anti-25869, 25934, 26335, 50365, 21117, 38692, 46508, 16816, 16839, 49937, 49931 or 49933 antibodies. Diagnostic and therapeutic methods utilizing compositions of the invention are also provided. | 06-23-2011 |
Patent application number | Description | Published |
20100323508 | PLASMA GRID IMPLANT SYSTEM FOR USE IN SOLAR CELL FABRICATIONS - A method of ion implantation comprising: providing a plasma within a plasma region of a chamber; positively biasing a first grid plate, wherein the first grid plate comprises a plurality of apertures; negatively biasing a second grid plate, wherein the second grid plate comprises a plurality of apertures; flowing ions from the plasma in the plasma region through the apertures in the positively-biased first grid plate; flowing at least a portion of the ions that flowed through the apertures in the positively-biased first grid plate through the apertures in the negatively-biased second grid plate; and implanting a substrate with at least a portion of the ions that flowed through the apertures in the negatively-biased second grid plate. | 12-23-2010 |
20110192993 | ADJUSTABLE SHADOW MASK ASSEMBLY FOR USE IN SOLAR CELL FABRICATIONS - An adjustable shadow mask implantation system comprising: an ion source configured to provide ions; and an shadow mask assembly configured to selectively allow ions from the ion source to pass therethrough to a substrate where they are implanted, wherein the shadow mask assembly is configured to adjust between a first position and a second position, wherein the shadow mask assembly enables ion implantation of multiple substantially parallel lines absent any lines with an intersecting orientation with respect to the multiple substantially parallel lines when set in the first position, and wherein the shadow mask assembly enables ion implantation of multiple substantially parallel lines and a line with an intersecting orientation with respect to the multiple substantially parallel lines when set in the second position. | 08-11-2011 |
20120122273 | DIRECT CURRENT ION IMPLANTATION FOR SOLID PHASE EPITAXIAL REGROWTH IN SOLAR CELL FABRICATION - An apparatus and methods for ion implantation of solar cells. The disclosure provide enhanced throughput and recued or elimination of defects after SPER anneal step. The substrate is continually implanted using continuous high dose-rate implantation, leading to efficient defect accumulation, i.e., amorphization, while suppressing dynamic self-annealing. | 05-17-2012 |
20120125259 | ION IMPLANT SYSTEM HAVING GRID ASSEMBLY - An ion implantation system having a grid assembly. The system includes a plasma source configured to provide plasma in a plasma region; a first grid plate having a plurality of apertures configured to allow ions from the plasma region to pass therethrough, wherein the first grid plate is configured to be biased by a power supply; a second grid plate having a plurality of apertures configured to allow the ions to pass therethrough subsequent to the ions passing through the first grid plate, wherein the second grid plate is configured to be biased by a power supply; and a substrate holder configured to support a substrate in a position where the substrate is implanted with the ions subsequent to the ions passing through the second grid plate. | 05-24-2012 |
20120129325 | METHOD FOR ION IMPLANT USING GRID ASSEMBLY - A method of ion implantation comprising: providing a plasma within a plasma region of a chamber; positively biasing a first grid plate, wherein the first grid plate comprises a plurality of apertures; negatively biasing a second grid plate, wherein the second grid plate comprises a plurality of apertures; flowing ions from the plasma in the plasma region through the apertures in the positively-biased first grid plate; flowing at least a portion of the ions that flowed through the apertures in the positively-biased first grid plate through the apertures in the negatively-biased second grid plate; and implanting a substrate with at least a portion of the ions that flowed through the apertures in the negatively-biased second grid plate. | 05-24-2012 |
20120138230 | SYSTEMS AND METHODS FOR MOVING WEB ETCH, CVD, AND ION IMPLANT - Systems and methods for moving substrates through process chambers for photovoltaic (PV) or solar cell applications are disclosed. In particular, systems and methods for moving substrates through process chambers using a conveyor belt are disclosed. The conveyor belt can be used to move the substrates through etch chambers, chemical vapor deposition (CVD) chambers, and/or ion implant chambers, and the like. | 06-07-2012 |
20130115764 | SUBSTRATE PROCESSING SYSTEM AND METHOD - A system for processing substrates has a vacuum enclosure and a processing chamber situated to process wafers in a processing zone inside the vacuum enclosure. Two rail assemblies are provided, one on each side of the processing zone. Two chuck arrays ride, each on one of the rail assemblies, such that each is cantilevered on one rail assemblies and support a plurality of chucks. The rail assemblies are coupled to an elevation mechanism that places the rails in upper position for processing and at lower position for returning the chuck assemblies for loading new wafers. A pickup head assembly loads wafers from a conveyor onto the chuck assemblies. The pickup head has plurality of electrostatic chucks that pick up the wafers from the front side of the wafers. Cooling channels in the processing chucks are used to create air cushion to assist in aligning the wafers when delivered by the pickup head. | 05-09-2013 |
20150072461 | ION IMPLANT SYSTEM HAVING GRID ASSEMBLY - An ion implantation system having a grid assembly. The system includes a plasma source configured to provide plasma in a plasma region; a first grid plate having a plurality of apertures configured to allow ions from the plasma region to pass therethrough, wherein the first grid plate is configured to be biased by a power supply; a second grid plate having a plurality of apertures configured to allow the ions to pass therethrough subsequent to the ions passing through the first grid plate, wherein the second grid plate is configured to be biased by a power supply; and a substrate holder configured to support a substrate in a position where the substrate is implanted with the ions subsequent to the ions passing through the second grid plate. | 03-12-2015 |
Patent application number | Description | Published |
20080287869 | Safety Syringe - A safety syringe that includes syringe assembly retained within a hollow tubular shell, whereby a retaining member is utilized for retaining the syringe assembly in an operative position such that it is available for administering a shot. After the safety syringe is used, a retracting assembly retracts the syringe assembly into the shell and locks it in place thereby preventing any accidental pricks. | 11-20-2008 |
20090005737 | Auto-Injector - An auto-injector that includes a hollow tubular shell to retain the internal structure and provide a surface to be held by the user; a trigger for activating the auto-injector; a plunger lock for slideably inserting into the trigger and for retaining a plunger in the operative position prior to use; and, a syringe assembly comprising a hollow tubular barrel for slideably receiving the plunger, such that when the trigger is activated the syringe assembly is activated and the injection is automatically administered. | 01-01-2009 |
20100274184 | SYRINGE HAVING EXTENDED BLENDING PATH - An injection device such as a syringe, which has a helical flow path for a solution in which the solvent and solute have been introduced. The helical flow path is formed by a helically configured member which has general overall configuration of a helical coil spring. Individual coils may be formed to have a groove located along the length of the helix. When compressed, the novel member effectively takes on a cylindrical outer configuration. Because the groove is covered and sealed by the surface of the next turn of the helix when compressed, an enclosed helical flow path is formed in the compressed member. The invention may be an injection device using the novel flow path forming member or alternatively, the flow path forming member itself. | 10-28-2010 |
20100274185 | AUTOMATIC INJECTION SYRINGE ASSEMBLY - An apparatus for actuating a syringe. The syringe includes a barrel, a plunger and a needle. A needle shield is near the front of the barrel and is movable from a first position enclosing the needle and a retracted position wherein the needle is exposed. A spring abuts the plunger. A cap has an interior wall for engaging the spring and releasably engages the plunger. The spring is compressed between the plunger and the interior wall when the cap releasably engages the plunger. A resilient member releasably secures the cap in releasable engagement with the plunger and is movable from a first position to a compressed position when the needle shield is moved from its first position to its retracted position. The cap disengages the plunger when the resilient member is moved to the compressed position wherein the spring expands to provide a medicament delivery pressure to the plunger. | 10-28-2010 |
20100324480 | AUTOMATIC INJECTION SYRINGE ASSEMBLY - An apparatus for applying medicament delivery pressure to a plunger pad of a plunger of a syringe includes a spring having a first end and a second end, wherein the spring first end is operable to abut the plunger pad. The assembly also includes a shell including an interior and a first step therein. A cap is disposed within the shell interior. The cap includes a surface for engaging the spring second end. The cap is movable from a first position, wherein the shell first step retains the cap in releasable engagement with the plunger such that the spring is compressed between the cap surface and plunger pad, and a second position, wherein the cap disengages the shell first step such that the cap disengages the plunger such that the spring expands to move the barrel and needle forward as well as deliver medicament delivery pressure to the plunger pad. | 12-23-2010 |
20110319832 | PROTECTIVE GUARD FOR NEEDLES OF INJECTION DEVICES HAVING REMOVABLE NEEDLE ASSEMBLIES - Protection for the otherwise exposed sharp point of a needle of an injection device. A two part cover for the needle comprises a stationary base which engages the injection device, and a relatively movable cover. The cover is guided to slide longitudinally along the base by a groove-and-projection system. The projection is held in an initial position, and slides along the groove during injection. At the end of the injection, the projection is immobilized in the groove at a final position, and immobilizes the moveable cover in a deployed position covering the needle. | 12-29-2011 |
20110319833 | PROTECTIVE GUARD FOR NEEDLES OF INJECTION DEVICES - A self-deploying cover for protection against unintended pricks from injection devices. The cover comprises a base which engages the injection device, and a protective sleeve which covers the sharp point and moves relative to the base to expose and cover the sharp point. The sleeve is guided by a projection which rides within a generally V-shaped groove formed in the base. The groove comprises deflectable arms which deflect to pass the projection, but which oppose return of the projection after passing. The sleeve is spring urged to the extended position and is automatically withdrawn during injections. After an injection, the sleeve is locked into the extended position by the last deflectable arm. | 12-29-2011 |
20120123349 | SYRINGE SHARP TIP GUARD - A guard for the sharp tip of a needle of an injection syringe. The guard may comprise two components which are separate from and readily attachable to the syringe. One component is stationary and the other movable relative to the syringe. The movable member moves by expanding longitudinally to cover the otherwise exposed needle tip when the plunger of the syringe is depressed beyond a predetermined degree. The stationary member releasably holds the movable member in the initial position, and releases the movable member to expand and thus deploy when the predetermined degree of depression is imposed by the user of the syringe. | 05-17-2012 |
20140296792 | SHARPS GUARD - An arrangement for covering the sharp point of a needle of a syringe or similar needle device. The arrangement includes a hollow cover which exposes the needle in a retracted position and covers the needle in the deployed condition. A resilient multi-section link anchored to the syringe may propel the hollow cover to the deployed position when the link or the needle device is pressed against an environmental surface. The arrangement may be integral with the needle device or may be formed as a separate component which is attachable to the needle device. An optional cap may cover the needle when the hollow cover is in the retracted position. | 10-02-2014 |