Chuang, Hsinchu City
Bing-Juo Chuang, Hsinchu City TW
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20150116594 | Pixel clock generation circuit and method thereof - This invention discloses circuits and methods for generating a pixel clock. The circuits utilize an image signal of a first format to generate a pixel clock, which can be utilized to generate an image signal of a second format. The circuits include a reference clock generation circuit, an image processing circuit, and a clock adjustment circuit. The reference clock generation circuit generates a reference clock. The image processing circuit processes the image signal of the first format to generate a control signal. The clock adjustment circuit, which is coupled to the reference clock generation circuit and the image signal processing circuit, generates the pixel clock according to the reference clock and the control signal. The control signal is substantially a periodic signal, whose frequency is proportional to the frequency of a synchronization signal of the image signal of the second format. | 04-30-2015 |
Chao Kai Chuang, Hsinchu City TW
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20140133253 | System and Method for Memory Testing - An embodiment method of testing a memory includes writing a first logic state to a first cell in a first clock cycle and reading the first logic state in the first cell in a second clock cycle in a first phase, and reading the first logic state in the first cell and writing a second logic state to the first cell in the first clock cycle and reading the second logic state in the first cell in the second clock cycle in a second phase. As such, a concurrent read/write operation is performed at the same time and for the same memory bit (i.e., the first cell). | 05-15-2014 |
Che-Hao Chuang, Hsinchu City TW
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20080232013 | High-Voltage Tolerant Power-Rail ESD Clamp Circuit for Mixed-Voltage I/O Interface - A circuit for electrostatic discharge (ESD) protection includes a resistor a capacitor connected in series with the resistor, a first transistor including a gate, the gate being connected to a first power supply providing a first voltage to the gate via the resistor and a first terminal connected to the first power supply, a second transistor including a gate, the gate being connected to a second power supply, the second power supply providing a second voltage smaller than the first voltage, the second transistor having a first terminal connected to a second terminal of the first transistor, and a third transistor including a gate, the gate being connected to the second power supply, a first terminal of the third transistor being connected to a second terminal of the second transistor, and a second terminal being connected to a reference voltage different from the first voltage and the second voltage. | 09-25-2008 |
20090032837 | ASYMMETRIC BIDIRECTIONAL SILICON-CONTROLLED RECTIFIER - The present invention discloses an asymmetric bidirectional silicon-controlled rectifier, which comprises: a second conduction type substrate; a first conduction type undoped epitaxial layer formed on the substrate; a first well and a second well both formed inside the undoped epitaxial layer and separated by a portion of the undoped epitaxial layer; a first buried layer formed in a junction between the first well and the substrate; a second buried layer formed in a junction between the second well and the substrate; a first and a second semiconductor area with opposite conduction type both formed inside the first well; a third and a fourth semiconductor area with opposite conduction type both formed inside the second well, wherein the first and second semiconductor areas are connected to the anode of the silicon-controlled rectifier, and the third and fourth semiconductor areas are connected to the cathode of the silicon-controlled rectifier. | 02-05-2009 |
20090032838 | SYMMETRIC BIDIRECTIONAL SILICON-CONTROLLED RECTIFIER - The present invention discloses a symmetric bidirectional silicon-controlled rectifier, which comprises: a substrate; a buried layer formed on the substrate; a first well, a middle region and a second well, which are sequentially formed on the buried layer side-by-side; a first semiconductor area and a second semiconductor area both formed inside the first well; a third semiconductor area formed in a junction between the first well and the middle region, wherein a first gate is formed over a region between the second and third semiconductor areas; a fourth semiconductor area and a fifth semiconductor area both formed inside the second well; a sixth semiconductor area formed in a junction between the second well and the middle region, wherein a second gate is formed over a region between the fifth and sixth semiconductor areas. | 02-05-2009 |
20090179679 | SLEW-RATE CONTROL CIRCUITRY WITH OUTPUT BUFFER AND FEEDBACK - The present invention proposed a slew-rate control circuitry without the use of external components such as amplifiers. Therefore slew-rate control circuitry of the present invention not only provides an IC with build-in slew-rate control, but also reduces number of transistors used externally which will increase gate-oxide reliability of the IC. The slew-rate control circuitry of the present invention is primarily comprised by an output buffer and feedback circuitry, the output buffer mainly consisted four transistors and depends on output of the IC, these four transistors will interact with each other to control the slew-rate of IC output. Additional feedback circuitry and gate-tracking circuitry are also disclosed to enhance the performance of the slew-rate control circuitry. | 07-16-2009 |
20120012973 | LATERAL TRANSIENT VOLTAGE SUPPRESSOR WITH ULTRA LOW CAPACITANCE - A lateral transient voltage suppressor with ultra low capacitance is disclosed. The suppressor comprises a first type substrate and at least one diode cascade structure arranged in the first type substrate. The cascade structure further comprises at least one second type lightly doped well and at least one first type lightly doped well, wherein there are two heavily doped areas arranged in the second type lightly doped well and the first type lightly doped well. The cascade structure neighbors a second type well, wherein there are three heavily doped areas arranged in the second type well. The suppressor further comprises a plurality of deep isolation trenches arranged in the first type substrate and having a depth greater than depths of the second type lightly doped well, the second type well and the first type lightly doped well. Each doped well is isolated by trenches. | 01-19-2012 |
20120012974 | LATERAL TRANSIENT VOLTAGE SUPPRESSOR FOR LOW-VOLTAGE APPLICATIONS - A lateral transient voltage suppressor for low-voltage applications is disclosed. The suppressor comprises an N-type heavily doped substrate and at least two clamp diode structures horizontally arranged in the N-type heavily doped substrate. Each clamp diode structure further comprises a clamp well arranged in the N-type heavily doped substrate and having a first heavily doped area and a second heavily doped area. The first and second heavily doped areas respectively belong to opposite types. There is a plurality of deep isolation trenches arranged in the N-type heavily doped substrate and having a depth greater than depth of the clamp well. The deep isolation trenches can separate each clamp well. The present invention avoids the huge leakage current to be suitable for low-voltage application. | 01-19-2012 |
20120014027 | TRANSIENT VOLTAGE SUPPRESSOR FOR MULTIPLE PIN ASSIGNMENTS - A transient voltage suppressor (TVS) for multiple pin assignments is disclosed. The suppressor comprises at least two cascade-diode circuits in parallel to each other and an electrostatic-discharge clamp element in parallel to each cascade-diode circuit and connected with a low voltage. One cascade-diode circuit is connected with a high voltage, and the other cascade-diode circuits are respectively connected with I/O pins. Each cascade-diode circuit further comprises a first diode and a second diode cascaded to the first diode, wherein a node between the first diode and the second diode is connected with the high voltage or the one I/O pin. The design of the present invention can meet several bounding requirements. It is flexible different pin assignments of TVS parts. | 01-19-2012 |
20120025350 | VERTICAL TRANSIENT VOLTAGE SUPPRESSORS - A vertical transient voltage suppressor for protecting an electronic device is disclosed. The vertical transient voltage includes a conductivity type substrate having highly doping concentration; a first type lightly doped region is arranged on the conductivity type substrate, wherein the conductivity type substrate and the first type lightly doped region respectively belong to opposite types; a first type heavily doped region and a second type heavily doped region are arranged in the first type lightly doped region, wherein the first and second type heavily doped regions and the conductivity type substrate belong to same types; and a deep first type heavily doped region is arranged on the conductivity type substrate and neighbors the first type lightly doped region, wherein the deep first type heavily doped region and the first type lightly doped region respectively belong to opposite types, and wherein the deep first type heavily doped region is coupled to the first type heavily doped region. | 02-02-2012 |
20120068299 | TRANSIENT VOLTAGE SUPPRESSORS - The present invention relates a transient voltage suppressor (TVS) for directional ESD protection. The TVS includes: a conductivity type substrate; a first type lightly doped region, having a first type heavily doped region arranged therein; a second type lightly doped region, having a second type heavily doped region and a third type heavily doped region arranged therein; a third type lightly doped region, having a fourth type heavily doped region arranged therein; a plurality of closed isolation trenches, arranged on the conductivity type substrate, wherein at least one of the plurality of closed isolation trenches is neighbored one of the type lightly doped regions; and a first pin. Accordingly, the TVS of present invention may adaptively provide effective ESD protection under positive and negative ESD stresses, improve the efficiency of ESD protection within the limited layout area. | 03-22-2012 |
20120241903 | LOW CAPACITANCE TRANSIENT VOLTAGE SUPPRESSOR - A low capacitance transient voltage suppressor is disclosed. The suppressor comprises an N-type heavily doped substrate and an epitaxial layer formed on the substrate. At least one steering diode structure formed in the epitaxial layer comprises a diode lightly doped well and a first P-type lightly doped well, wherein a P-type heavily doped area is formed in the diode lightly doped well and a first N-type heavily doped area and a second P-type heavily doped area are formed in the first P-type lightly doped well. A second P-type lightly doped well having two N-type heavily doped areas is formed in the epitaxial layer. In addition, an N-type heavily doped well and at least one deep isolation trench are formed in the epitaxial layer, wherein the trench has a depth greater than or equal to depths of all the doped wells, so as to separate at least one doped well. | 09-27-2012 |
20130003242 | TRANSIENT VOLTAGE SUPPRESSOR FOR MULTIPLE PIN ASSIGNMENTS - A transient voltage suppressor (TVS) for multiple pin assignments is disclosed. The suppressor comprises at least two cascade-diode circuits in parallel to each other and an electrostatic-discharge clamp element in parallel to each cascade-diode circuit and connected with a low voltage. | 01-03-2013 |
Che Lun Chuang, Hsinchu City TW
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20090161951 | METHOD FOR CORRECTING RED-EYE - A method for correcting red-eye is described. Through facial features, at least one facial region is obtained in an image, a nose position in each facial region is obtained by using a nose feature, and at least one eye position is obtained based on a relative position relation between the nose and the eyes. After a color gamut of the image is converted, a red region is obtained from the eye position, and a plurality of edges is formed by using a luminance of the color gamut on the image with the converted color gamut according to the eye feature, so as to exclude the red region out of the plurality of edges, thereby improving accuracy of the red region on the eye position. Then, the red region is covered by an iris color, so as to correct the red-eye. | 06-25-2009 |
20100208990 | COMPENSATION METHOD FOR ALLEVIATING COLOR SHADING IN DIGITAL IMAGE - A compensation method for alleviating color shading in a digital image is adapted to correct a color shading phenomenon in a digital image that causes luminance differences between regions in the digital image. The compensation method includes capturing a uniform color block image; calculating horizontal compensation coefficients of a plurality of horizontal segments of the color block image; performing a linear interpolation process on the horizontal compensation coefficients to generate corresponding horizontal interpolation coefficients, and calculating determination horizontal correction coefficients corresponding to all the horizontal segments, respectively; calculating vertical compensation coefficients of a plurality of vertical segments; multiplying the determination horizontal correction coefficients by the vertical compensation coefficients, respectively, so as to obtain a color shading compensation coefficient of each segment, respectively; and multiplying an average luminance value of each segment by a corresponding color shading compensation coefficient, respectively, thus compensating for color shading in the color block image. | 08-19-2010 |
20110158514 | METHOD FOR REMOVING COLOR FRINGE IN DIGITAL IMAGE - A method for removing color fringe is presented. Separated luminance and chrominance (YCbCr) signals of a digital image are analyzed through specific color detection, luminance detection, and gradient color detection, so as to determine whether color fringe occurs to each pixel in the digital image, thereby correcting pixels with color fringe. | 06-30-2011 |
20110158515 | METHOD FOR REMOVING COLOR FRINGE IN DIGITAL IMAGE - A method for removing color fringe is presented. First, detection and correction of color fringe are performed on an original-size image and a small-size image respectively, so as to generate respective corrected images and corresponding color fringe maps. Then, the corrected small-size image and its corresponding color fringe map are enlarged to the same resolution as the original-size image. Finally, the two corrected images are blended according to the respective corresponding color fringe maps. | 06-30-2011 |
20120281120 | IMAGE PROCESSING METHOD AND IMAGE PROCESSING APPARATUS - An image processing method and an image processing apparatus are provided. In the image processing method, each of a plurality of original images is divided into K bands, where K is a positive integer greater than or equal to 1. A plurality of local motions of each band in any two adjacent of the original images are calculated, and a global motion of each band is calculated according to the local motions of the band. A horizontal component velocity and a vertical component velocity of each band are generated according to the global motion and a capturing time difference. A plurality of transformation matrixes corresponding to the bands are generated according to the horizontal component velocities, the vertical component velocities, a row readout time, and the width of a valid area. One of the two adjacent original images is transformed according to the transformation matrixes to generate a compensated image. | 11-08-2012 |
20120287311 | DIGITAL IMAGE PROCESSING DEVICE AND PROCESSING METHOD THEREOF - A digital image processing device and processing method thereof are provided. The device includes a digital image capturing module, an image enlarging module, an image correcting module, and an image blending module. The digital image capturing module captures a plurality of first resolution images. The image enlarging module enlarges the first resolution images and produces a plurality of second resolution images. The image correcting module selects a target image and produces a plurality of corrected images. The image blending module performs direction gradient operation on each of the pixels of the target and corrected images and produces a plurality of gradient differential values. The image blending module performs a weighting sum operation on each of the pixels of the target and corrected images and produces a third resolution images. | 11-15-2012 |
20120288215 | IMAGE PROCESSING DEVICE AND PROCESSING METHOD THEREOF - An image processing device and the processing method thereof are provided. The device includes an image correcting module, an object-motion detection module and an image blending module. The image correcting module estimates a plurality of local motions of the non-selected images relative to the target image and a plurality of global motions, and performs a plurality of motion corrections to generate a plurality of corrected images. The object-motion detection module judges whether or not the difference between each of the local motions and the corresponding global motion is greater than a threshold value to generate a plurality of object-motion indicators. The image blending module performs an arithmetic operation on each pixel of the target image and each pixel of the corrected images according to the object-motion indicators so as to generate a super-resolution image. | 11-15-2012 |
20130176466 | Image Capturing Device Capable of Reducing Smear Effect and Method for Reducing Smear Effect - A device and a method for reducing a smear effect. The device comprises an image sensing module and a smear reduction module. The image sensing module captures an image and optical black data generated from the optical area of the image sensing module. The smear reduction module searches the optical black data generated in the lower boundary of the optical black area corresponding to which generated in the upper boundary of the optical black area according to coordinates of the optical black data. Thereby, the smear reduction module can compute an offset line representing an offset of the optical black data, and the smear reduction module compensates the smear effect occurring in the image. | 07-11-2013 |
20130279826 | IMAGE PROCESSING DEVICE AND PROCESSING METHOD THEREOF - The invention is directed to an image processing device and a processing method thereof. The image processing device comprises an image calibration module estimating multiple local motions and global motions of unselected images relative to a target image and performing multiple motions calibrations so as to generate multiple calibrated images, a moving-object detection module determining if a difference value between each of the local motions and the corresponding global motions is greater than a threshold value and if a pixel difference value between each pixel point of the target image and each pixel point of the calibrated images is greater than a predetermined difference value so as to generate multiple object motion pointers, and an image blending module performing a calculation on each pixel point of the target and calibrated images based on the object motion pointers so as to generate a super-resolution image. | 10-24-2013 |
20140218550 | IMAGE CAPTURING DEVICE AND IMAGE PROCESSING METHOD THEREOF - An image capturing device and an image processing method are provided. The present method includes following steps. A first image and a second image are captured with a first focal length and a second focal length correspondingly. The motion corrected second image is produced by performing geometric correction procedure on the second image. A gradient operation is performed on each of the pixels of the first image to obtain a plurality of first gradients, and the gradient operation is performed on each of the pixels of the motion corrected second image to obtain a plurality of second gradients. The first gradients and the second gradients are compared and a first parameter map is generated according to the comparison results. A blending image is produced in according with the first parameter map and the first image, and an output image is produced at least in according with the blending image. | 08-07-2014 |
20150103213 | Method for Reducing Smear Effect in Image Capturing Device - A device and a method for reducing a smear effect. The device comprises an image sensing module and a smear reduction module. The image sensing module captures an image and optical black data generated from the optical area of the image sensing module. The smear reduction module searches the optical black data generated in the lower boundary of the optical black area corresponding to which generated in the upper boundary of the optical black area according to coordinates of the optical black data. Thereby, the smear reduction module can compute an offset line representing an offset of the optical black data, and the smear reduction module compensates the smear effect occurring in the image. | 04-16-2015 |
20150213588 | IMAGE CAPTURING DEVICE AND METHOD FOR DETECTING IMAGE DEFORMATION THEREOF - An image capturing device and a method for detecting image deformation thereof are provided. The method is for the image capturing device having a first sensor and a second image sensor, and the method includes the following steps. A first image is captured through the first image sensor, and a second image is captured through the second image sensor. A deform detection is performed according to the first and second images so as to obtain a comparison information between the first and second images. Whether a coordinate parameter relationship between the first and second images being varied is determined according to the comparison information, in which the coordinate parameter relationship is associated with a spatial configuration relationship between the first and second image sensors. | 07-30-2015 |
20150213589 | IMAGE CAPTURING DEVICE AND METHOD FOR CALIBRATING IMAGE DEFORMATION THEREOF - An image capturing device and a method for calibrating image deformation thereof are provided. The image capturing device has a first image sensor and a second image sensor and the method includes following steps. A plurality of image groups are captured through the first image sensor and the second image sensor. Each of the image groups includes a first image and a second image, and the image groups include a reference image group. Whether an image deformation occurs on a first reference image and a second reference image in the reference image group is detected. If it is detected that the image deformation occurs on the reference image group, a current calibration parameter is updated according to a plurality of feature point comparison values corresponding to the image groups. The current calibration parameter is used for performing an image rectification on each of the first images and the second images. | 07-30-2015 |
20160080654 | METHOD OF CAPTURING IMAGES AND IMAGE CAPTURING DEVICE USING THE METHOD - The present invention discloses a method of capturing images and an image capturing device using the method. The image capturing device has a first lens module and a second lens module having a view angle which is smaller than that of the first lens module. The method comprises: increasing an exposure time and reducing a light sensitivity value of the first lens module and capturing a first image by using the first lens module; reducing the exposure time and increasing the light sensitivity value of the first lens module and capturing a second image by using the second lens module; extracting a plurality of image features from the first image and the second image respectively and determining a region corresponding to the second image in the first image; and merging the second image into the region in the first image to generate an output image. | 03-17-2016 |
20160080657 | IMAGE CAPTURING DEVICE AND DIGITAL ZOOM METHOD - The present invention discloses an image capturing device and a digital zoom method. The image capturing device comprises a first lens module, a second lens module, a feature extraction unit, an image zooming-deformation unit and an image merging unit. The first lens module and the second lens module are applied to capture a first image and a second image, respectively. The feature extraction unit extracts a plurality of first image features and second image features from the first image and the second image, respectively, and generating pixel offset characteristics. Based on a zoom factor and the pixel offset characteristics, the image zooming-deformation unit zooms and deforms the first and second images to generate a third image and a fourth image. The image merging unit bases the zoom factor to merge the third image and the fourth image for obtaining a combined image. | 03-17-2016 |
20160105615 | IMAGE PROCESSING SYSTEM AND METHOD FOR OBJECT-TRACING - An image processing system and a method for object-tracing are provided. The method includes: receiving a first wide field of view image and a first narrow field of view image, and determining a to-be-traced object therefrom and choosing one image therefrom for serving as a first output image; using an area size of the to-be-traced object in the first output image as a reference area; comparing the reference area with the area sizes of the to-be-traced object from a second wide field of view image and a second narrow field of view image respectively so as to determine one of that as a main image, and respectively zooming and deforming the main image and an area corresponding to the other image, and then fusing a zoomed and deformed second image as a second output image. | 04-14-2016 |
Cheng Te Chuang, Hsinchu City TW
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20110157421 | Systems and Methods for Capturing Images of Objects - A method for generating an image object, performed by a mobile electronic device, comprises the following steps. The mobile electronic device comprises multiple shutter objects, and each shutter object corresponds to an orientation type. A signal generated by one of the shutter objects is detected. A orientation type is determined according to the shutter object generating the signal. The image object with the determined orientation type is stored. | 06-30-2011 |
Chen-Jung Chuang, Hsinchu City TW
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20100271294 | Method for Reducing Resonance Energy of an LCD panel and Related LCD Device - A method for reducing resonance energy of an LCD panel includes providing a plurality of driving signal patterns, each defining a non-overlap area width of a synchronization signal and a scan-line charging frequency, and determining an order of the plurality of driving signal patterns to modulate driving signals of the LCD panel accordingly. | 10-28-2010 |
20110001534 | Voltage Generator Capable of Preventing Latch-up and Method Thereof - A voltage generator capable of preventing latch-up is disclosed. The voltage generator includes a positive charge pump unit, a negative charge pump unit, a second stage charge pump unit, and a control unit. The positive charge pump unit is utilized for generating a positive charge pump voltage according to a first enable signal. The negative charge pump is utilized for generating a negative charge pump voltage according to a second enable signal. The second stage charge pump unit is utilized for generating a gate-on voltage and a gate-off voltage according to a third enable signal and a fourth enable signal. The control unit is utilized for generating the first enable signal, the second enable signal, the third enable signal, and the fourth enable signal and make the second stage charge pump unit generate the gate-on voltage (or the gate-off voltage) in a successively-increasing (or decreasing) manner. | 01-06-2011 |
20110012671 | Charge Pump Circuit - A charge pump circuit includes an input end, a first reservoir capacitor, a second reservoir capacitor, a first output end, a second output end, and a charge pump unit. The input end is utilized for receiving an input voltage. The charge pump unit includes a first flying capacitor, a second capacitor, a plurality of switches, and a control unit. The control unit is utilized for controlling on/off state of the plurality of switches so that the first flying capacitor provides a positive charge pump voltage to the first output end or a negative charge pump voltage to the second output and the second flying capacitor provides a positive charge pump voltage to the first output end through charge and discharge process. | 01-20-2011 |
Chia-Lin Chuang, Hsinchu City TW
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20090051040 | POWER LAYOUT OF INTEGRATED CIRCUITS AND DESIGNING METHOD THEREOF - The invention discloses a technique for designing the power layout of an integrated circuit. The power layout design forms a power mesh and a power ring with a plurality of metal trunks with uniform line width. In particular, the power ring includes a plurality of metal rings, which are formed by arranging denser layout of the metal trunks with uniform line width. The power ring serves as a function of receiving and providing a power source to the elements of the integrated circuit. | 02-26-2009 |
20090132988 | POWER MESH ARRANGEMENT METHOD UTILIZED IN AN INTEGRATED CIRCUIT HAVING MULTIPLE POWER DOMAINS - The invention discloses a power mesh arrangement method utilized in an integrated circuit having multiple power domains. The arrangement method includes: forming a first partial local power mesh according to a position of a first power domain; forming a second partial local power mesh according to a position of a second power domain; forming a global power mesh, utilized for providing powers needed by the first and the second power domains; coupling the first partial local power mesh to the global power mesh and the first power domain; and coupling the second partial local power mesh to the global power mesh and the second power domain. | 05-21-2009 |
20090193271 | POWER MESH MANAGEMENT METHOD - The invention discloses a power mesh managing method utilized in an integrated circuit. The integrated circuit includes a standard cell and a standard-cell power supplying mesh corresponding to a first direction. The power mesh managing method includes: defining a power supplying network including a first plurality of power meshes growing along the first direction and a second plurality of power meshes growing along a second direction, and defining an assistant connecting network on a third metal layer, wherein the assistant connecting network includes a plurality of assistant connecting lines growing along the second direction, the first plurality of power meshes are formed on a first metal layer, the second plurality of power meshes on a second metal layer, the third metal layer is below the first metal layer, and the second metal layer is above the first metal layer. | 07-30-2009 |
20090193381 | POWER MESH MANAGEMENT METHOD - The invention discloses a power mesh management method utilized in an integrated IC. The integrated circuit includes a macro block including at least a macro block power supplying line growing along a first direction. The management method includes: defining a plurality of first power supplying lines located in a metal layer above the macro block, wherein each of the first supplying lines grows along the first direction; defining a plurality of second power supplying lines located in another metal layer above the macro block, wherein each of the second supplying lines grows along a second direction; defining a partial power supplying line from the plurality of first power supplying lines where the partial power supplying line overlaps the macro block power supplying line; and removing the partial power supplying line from the plurality of first power supplying lines. | 07-30-2009 |
20120242149 | METHOD FOR DESIGNING POWER DISTRIBUTION NETWORK OF CIRCUIT SYSTEM AND RELATED CIRCUIT SYSTEM - A method for designing a power distribution network of a circuit system includes the following steps: determining positions of a plurality of power source nodes; estimating a current distribution condition of the circuit system; and creating a first part of the power distribution network according to at least the positions of the power source nodes | 09-27-2012 |
20120304144 | Power Mesh Managing Method - The invention discloses a power mesh managing method utilized in an integrated circuit. The integrated circuit includes a standard cell and a standard-cell power supplying mesh corresponding to a first direction. The power mesh managing method includes: defining a power supplying network including a first plurality of power meshes growing along the first direction and a second plurality of power meshes growing along a second direction, and defining an assistant connecting network on a third metal layer, wherein the assistant connecting network includes a plurality of assistant connecting lines growing along the second direction, the first plurality of power meshes are formed on a first metal layer, the second plurality of power meshes on a second metal layer, the third metal layer is below the first metal layer, and the second metal layer is above the first metal layer. | 11-29-2012 |
20130037934 | INTEGRATED CIRCUIT CHIP WITH REDUCED IR DROP - An integrated circuit chip includes a power/ground interconnection network in a topmost metal layer over a semiconductor substrate and at least a bump pad on/over the power/ground interconnection network. The power/ground mesh interconnection network includes a first power/ground line connected to the bump pad and extending along a first direction, and a connection portion connected to the bump pad and extending along a second direction. | 02-14-2013 |
20140210079 | METHOD FOR DESIGNING POWER DISTRIBUTION NETWORK OF CIRCUIT SYSTEM AND RELATED CIRCUIT SYSTEM - A method for designing a power distribution network of a circuit system includes the following steps: determining positions of a plurality of power source nodes; estimating a current distribution condition of the circuit system; and creating a first part of the power distribution network according to at least the positions of the power source nodes. | 07-31-2014 |
Chia-Ming Chuang, Hsinchu City TW
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20100200885 | LIGHT-EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - A light emitting device and a method of fabricating thereof are provided. The method of fabricating the light emitting device comprises: providing a substrate having a first major surface and a second major surface; forming a plurality of light-emitting stacks on the first major surface; forming an etching protection layer on each of the light emitting stacks; forming a plurality of holes by a discontinuous laser beam on the substrate; etching the plurality of holes; and slicing off the substrate along the plurality of holes to form a light emitting device. The light emitting device has a substrate wherein the sidewall of the substrate comprising a first area with a substantially flat surface and a second area with substantially textured surface. | 08-12-2010 |
20130302927 | Light-Emitting Device and Manufacturing Method Thereof - A light emitting device and a method of fabricating thereof are provided. The method of fabricating the light emitting device comprises: providing a substrate having a first major surface and a second major surface; forming a plurality of light-emitting stacks on the first major surface; forming an etching protection layer on each of the light emitting stacks; forming a plurality of holes by a discontinuous laser beam on the substrate; etching the plurality of holes; and slicing off the substrate along the plurality of holes to form a light emitting device. The light emitting device has a substrate wherein the sidewall of the substrate comprising a first area with a substantially flat surface and a second area with substantially textured surface. | 11-14-2013 |
Chi-Chih Chuang, Hsinchu City TW
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20080293342 | CMP HEAD AND METHOD OF MAKING THE SAME - A CMP head includes a membrane support and a membrane. The membrane support is disk-shaped, having an origin and a radius R. The membrane support has at least a ventilator disposed in a central region within the range between origin and (2/3) R, and at least a diversion opening disposed in a peripheral region within the range between (2/3) R and R. The membrane includes a disk-shaped part disposed on the first surface of the membrane support, and an annular part surrounding the annular sidewall of the membrane support. | 11-27-2008 |
Chieh-Lin Chuang, Hsinchu City TW
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20120311250 | ARCHITECTURE AND ACCESS METHOD OF HETEROGENEOUS MEMORIES - A heterogeneous memory architecture includes a first memory, a second memory and a memory controller. The first memory has a first memory space. The second memory has a second memory space larger than the first memory space. The memory controller is used for accessing common address space of the first memory and the second memory in a 2X-bit bandwidth, and for disabling the first memory and accessing non-common address space of the second memory in opposite to the first memory in a X-bit bandwidth, X being a positive integer. | 12-06-2012 |
Chih-Chiang Chuang, Hsinchu City TW
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20080252576 | PANEL DISPLAY APPARATUS AND SOURCE DRIVER THEREOF - A panel display apparatus and a source driver including a set of first input terminals, a set of second input terminals, a set of first output terminals, a set of second output terminals, an interface module and a driving module are disclosed. The sets of the first and the second input terminals are coupled to a previous source driver and a timing controller, respectively. The sets of the first and the second output terminals are coupled to a following source driver and a display panel, respectively. The interface module selects the set of the first or the second input terminals upon a pre-setting, and connects the selected input terminals to the set of the first output terminals. The driving module generates at least a driving signal upon a signal of the selected input terminals. The driving signal is outputted to the display panel through the second output terminals. | 10-16-2008 |
20080288261 | METHOD FOR DYNAMICALLY ADJUSTING AUDIO DECODING PROCESS - A method for dynamically arranging DSP tasks. The method comprises receiving an audio bit stream, checking a remaining execution time as the DSP transforms the audio information into spectral information, simplifying the step of transforming the audio information when the DSP detects that the remaining execution time is shorter then a predetermined interval, and skipping one section of the audio information and decoding the remaining section when the execution time is less than a predetermined interval. | 11-20-2008 |
20090040158 | GAMMA REFERENCE VOLTAGE GENERATING DEVICE, METHOD FOR GENERATING GAMMA REFERENCE VOTLAGE, AND GRAY LEVEL VOLTAGE GENERATING DEVICE - A gamma reference voltage generating device, a method for generating gamma reference voltages, and a gray level voltage generating device are provided. The gray level voltage generating device includes a selection unit and a gray level voltage generator. The selection unit is adapted for receiving M first gamma reference voltages, and selecting N second gamma reference voltages from the M first gamma reference voltages and outputting the N second gamma reference voltages, wherein M and N are positive integers, and M>N. The gray level voltage generator is coupled to the selection unit, for generating a plurality of gray level voltages according to the N second gamma reference voltages. The gamma curve can be adaptively adjusted by using the present invention so as to improve the display quality. | 02-12-2009 |
20090309860 | Driving Method and Related Device for Reducing Power Consumption of LCD - A driving method is provided for reducing power consumption of a liquid crystal display. The driving method includes steps of sequentially receiving first data and second data, determining whether the second data is the same as the first data, and controlling a data-line driving circuit not to read in driving data corresponding to the second data when the second data is the same as the first data. | 12-17-2009 |
20110099020 | Method for Dynamically Adjusting Audio Decoding Process - A method for dynamically arranging DSP tasks. The method comprises receiving an audio bit stream, checking a remaining execution time as the DSP transforms the audio information into spectral information, simplifying the step of transforming the audio information when the DSP detects that the remaining execution time is shorter then a predetermined interval, and skipping one section of the audio information and decoding the remaining section when the execution time is less than a predetermined interval. | 04-28-2011 |
Chih-Hua Chuang, Hsinchu City TW
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20130009718 | OSCILLATING SIGNAL GENERATING APPARATUS AND CONTROL SIGNAL GENERATOR OF THE OSCILLATING SIGNAL GENERATING APPARATUS - An oscillating signal generating device includes: an oscillating circuit arranged to generate an oscillating signal according to a current controlled signal; and a control signal generating circuit coupled to the oscillating circuit, the control signal generating circuit for receiving a first reference voltage and a second reference voltage, the control signal generating circuit operated between the first reference voltage and the second reference voltage, and the control signal generating circuit arranged to generate the current controlled signal according to a voltage input signal; wherein the control signal generating circuit is capable of monotonically generating the current controlled signal according to the voltage input signal when a voltage level of the voltage input signal falls between the first reference voltage and the second reference voltage. | 01-10-2013 |
Ching-Sang Chuang, Hsinchu City TW
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20100267177 | METHOD FOR FABRICATING ACTIVE DEVICE ARRAY SUBSTRATE - A method for fabricating an active device array substrate is provided. First, a substrate having a display area and a sensing area is provided. Then, a first patterned conductor layer is formed on the display area of the substrate. A gate insulator is formed on the substrate. A patterned semiconductor layer, a second patterned conductor layer and a patterned photosensitive dielectric layer are formed on the gate insulator, wherein the second patterned conductor layer includes a source electrode, a drain electrode and a lower electrode, the patterned photosensitive dielectric layer covering the second patterned conductor layer includes an interface protection layer disposed on the source electrode and the drain electrode and a photo-sensing layer disposed on the lower electrode. A passivation layer is then formed on the substrate. After that, a third patterned conductor layer including a pixel electrode and an upper electrode is formed on the passivation layer. | 10-21-2010 |
20120112214 | ACTIVE DEVICE ARRAY SUBSTRATE - An active device array substrate is provided. First, a substrate having a display area and a sensing area is provided. Then, a first patterned conductor layer is disposed on the display area of the substrate. A gate insulator is disposed on the substrate. A patterned semiconductor layer, a second patterned conductor layer and a patterned photosensitive dielectric layer are disposed on the gate insulator, wherein the second patterned conductor layer includes a source electrode, a drain electrode and a lower electrode, the patterned photosensitive dielectric layer covering the second patterned conductor layer includes an interface protection layer disposed on the source electrode and the drain electrode and a photo-sensing layer disposed on the lower electrode. A passivation layer is then disposed on the substrate. After that, a third patterned conductor layer including a pixel electrode and an upper electrode is disposed on the passivation layer. | 05-10-2012 |
Ching-Te Chuang, Hsinchu City TW
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20130194861 | SINGLE-ENDED SRAM WITH CROSS-POINT DATA-AWARE WRITE OPERATION - A single-ended SRAM including at least one memory cell and a third switch is provided. The memory cell includes a data-latching unit, a first switch, a second switch and a data-transferring unit. The data-latching unit is configured for latching the received input data and provides a storage data and the inverse data of the storage data. The first switch transfers a reference data to the data-latching unit according to a first word-line signal. The second switch transfers the reference data to the data-latching unit according to a second word-line signal. The data-transferring unit decides whether or not to transfer the reference data to the bit-line according to the storage data and a control signal. The third switch receives the reference data and the control signal and transfers the reference data to the first switch, the second switch and the data-transferring unit according to the control signal. | 08-01-2013 |
20160027500 | CIRCUIT FOR MITIGATING WRITE DISTURBANCE OF DUAL-PORT SRAM - A circuit for mitigating write disturbance including a first and a second discharge control paths is provided and applied to the dual-port SRAM. The first discharge control path is connected to bit lines of the second port and the first port, and a first control line. The second discharge control path is connected to inverse bit lines of the second port and the first port, and the first control line. A first discharge current is generated when the bit line of the second and the first ports are respectively at a high level voltage, and a low level voltage, and the first control line operates. A second discharge current is generated when the inverse bit line of the second and the first ports are respectively at the high level voltage and the low level voltage, and the first control line operates. | 01-28-2016 |
Chin-Kai Chuang, Hsinchu City TW
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20080274508 | Expression system for enhancing solubility and immunogeneicity of recombinant proteins - Expression system for enhancing solubility and immunogenicity of recombinant proteins. The expression system includes a protein expression vector that contains a chimeric gene encoding a chimeric protein. The chimeric protein contains three polypeptidyl fragments: (a) a first polypeptidyl fragment at the N-terminal end of the chimeric protein that contains a protein transduction domain (PTD) or a fragment thereof having HIV Tat PTD activity; (b) a second polypeptidyl fragment at the C-terminal end of the first polypeptidyl fragment that contains a J-domain or a fragment thereof having heat shock protein 70 (Hsp70)-interacting activity; and (c) a third polypeptidyl fragment at the C-terminal end of the second polypeptidyl fragment that contains a target protein or polypeptide. | 11-06-2008 |
20090187004 | EXPRESSION SYSTEM FOR ENHANCING SOLUBILITY AND IMMUNOGENEICITY OF RECOMBINANT PROTEINS - Expression system for enhancing solubility and immunogenicity of recombinant proteins. The expression system includes a protein expression vector that contains a chimeric gene encoding a chimeric protein comprising: (a) a first polypeptidyl fragment at the N-terminal end of the chimeric protein, containing a protein transduction domain (PTD), or a fragment thereof, having HIV Tat PTD activity; (b) a second polypeptidyl fragment at the C-terminal end of the first polypeptidyl fragment, containing a J-domain, or a fragment thereof, having heat shock protein 70 (Hsp70)-interacting activity; and (c) a third polypeptidyl fragment at the C-terminal end of the second polypeptidyl fragment, containing a target protein or polypeptide. | 07-23-2009 |
Chita Chuang, Hsinchu City TW
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20160064340 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device structure includes a first substrate having a first surface and a second surface opposite to the first surface, a conductive pad at the first surface of the first substrate, and a connector overlying the conductive pad, wherein the connector is configured for electrically connecting with a conductive land of a second substrate, wherein a geometric center of the connector is deviated from a geometric center of the conductive pad and a geometric center of the conductive land. | 03-03-2016 |
Chun-Hsiung Chuang, Hsinchu City TW
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20140181166 | APPARATUS FOR LOW COMPLEXITY SUB-NYQUIST SAMPLING OF SPARSE WIDEBAND SIGNALS - An apparatus for low complexity sub-Nyquist sampling of sparse wideband signals is provided, including a mixer, a periodic random sequence generator and a filter bank. The periodic random sequence generator generates a periodic pseudo-random sequence. The mixer is connected to the periodic random sequence generator for receiving the periodic pseudo-random sequence and mixing with an input signal to obtain a modulated signal. The filter bank further includes a plurality of filters and is connected to the mixer for filtering the modulated signal. The sub-Nyquist sampling apparatus may further includes a plurality of analog-to-digital convertors (ADCs), with each ADC connected to each filter of the filter bank to sample the signal from the filter bank and output a sampling signal. | 06-26-2014 |
Chun-Lung Chuang, Hsinchu City TW
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20140055940 | MEMORY DEVICE - A memory device includes a control board and a conductive housing. In one embodiment, a circuit ground in the control board is electrically coupled to the conductive housing to make a common ground contact. In another embodiment, differential impedances at different locations of a conductor are controllably maintained within a specified range by adjusting width of the conductor and/or spacing between the adjacent conductors of a differential pair. | 02-27-2014 |
20140198460 | Micro Secure Digital Adapter - A micro secure digital (SD) adapter, for adapting a micro SD card to an SD interface, the micro SD adapter comprising a micro SD slot, for disposing the micro SD card; a pin module, comprising a plurality of signal pins, a first ground pin, and a second ground pin; a plurality of connectors, for conducting the plurality of signal pins and the first ground pin to the micro SD card according to a pin configuration of the micro SD card when the micro SD card is disposed in the micro SD slot; and a conducting module, electrically connected between a terminal of a first connector corresponding to the first ground pin and the second ground pin. | 07-17-2014 |
Fong-Lung Chuang, Hsinchu City TW
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20080254619 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device is provided. First, a semiconductor substrate and a dielectric layer positioned on the semiconductor substrate are prepared. Subsequently, the dielectric layer is etched to form a hole structure in the dielectric layer. Afterward, a degas process is performed. An ultraviolet (UV) treatment is carried out to the semiconductor substrate in the degas process so as to expel at least a gas contained in the dielectric layer. Next, a barrier layer is formed on the sidewall and on the bottom of the hole structure. Furthermore, the hole structure is filled with a conductive material. Since the UV treatment can degas the dielectric layer efficiently, the formed semiconductor device can have a fine and stable structure. | 10-16-2008 |
20150064861 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device is provided. A substrate having a first gate and a second gate respectively formed in a first region and a second region is provided. An underlayer is formed on the substrate to cover the first gate in the first region and the second gate in the second region. A patterned mask with a predetermined thickness is formed on the underlayer in the first region. The underlayer corresponding to the second gate in the second region is removed by the patterned mask to expose the second gate, wherein the underlayer corresponding to the first gate in the first region is partially consumed to expose part of the first gate. | 03-05-2015 |
Gene C.h. Chuang, Hsinchu City TW
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20110158341 | METHOD AND APPARATUS FOR PHASE QUANTIZATION AND EQUAL GAIN PRECODING USING LATTICES - A method and apparatus are disclosed for phase quantization and equal gain precoding in a wireless communication system. The method includes scaling, by a receiving device, a phase vector based on a predetermined scaling factor to determine a first lattice point. The method also includes determining, by the receiving device, a second lattice point based on the determined first lattice point. In addition, the method includes determining, by the receiving device, a quantized phase vector based on the determined second lattice point and the predetermined scaling factor. | 06-30-2011 |
20120072151 | ENERGY DETECTION METHOD AND AN ENERGY DETECTION CIRCUIT USING THE SAME - An energy detection method is provided. The method obtains an initial time point of an input signal with reference to a digital signal corresponding to the input signal. An i | 03-22-2012 |
20120140848 | Transmitting Terminal and Transmit Antenna Selecting Method Thereof - A transmitting terminal includes a signal processing unit, M | 06-07-2012 |
Hak-Lay Chuang, Hsinchu City TW
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20120299115 | SEMICONDUCTOR STRUCTURE WITH SUPPRESSED STI DISHING EFFECT AT RESISTOR REGION - A method includes forming a first isolation feature of a first width and a second isolation feature of a second width in a substrate, the first width being substantially greater than the second width; forming an implantation mask on the substrate, wherein the implantation mask covers the first isolation feature and exposes the second isolation feature; performing an ion implantation process to the substrate using the implantation mask; and thereafter performing an etching process to the substrate. | 11-29-2012 |
20120319238 | Large Dimension Device and Method of Manufacturing Same in Gate Last Process - An integrated circuit device and methods of manufacturing the same are disclosed. In an example, integrated circuit device includes a capacitor having a doped region disposed in a semiconductor substrate, a dielectric layer disposed over the doped region, and an electrode disposed over the dielectric layer. At least one post feature embedded in the electrode. | 12-20-2012 |
20130154021 | ENHANCED GATE REPLACEMENT PROCESS FOR HIGH-K METAL GATE TECHNOLOGY - The present disclosure provides a method of fabricating a semiconductor device. A high-k dielectric layer is formed over a substrate. A first capping layer is formed over a portion of the high-k dielectric layer. A second capping layer is formed over the first capping layer and the high-k dielectric layer. A dummy gate electrode layer is formed over the second capping layer. The dummy gate electrode layer, the second capping layer, the first capping layer, and the high-k dielectric layer are patterned to form an NMOS gate and a PMOS gate. The NMOS gate includes the first capping layer, and the PMOS gate is free of the first capping layer. The dummy gate electrode layer of the PMOS gate is removed, thereby exposing the second capping layer of the PMOS gate. The second capping layer of the PMOS gate is transformed into a third capping layer. | 06-20-2013 |
Harry Hak-Lay Chuang, Hsinchu City TW
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20110042750 | CONTROLLING GATE FORMATION FOR HIGH DENSITY CELL LAYOUT - Methods of forming a semiconductor structure and the semiconductor structure are disclosed. In one embodiment, a method includes forming a gate dielectric layer over a substrate, forming a gate electrode layer over the gate dielectric layer, and etching the gate electrode layer and the gate dielectric layer to form a horizontal gate structure and a vertical gate structure, wherein the horizontal gate structure and the vertical gate structure are connected by an interconnection portion. The method further includes forming a photoresist covering the horizontal gate structure and the vertical gate structure, with the photoresist having a gap exposing the interconnection portion between the horizontal gate structure and the vertical gate structure, and then etching the interconnection portion. | 02-24-2011 |
20110057267 | POLYSILICON DESIGN FOR REPLACEMENT GATE TECHNOLOGY - The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature. | 03-10-2011 |
20110156142 | HIGH VOLTAGE DEVICE WITH PARTIAL SILICON GERMANIUM EPI SOURCE/DRAIN - A semiconductor device is provided which includes a semiconductor substrate, a gate structure formed on the substrate, sidewall spacers formed on each side of the gate structure, a source and a drain formed in the substrate on either side of the gate structure, the source and drain having a first type of conductivity, a lightly doped region formed in the substrate and aligned with a side of the gate structure, the lightly doped region having the first type of conductivity, and a barrier region formed in the substrate and adjacent the drain. The barrier region is formed by doping a dopant of a second type of conductivity different from the first type of conductivity. | 06-30-2011 |
20110193161 | METHOD AND APPARATUS OF FORMING A GATE - The present disclosure provides a semiconductor device having a transistor. The transistor includes a substrate and first and second wells that are disposed within the substrate. The first and second wells are doped with different types of dopants. The transistor includes a first gate that is disposed at least partially over the first well. The transistor further includes a second gate that is disposed over the second well. The transistor also includes source and drain regions. The source and drain regions are disposed in the first and second wells, respectively. The source and drain regions are doped with dopants of a same type. | 08-11-2011 |
20110193162 | LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR TRANSISTOR WITH PARTIALLY UNSILICIDED SOURCE/DRAIN - A method of fabricating a laterally diffused metal oxide semiconductor (LDMOS) transistor includes forming a dummy gate over a substrate. A source and a drain are formed over the substrate on opposite sides of the dummy gate. A first silicide is formed on the source. A second silicide is formed on the drain so that an unsilicided region of at least one of the drain or the source is adjacent to the dummy gate. The unsilicided region of the drain provides a resistive region capable of sustaining a voltage load suitable for a high voltage LDMOS application. A replacement gate process is performed on the dummy gate to form a gate. | 08-11-2011 |
20110195549 | GATE STACK FOR HIGH-K/METAL GATE LAST PROCESS - A method for fabricating an integrated circuit device is disclosed. An exemplary method includes providing a substrate; forming a high-k dielectric layer over the substrate; forming a first capping layer over the high-k dielectric layer; forming a second capping layer over the first capping layer; forming a dummy gate layer over the second capping layer; performing a patterning process to form a gate stack including the high-k dielectric layer, first and second capping layers, and dummy gate layer; removing the dummy gate layer from the gate stack, thereby forming an opening that exposes the second capping layer; and filling the opening with a first metal layer over the exposed second capping layer and a second metal layer over the first metal layer, wherein the first metal layer is different from the second metal layer and has a work function suitable to the semiconductor device. | 08-11-2011 |
20110195557 | METHOD FOR FORMING LOW RESISTANCE AND UNIFORM METAL GATE - The present disclosure provides a method that includes forming a high k dielectric layer on a semiconductor substrate; forming a polysilicon layer on the high k dielectric layer; patterning the high k dielectric layer and polysilicon layer to form first and second dummy gates in first and second field effect transistor (FET) regions, respectively; forming an inter-level dielectric (ILD); applying a first CMP process to the semiconductor substrate, exposing the first and second dummy gates; removing the polysilicon from the first dummy gate, resulting in a first gate trench; forming a first metal electrode in the first gate trench; applying a second CMP process; forming a mask covering the first FET region and exposing the second dummy gate; thereafter removing the polysilicon from the second dummy gate, resulting in a second gate trench; forming a second metal electrode in the second gate trench; and applying a third CMP process. | 08-11-2011 |
20110198675 | SPACER STRUCTURE OF A FIELD EFFECT TRANSISTOR - This disclosure relates to a spacer structure of a field effect transistor. An exemplary structure for a field effect transistor includes a substrate; a gate structure that has a sidewall overlying the substrate; a silicide region in the substrate on one side of the gate structure having an inner edge closest to the gate structure; a first oxygen-sealing layer adjoining the sidewall of the gate structure; an oxygen-containing layer adjoining the first oxygen-sealing layer on the sidewall and further including a portion extending over the substrate; and a second oxygen-sealing layer adjoining the oxygen-containing layer and extending over the portion of the oxygen-containing layer over the substrate, wherein an outer edge of the second oxygen-sealing layer is offset from the inner edge of the silicide region. | 08-18-2011 |
20110201172 | METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE - The disclosure relates to integrated circuit fabrication, and more particularly to a method for fabricating a semiconductor device. An exemplary method for fabricating the semiconductor device comprises providing a substrate; forming pad oxide layers over a frontside and a backside of the substrate; forming hardmask layers over the pad oxide layers on the frontside and the backside of the substrate; and thinning the hardmask layer over the pad oxide layer on the frontside of the substrate. | 08-18-2011 |
20110210403 | NOVEL STRUCTURES AND METHODS TO STOP CONTACT METAL FROM EXTRUDING INTO REPLACEMENT GATES - The methods and structures described are used to prevent protrusion of contact metal (such as W) horizontally into gate stacks of neighboring devices to affect the work functions of these neighboring devices. The metal gate under contact plugs that are adjacent to devices and share the (or are connected to) metal gate is defined and lined with a work function layer that has good step coverage to prevent contact metal from extruding into gate stacks of neighboring devices. Only modification to the mask layout for the photomask(s) used for removing dummy polysilicon is involved. No additional lithographical operation or mask is needed. Therefore, no modification to the manufacturing processes or additional substrate processing steps (or operations) is involved or required. The benefits of using the methods and structures described above may include increased device yield and performance. | 09-01-2011 |
20110215404 | Method and Apparatus of Forming ESD Protection Device - The present disclosure provides a semiconductor device having a transistor. The transistor includes a source region, a drain region, and a channel region that are formed in a semiconductor substrate. The channel region is disposed between the source and drain regions. The transistor includes a first gate that is disposed over the channel region. The transistor includes a plurality of second gates that are disposed over the drain region. | 09-08-2011 |
20110215420 | CASCODE CMOS STRUCTURE - A MOS device includes an active area having first and second contacts. First and second gates are disposed between the first and second contacts. The first gate is disposed adjacent to the first contact and has a third contact. The second gate is disposed adjacent to the second contact and has a fourth contact coupled to the third contact. A transistor defined by the active area and the first gate has a first threshold voltage, and a transistor defined by the active area and the second gate has a second threshold voltage. | 09-08-2011 |
20110220963 | METHOD AND APPARATUS OF FORMING BIPOLAR TRANSISTOR DEVICE - The present disclosure provides a semiconductor device having a transistor. The transistor includes a substrate. The transistor includes a collector region that is formed in a portion of the substrate. The transistor includes a base region that is surrounded by the collector region. The transistor includes an emitter region that is surrounded by the based region. The transistor includes an isolation structure that is disposed adjacent the emitter region. The transistor includes a gate structure that is disposed over a portion of the emitter region and a portion of the isolation structure. | 09-15-2011 |
20110221009 | METHOD AND APPARATUS FOR REDUCING GATE RESISTANCE - An apparatus has a semiconductor device that includes: a semiconductor substrate having a channel region, a high-k dielectric layer disposed at least partly over the channel region, a gate electrode disposed over the dielectric layer and disposed at least partly over the channel region, wherein the gate electrode is made substantially of metal, and a gate contact engaging the gate electrode at a location over the channel region. A different aspect involves a method for making a semiconductor device that includes: providing a semiconductor substrate having a channel region, forming a high-k dielectric layer at least partly over the channel region, forming a gate electrode over the dielectric layer and at least partly over the channel region, the gate electrode being made substantially of metal, and forming a gate contact that engages the gate electrode at a location over the channel region. | 09-15-2011 |
20110227161 | METHOD OF FABRICATING HYBRID IMPACT-IONIZATION SEMICONDUCTOR DEVICE - The present disclosure provides a semiconductor device which includes a semiconductor substrate, a first gate structure disposed over the substrate, the first gate structure including a first gate electrode of a first conductivity type, a second gate structure disposed over the substrate and proximate the first gate structure, the second gate structure including a second gate electrode of a second conductivity type different from the first conductivity type, a first doped region of the first conductivity type disposed in the substrate, the first doped region including a first lightly doped region aligned with a side of the first gate structure, and a second doped region of the second conductivity type disposed in the substrate, the second doped region including a second lightly doped region aligned with a side of the second gate structure. | 09-22-2011 |
20110227167 | REDUCED SUBSTRATE COUPLING FOR INDUCTORS IN SEMICONDUCTOR DEVICES - The present disclosure provides reduced substrate coupling for inductors in semiconductor devices. A method of fabricating a semiconductor device having reduced substrate coupling includes providing a substrate having a first region and a second region. The method also includes forming a first gate structure over the first region and a second gate structure over the second region, wherein the first and second gate structures each include a dummy gate. The method next includes forming an inter layer dielectric (ILD) over the substrate and forming a photoresist (PR) layer over the second gate structure. Then, the method includes removing the dummy gate from the first gate structure, thereby forming a trench and forming a metal gate in the trench so that a transistor may be formed in the first region, which includes a metal gate, and an inductor component may be formed over the second region, which does not include a metal gate. | 09-22-2011 |
20110237040 | MAIN SPACER TRIM-BACK METHOD FOR REPLACEMENT GATE PROCESS - The embodiments of methods described in this disclosure for trimming back nitride spacers for replacement gates allows the hard mask layers (or hard mask) to protect the polysilicon above the high-K dielectric during trim back process. The process sequence also allows determining the trim-back amount based on the process uniformity (or control) of nitride deposition and nitride etchback (or trimming) processes. Nitride spacer trim-back process integration is critical to avoid creating undesirable consequences, such as silicided polyisicon on top of high-K dielectric described above. The integrated process also allows widening the space between the gate structures to allow formation of silicide with good quality and allow contact plugs to have sufficient contact with the silicide regions. The silicide with good quality and good contact between the contact plugs and the silicide regions increase the yield of contact and allows the contact resistance to be in acceptable and workable ranges. | 09-29-2011 |
20120001259 | METHOD AND APPARATUS FOR IMPROVING GATE CONTACT - A method includes providing a substrate having a first surface, forming an isolation structure disposed partly in the substrate and having an second surface higher than the first surface by a step height, removing a portion of the isolation structure to form a recess therein having a bottom surface spaced from the first surface by less than the step height, forming a gate structure, and forming a contact engaging the gate structure over the recess. A different aspect involves an apparatus that includes a substrate having a first surface, an isolation structure disposed partly in the substrate and having a second surface higher than the first surface by a step height, a recess extending downwardly from the second surface, the recess having a bottom surface spaced from the first surface by less than the step height, a gate structure, and a contact engaging the gate structure over the recess. | 01-05-2012 |
20120009754 | METHOD FOR MAIN SPACER TRIM-BACK - The embodiments of methods described in this disclosure for trimming back nitride spacers for replacement gates allows the hard mask layers (or hard mask) to protect the polysilicon above the high-K dielectric during trim back process. The process sequence also allows determining the trim-back amount based on the process uniformity (or control) of nitride deposition and nitride etchback (or trimming) processes. Nitride spacer trim-back process integration is critical to avoid creating undesirable consequences, such as silicided polyisicon on top of high-K dielectric described above. The integrated process also allows widening the space between the gate structures to allow formation of silicide with good quality and allow contact plugs to have sufficient contact with the silicide regions. The silicide with good quality and good contact between the contact plugs and the silicide regions increase the yield of contact and allows the contact resistance to be in acceptable and workable ranges. | 01-12-2012 |
20120012937 | INTERCONNECTION STRUCTURE FOR N/P METAL GATES - The disclosure relates to integrated circuit fabrication, and more particularly to an interconnection structure for N/P metal gates. An exemplary structure for an interconnection structure comprises a first gate electrode having a first portion of a first work-function metal layer under a first portion of a signal metal layer; and a second gate electrode having a second portion of the first work-function metal layer interposed between a second work-function metal layer and a second portion of the signal metal layer, wherein the second portion of the signal metal layer is over the second portion of the first work-function metal layer, wherein the second portion of the signal metal layer and the first portion of the signal metal layer are continuous, and wherein a maximum thickness of the second portion of the signal metal layer is less than a maximum thickness of the first portion of the signal metal layer. | 01-19-2012 |
20120025309 | OFFSET GATE SEMICONDUCTOR DEVICE - An offset gate semiconductor device includes a substrate and an isolation feature formed in the substrate. An active region is formed in the substrate substantially adjacent to the isolation feature. An interface layer is formed on the substrate over the isolation feature and the active region. A polysilicon layer is formed on the interface layer over the isolation feature and the active region. A trench being formed in the polysilicon layer over the isolation feature. The trench extending to the interface layer. A fill layer is formed to line the trench and a metal gate formed in the trench. | 02-02-2012 |
20120025323 | SPACER STRUCTURES OF A SEMICONDUCTOR DEVICE - The disclosure relates to spacer structures of a semiconductor device. An exemplary structure for a semiconductor device comprises a substrate having a first active region and a second active region; a plurality of first gate electrodes having a gate pitch over the first active region, wherein each first gate electrode has a first width; a plurality of first spacers adjoining the plurality of first gate electrodes, wherein each first spacer has a third width; a plurality of second gate electrodes having the same gate pitch as the plurality of first gate electrodes over the second active region, wherein each second gate electrode has a second width greater than the first width; and a plurality of second spacers adjoining the plurality of second gate electrodes, wherein each second spacer has a fourth width less than the third width. | 02-02-2012 |
20120032238 | CONTACT ETCH STOP LAYERS OF A FIELD EFFECT TRANSISTOR - An exemplary structure for a field effect transistor according to at least one embodiment comprises a substrate comprising a surface; a gate structure comprising sidewalls and a top surface over the substrate; a spacer adjacent to the sidewalls of the gate structure; a first contact etch stop layer over the spacer and extending along the surface of the substrate; an interlayer dielectric layer adjacent to the first contact etch stop layer, wherein a top surface of the interlayer dielectric layer is coplanar with the top surface of the gate structure; and a second contact etch stop layer over the top surface of the gate structure. | 02-09-2012 |
20120074475 | METAL GATE STRUCTURE OF A SEMICONDUCTOR DEVICE - The applications discloses a semiconductor device comprising a substrate having a first active region, a second active region, and an isolation region having a first width interposed between the first and second active regions; a P-metal gate electrode over the first active region and extending over at least ⅔ of the first width of the isolation region; and an N-metal gate electrode over the second active region and extending over no more than ⅓ of the first width. The N-metal gate electrode is electrically connected to the P-metal gate electrode over the isolation region. | 03-29-2012 |
20120074498 | METHOD AND APPARATUS FOR IMPROVING GATE CONTACT - A method of fabricating a semiconductor device includes providing a substrate having a first surface, forming an isolation structure disposed partly in the substrate and having an second surface higher than the first surface by a step height, removing a portion of the isolation structure to form a recess therein having a bottom surface disposed below the first surface, and forming a contact engaging the gate structure over the recess. A different aspect involves an apparatus that includes a substrate having a first surface, an isolation structure disposed partly in the substrate and having a second surface higher than the first surface by a step height, a recess extending downwardly from the second surface, the recess having a bottom surface disposed below the first surface, a gate structure, and a contact engaging the gate structure over the recess. | 03-29-2012 |
20120083095 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE BY THINNING HARDMASK LAYERS ON FRONTSIDE AND BACKSIDE OF SUBSTRATE - The disclosure relates to integrated circuit fabrication, and more particularly to a method for fabricating a semiconductor device. An exemplary method for fabricating the semiconductor device comprises providing a substrate; forming pad oxide layers over a frontside and a backside of the substrate; forming hardmask layers over the pad oxide layers on the frontside and the backside of the substrate; and thinning the hardmask layer over the pad oxide layer on the frontside of the substrate. | 04-05-2012 |
20120104471 | CONTACT STRUCTURE FOR REDUCING GATE RESISTANCE AND METHOD OF MAKING THE SAME - A semiconductor device having a gate on a substrate with source/drain (S/D) regions adjacent to the gate. A first dielectric layer overlays the gate and the S/D regions, the first dielectric layer having first contact holes over the S/D regions with first contact plugs formed of a first material and the first contact plugs coupled to respective S/D regions. A second dielectric layer overlays the first dielectric layer and the first contact plugs. A second contact hole formed in the first and second dielectric layers is filled with a second contact plug formed of a second material. The second contact plug is coupled to the gate and interconnect structures formed in the second dielectric layer, the interconnect structures coupled to the first contact plugs. The second material is different from the first material, and the second material has an electrical resistance lower than that of the first material. | 05-03-2012 |
20120119306 | METAL GATE TRANSISTOR, INTEGRATED CIRCUITS, SYSTEMS, AND FABRICATION METHODS THEREOF - A method of forming an integrated circuit structure includes providing a gate strip in an inter-layer dielectric (ILD) layer. The gate strip comprises a metal gate electrode over a high-k gate dielectric. An electrical transmission structure is formed over the gate strip and a conductive strip is formed over the electrical transmission structure. The conductive strip has a width greater than a width of the gate strip. A contact plug is formed above the conductive strip and surrounded by an additional ILD layer. | 05-17-2012 |
20120270379 | METHOD OF FABRICATING A DUMMY GATE STRUCTURE IN A GATE LAST PROCESS - A method of semiconductor device fabrication including forming a plurality of gate structures in a first portion of a substrate, wherein the plurality of gate structures have a first height. A first metal gate structure is formed in a second portion of the substrate, the first metal gate structure being surrounded by an isolation region. A plurality of dummy gate structures is formed in the second portion of the substrate. The plurality of dummy gate structures are configured in a ring formation encircling the metal gate structure and the isolation region. The plurality of dummy structures have a top surface that is substantially planar with the plurality of gate structures and covers at least 5% of a pattern density of the second portion of the substrate. | 10-25-2012 |
20120280323 | DEVICE HAVING A GATE STACK - A device includes a drain, a source, and a gate stack. The gate stack has a gate dielectric layer, a gate conductive layer immediately on top of the gate dielectric layer, and first gate and a second gate layer that are immediately on top of the gate conductive layer. The first gate layer has a first resistance higher than a second resistance of the second gate layer. The second gate layer is conductive, is electrically coupled with the gate conductive layer, and has a contact terminal configured to serve as a gate contact terminal for the device. Fabrication methods of the gate stack are also disclosed. | 11-08-2012 |
20130012011 | INTERCONNECTION STRUCTURE FOR N/P METAL GATES - This description relates to a method for fabricating an interconnection structure in a complementary metal-oxide-semiconductor (CMOS). The method includes forming a first opening in a dielectric layer over a substrate and partially filling the first opening with a second work-function metal layer, wherein a top surface of the second work-function metal layer is below a top surface of the first opening. The method further includes forming a second opening adjoining the first opening in the dielectric layer over the substrate and depositing a first work-function metal layer in the first and second openings, whereby the first work-function metal layer is over the second work-function metal layer in the first opening. The method further includes depositing a signal metal layer over the first work-function metal layer in the first and second openings and planarizing the signal metal layer. | 01-10-2013 |
20130029482 | SPACER STRUCTURES OF A SEMICONDUCTOR DEVICE - The disclosure relates to spacer structures of a semiconductor device. An exemplary structure for a semiconductor device comprises a substrate having a first active region and a second active region; a plurality of first gate electrodes having a gate pitch over the first active region, wherein each first gate electrode has a first width; a plurality of first spacers adjoining the plurality of first gate electrodes, wherein each first spacer has a third width; a plurality of second gate electrodes having the same gate pitch as the plurality of first gate electrodes over the second active region, wherein each second gate electrode has a second width greater than the first width; and a plurality of second spacers adjoining the plurality of second gate electrodes, wherein each second spacer has a fourth width less than the third width. | 01-31-2013 |
20130244416 | SPACER STRUCTURE OF A FIELD EFFECT TRANSISTOR WITH AN OXYGEN-CONTAINING LAYER BETWEEN TWO OXYGEN-SEALING LAYERS - A method of fabricating a spacer structure which includes forming a dummy gate structure comprising a top surface and sidewall surfaces over a substrate and forming a spacer structure over the sidewall surfaces. Forming the spacer structure includes depositing a first oxygen-sealing layer on the dummy gate structure and removing a portion of the first oxygen-sealing layer on the top surface of the dummy gate structure, whereby the first oxygen-sealing layer remains on the sidewall surfaces. Forming the spacer structure further includes depositing an oxygen-containing layer on the first oxygen-sealing layer and the top surface of the dummy gate structure. Forming the spacer structure further includes depositing a second oxygen-sealing layer on the oxygen-containing layer and removing a portion of the second oxygen-sealing layer over the top surface of the dummy gate structure. Forming the spacer structure further includes thinning the second oxygen-sealing layer. | 09-19-2013 |
20130323919 | METHODS TO STOP CONTACT METAL FROM EXTRUDING INTO REPLACEMENT GATES - A method of preventing contact metal from protruding into neighboring gate devices to affect work functions of the neighboring gate devices is provided includes forming a gate structure. Forming the gate structure includes forming a work function layer, and forming a gate metal layer having a void, wherein the work function layer surrounds the gate metal layer. The method further includes forming a contact plug having a contact metal directly on the gate metal layer of the first gate stack, wherein the contact metal protrudes into the void, and the work function layer prevents the contact metal from protruding into a second gate stack. | 12-05-2013 |
20140017886 | SPACER STRUCTURES OF A SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes forming a first set of gate electrodes over a substrate, adjacent gate electrodes of the first set of gate electrodes being separated by a first gap width, and having a first gate width. The method includes forming a second set of gate electrodes over the substrate, adjacent gate electrodes of the second set of gate electrodes being separated by a second gap width less than the first gap width, and having a second gate width greater than the first gate width. The method further includes forming a first set of spacer structures on sidewalls of the first and second sets of gate electrodes. The method further includes forming a second set of spacer structures abutting the first set of spacer structures and removing a subset of the second set of spacer structures over the sidewalls of the second set of gate electrodes. | 01-16-2014 |
20140038376 | Method and Apparatus of Forming ESD Protection Device - The present disclosure provides a semiconductor device having a transistor. The transistor includes a source region, a drain region, and a channel region that are formed in a semiconductor substrate. The channel region is disposed between the source and drain regions. The transistor includes a first gate that is disposed over the channel region. The transistor includes a plurality of second gates that are disposed over the drain region. | 02-06-2014 |
20140045310 | METHOD OF MAKING STRUCTURE HAVING A GATE STACK - A method includes removing a first portion of a gate layer of a structure. The structure includes a drain region, a source region, and a gate stack, and the gate stack includes a gate dielectric layer, a gate conductive layer directly on the gate dielectric layer, and the gate layer directly on the gate conductive layer. A drain contact region is formed on the drain region, and a source contact region is formed on the source region. A conductive region is formed directly on the gate conductive layer and adjacent to a second portion of the gate layer. A gate contact terminal is formed in contact with the conductive region. | 02-13-2014 |
20140045328 | INTERCONNECTION STRUCTURE FOR N/P METAL GATES - A method for fabricating an interconnection structure in a complementary metal-oxide-semiconductor (CMOS) includes forming an opening in a dielectric layer over a substrate and forming a dummy electrode in a first portion of the opening in the dielectric layer. The method further includes filling a second portion of the opening with a second work-function metal layer, wherein a top surface of the second work-function metal layer is below a top surface of the opening and removing the dummy electrode. The method further includes depositing a first work-function metal layer in the first and second portions, whereby the first work-function metal layer is over the second work-function metal layer in the opening and depositing a signal metal layer over the first work-function metal layer in the first and second portions. | 02-13-2014 |
20140159139 | LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR TRANSISTOR WITH PARTIALLY UNSILICIDED SOURCE/DRAIN - A transistor includes a substrate, a gate over the substrate, a source and a drain over the substrate on opposite sides of the gate, a first silicide on the source, and a second silicide on the drain. Only one of the drain or the source has an unsilicided region adjacent to the gate to provide a resistive region. | 06-12-2014 |
20140299937 | SPACER STRUCTURES OF A SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes forming a first set of gate electrodes over a substrate, adjacent gate electrodes of the first set of gate electrodes being separated by a first gap width. Each gate electrode of the first set of gate electrodes has a first gate width. The method further includes forming a second set of gate electrodes over the substrate, adjacent gate electrodes of the second set of gate electrodes being separated by a second gap width less than the first gap width. Each gate electrode of the second set of gate electrodes has a second gate width greater than the first gate width. | 10-09-2014 |
20150118809 | METHOD OF MAKING STRUCTURE HAVING A GATE STACK - A method includes removing a first portion of a gate layer of a first transistor and leaving a second portion of the gate layer. The first transistor includes a drain region, a source region, and a gate stack, and the gate stack includes a gate dielectric layer, a gate conductive layer over the gate dielectric layer, and the gate layer directly on the gate conductive layer. The method includes removing a gate layer of a second transistor and forming a conductive region at a region previously occupied by the first portion of the gate layer of the first transistor, the unit resistance of the conductive region being less than that of the gate layer of the first transistor. | 04-30-2015 |
Hung-Chang Chuang, Hsinchu City TW
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20140056354 | VIDEO PROCESSING APPARATUS AND METHOD - The invention provides a video processing apparatus. In one embodiment, the video processing apparatus includes a decoder, a detector, and a motion estimation and motion compensation (MEMC) module. The decoder decodes video data to generate a series of video frames with time stamps. The detector detects discontinuity of the video frames to generate discontinuity information. The MEMC module selects a previous frame prior to the discontinuity and a subsequent frame after the discontinuity from the video frames according to the discontinuity information, performs a motion estimation process to determine at least one motion, performs a motion compensation process according to the motion vector to synthesize an interpolated frame from the previous frame and the subsequent frame, and inserts the interpolated frame into the video frames to obtain a series of compensated frames. | 02-27-2014 |
Hung-Yi Chuang, Hsinchu City TW
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20080239610 | CHIP SCALE GAS DISCHARGE PROTECTIVE DEVICE AND FABRICATION METHOD OF THE SAME - Disclosed is a chip scale gas discharge protective device whose metal coupled electrodes are fabricated through processes of yellow light, image formation, and electro-casting of metal electrode, and the two electrodes are facing each other in arch lines with the distance of a gap controlled within the range of 0.5˜10 μm, wherein the entire structure is performed by a bridge process without an extra gas filling procedure in the gap. Due to the fact that the gap is as small as only several μm, a relevant potential difference existing across there is sufficient to ionize the air thereby suppressing the electro-static discharge (ESD) through the protected electronic device, whereas the fabrication method is disclosed. | 10-02-2008 |
Jen-Hui Chuang, Hsinchu City TW
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20100157064 | OBJECT TRACKING SYSTEM, METHOD AND SMART NODE USING ACTIVE CAMERA HANDOFF - If an active smart node detects that an object leaves a center region of a FOV for a boundary region, the active smart node predicts a possible path of the object. When the object gets out of the FOV, the active smart node predicts the object appears in a FOV of another smart node according to the possible path and a spatial relation between cameras. The active smart node notifies another smart node to become a semi-active smart node which determines an image characteristic similarity between the object and a new object and returns to the active smart node if a condition is satisfied. The active smart node compares the returned characteristic similarity, an object discovery time at the semi-active smart node, and a distance between the active smart node and the semi-active smart node to calculate possibility. | 06-24-2010 |
20100290709 | METHOD AND APPARATUS FOR RECOGNIZING TYPES OF VEHICLES - Consistent with the disclosed embodiments, the shapes of the windows of vehicles are used as features for recognizing vehicle types. This method transforms vehicle images with different view angles in a homographic manner to a normalized coordinate system and further extracts normalized window images. Subsequently, the method recognizes target vehicle types correctly in accordance with the normalized window images. | 11-18-2010 |
20110044500 | Light Information Receiving Method, Unit and Method for Recognition of Light-Emitting Objects - A light information receiving method, a method and a unit for the recognition of light-emitting objects are provided. The light information receiving method includes the following steps. A light-emitting object array is captured to obtain a plurality of images, wherein the light-emitting object array includes at least one light-emitting object. A temporal filtering process is performed to the images to recognize a light-emitting object. A light-emitting status of the light-emitting object array is recognized according to the light-emitting object location. A decoding process is performed according to the light-emitting status to output an item of information. | 02-24-2011 |
20110102664 | LIGHTING CONTROL MODULE, VIDEO CAMERA COMPRISING THE SAME AND CONTROL METHOD OF THE SAME - The present invention provides a lighting control module, a video camera comprising the same and a control method of the same. The video camera of the invention includes a sensing module, a light-emitting module and a control module. The sensing module receives a reflected light beam from a recording direction of the video camera, and generates an image of a scene in the recording direction. The light-emitting module emits a light toward the recording direction. Additionally, the lighting control module is connected to the light-emitting module for controlling the light-emitting module to periodically emit the light from a first brightness to a second brightness. | 05-05-2011 |
20110118973 | IMAGE PROCESSING METHOD AND SYSTEM - An image processing method and a system are provided. The image processing method of moving camera comprises the following steps. An image of a road is captured by a first camera unit. A coordinate of the image of an object shown in the image of the road is captured when the image of the object shown in the image of the road is selected. At least an aiming angle of a second camera unit is adjusted according to the coordinate to make the field-of-view of the second camera unit aligned with the object. The image of the object is captured by the second camera unit. The image of the object is enlarged. | 05-19-2011 |
20120307137 | LIGHTING CONTROL MODULE, VIDEO CAMERA COMPRISING THE SAME AND CONTROL METHOD OF THE SAME - The present invention provides a lighting control module, a video camera comprising the same and a control method of the same. The video camera of the invention includes a sensing module, a light-emitting module and a control module. The sensing module receives a reflected light beam from a recording direction of the video camera, and generates an image of a scene in the recording direction. The light-emitting module emits a light toward the recording direction. Additionally, the lighting control module is connected to the light-emitting module for controlling the light-emitting module to periodically emit the light from a first brightness to a second brightness. | 12-06-2012 |
20120320162 | VIDEO OBJECT LOCALIZATION METHOD USING MULTIPLE CAMERAS - An efficient 3D object localization method using multiple cameras is provided. The proposed method comprises a three-dimensional object localization process that firstly generates a plurality of two-dimensional line samples originated from a pre-calibrated vanishing point in each camera view for representing foreground video objects, secondly constructs a plurality of three-dimensional line samples from the two-dimensional line samples in all the multiple camera views, and thirdly determines three-dimensional object to locations by clustering the three-dimensional line samples into object groups. | 12-20-2012 |
20140198219 | MULTI-FUNCTION CONTROL ILLUMINATION DEVICE - A multi-function control illumination device has a synchronization separator, a parameter setting device, a light emitting device, and a video processor. The synchronization separator connects with a video camera and the parameter setting device connecting with the light emitting device. The synchronization separator receives a video signal from the video camera, retrieves a synchronization signal from the video signal, and outputs the synchronization signal to the parameter setting device. The parameter setting device generates an electric signal corresponding to the synchronization signal according to at least one illumination parameter and outputs the electric signal to the light emitting device. The light emitting device emits toward a shooting direction of the video camera a light beam whose intensity periodically varies according to the electric signal. Thereby, the video camera captures images exposed by light beams of different intensities lest nearby persons be overexposed and distant persons be under-exposed. | 07-17-2014 |
20150268798 | TOUCH DISPLAY APPARATUS AND TOUCH SENSING METHOD - A touch display apparatus includes a display panel, a frame and a plurality of sensing modules. The frame is disposed around the display panel and a plurality of apertures is arranged on the frame. The sensing modules are disposed at different height levels respectively. Each sensing module generates sensing data. Each sensing module includes a plurality of sensing units. The sensing units are disposed along the frame respectively and sense light which passes through the apertures. A touch sensing method is also disclosed herein. | 09-24-2015 |
20150359423 | TRIAL FRAME AND METHOD FOR MEASURING KEY PARAMETER THEREOF - A trial frame includes a trial frame body and at least one measurement subject having a visual invariant geometric characteristic. The trial frame body has at least one key parameter. The measurement subject is disposed on the trial frame body and collaborates with a measurement method. A two-dimensional image of the measurement subject is recorded by an image capturing device when the trial frame body fits to a user, and the key parameter is deduced from the two-dimensional image of the measurement subject. | 12-17-2015 |
Jui Cheng Chuang, Hsinchu City TW
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20120001054 | SENSING DEVICE AND IMAGE SENSOR MODULE THEREOF - An image sensor module is installed in a sensing device, and is used to detect a reflected light of an object. The image sensor module includes a carrier, a light sensing element, and a package body. The light sensing element is disposed on a substrate. The carrier is disposed on the substrate in the sensing device. The light sensing element is installed in the carrier, and is electrically connected with the substrate via multiple solder balls. The package body is installed on the carrier, and has a reflecting and diverting element, which is located between the light sensing element and the object and is used for reflecting reflected light of the object and diverting the reflected light towards a receiving direction of the light sensing element. The light sensing element receives the reflected light and generates a corresponding sensing signal. | 01-05-2012 |
Jui-Ping Chuang, Hsinchu City TW
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20130288436 | Aqueous Cleaning Techniques and Compositions for use in Semiconductor Device Manufacturing - Some embodiments relate to a manufacturing method for a semiconductor device. In this method, a semiconductor workpiece, which includes a metal gate electrode thereon, is provided. An opening is formed in the semiconductor workpiece to expose a surface of the metal gate. Formation of the opening leaves a polymeric residue on the workpiece. To remove the polymeric residue from the workpiece, a cleaning solution that includes an organic alkali component is used. | 10-31-2013 |
20150108578 | AQUEOUS CLEANING TECHNIQUES AND COMPOSITIONS FOR USE IN SEMICONDUCTOR DEVICE MANUFACTURE - Some embodiments relate to a manufacturing method for a semiconductor device. In this method, a semiconductor workpiece, which includes a metal gate electrode thereon, is provided. An opening is formed in the semiconductor workpiece to expose a surface of the metal gate. Formation of the opening leaves a polymeric residue on the workpiece. To remove the polymeric residue from the workpiece, a cleaning solution that includes an organic alkali component is used. Other embodiments related to a semiconductor device resulting from the method. | 04-23-2015 |
20150241786 | Tool And Method Of Developing - A tool and a method of developing are provided. In various embodiments, the method of developing includes rotating a wafer at a first rotating speed. The method further includes dispensing a developer solution onto the wafer at the first rotating speed by a first nozzle above the wafer, wherein the first nozzle moves back and forth along a path during dispensing the developer solution. The method further includes rotating the wafer at a second rotating speed to spread the developer solution onto the wafer uniformly. The method further includes dispensing a rinse solution onto the wafer at the second rotating speed by a second nozzle above the wafer. | 08-27-2015 |
Jung-Hong Chuang, Hsinchu City TW
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20110122139 | TWO DIMENSIONAL VECTOR GRAPHICS TRIANGULATION SYSTEM AND METHOD THEREOF - A two dimensional (2D) vector graphics triangulation system and a method thereof are provided. The system includes a memory module and a triangle mesh processing module. The memory module temporarily stores a triangle mesh triangulated from a 2D vector graphics into a binary tree data structure. The triangle mesh processing module adjusts the triangle mesh, or re-performs a triangulation processing to a local region of the loop when a state of a loop of the 2D vector graphics is changed. The triangle mesh processing module includes a level of detail unit, which proportionally adjusts an error threshold according to a zoom condition of the loop, updates an error value of each boundary line when the loop is deformed, and splits a boundary line or merges two neighbouring boundary lines according to the error values of the boundary lines and the error threshold. | 05-26-2011 |
Ju Yuan Chuang, Hsinchu City TW
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20110043033 | Out-Door Unit with Multiple Ports - An out-door unit with multiple ports comprises a plurality of circuit blocks, a DC-DC converter and a plurality of ports. The DC-DC converter is configured to provide current to the plurality of circuit blocks. The plurality of ports is connected to a plurality of in-door units respectively via a diode and provides current from the plurality of in-door units to the DC-DC converter via a diode respectively. At least one of the plurality of ports is connected to a first circuit block of the plurality of circuit blocks to provide current to the first circuit block. | 02-24-2011 |
Kai-Cheng Chuang, Hsinchu City TW
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20110122086 | TOUCH DISPLAY MODULE AND TOUCH DISPLAY APPARATUS COMPRISING THE SAME - A touch display apparatus comprising a controller and a touch display module, electrically connected to the controller, are provided. The touch display module comprises a display panel and a sensor assembly. The display panel includes a display surface and a connection surface opposite the display surface, and the sensor assembly is disposed on the connection surface and electrically connected to the controller. The sensor assembly comprises a first sensing layer and a second sensing layer, with a first sheet conducting layer and a second sheet conducting layer, respectively. When the display surface is touched, the first sheet conducting layer and the second sheet conducting layer are electrically connected to generate a touch signal. Thereby, the controller may detect a touch position according to the touch signal. | 05-26-2011 |
20110175872 | DISPLAY DEVICE FOR CONVERTING BETWEEN BRIGHT AND DARK STATES AND METHOD THEREOF - The configurations and controlling methods of a display device are provided in the present invention. The proposed display device having an environmental brightness, a display content and a display background with a display brightness includes a light sensor sensing the environmental brightness and adjusting the display brightness according to the environmental brightness such that a reader could read the display content easily. | 07-21-2011 |
20110279385 | TOUCH DISPLAY APPARATUS AND ELECTRONIC READING APPARATUS WITH TOUCH INPUT FUNCTION - The present invention relates to a touch display apparatus, which is including a display unit and a touch unit installed under the display unit. The display unit includes a first substrate and a second substrate installed in parallel. The touch unit includes a third substrate installed under the second substrate in parallel, and a plurality of first electrodes and a plurality of second electrodes separately installed on the lower surface of the second substrate and on the upper surface of the third substrate and facing each other. When a user touches the display unit of the electronic reading apparatus, the display unit will have a local deformation accordingly, the first electrode and the second electrode touch each other, and thus a touch signal is generated. Therefore, a touch function can be achieved. | 11-17-2011 |
20110285733 | DIGITAL STICKY NOTE WITH ELECTRIC PAPER DISPLAY - A digital sticky note has an electric paper displayer having a substrate. In addition, a display is configured on the substrate for showing an image picture without power. Further, a wireless receiver module, a process unit and a display circuit are also configured on the substrate. Wherein, the wireless receiver module receives a memo information through a wireless transmission interface, and transmits the memo information to the processor unit. Therefore, the processor unit controls the display circuit to show the memo information on the display array according to the obtained memo information. | 11-24-2011 |
20120036088 | Price display apparatus having bistable display panel and method thereof - The configurations of a price display apparatus and a method thereof are provided in the present invention. The proposed price display apparatus includes a bistable display panel displaying a selling price of an item. | 02-09-2012 |
20120038598 | ELECTROPHORETIC DISPLAY APPARATUS AND METHOD FOR MANUFACTURING THE SAME AND METHOD FOR DRIVING THE SAME - An electrophoretic display device includes an electrophoretic displaying layer, a photoconductive layer and a top electrode layer. The electrophoretic displaying layer includes a number of pixels. The top electrode layer and the photoconductive layer are respectively disposed at two opposite sides of the electrophoretic displaying layer. The photoconductive layer includes a number of photoconductive units spaced apart from each other. Each of the pixels corresponds to at least one photoconductive units. The present invention also provides a method for manufacturing the electrophoretic display device and a method for driving the electrophoretic display device. | 02-16-2012 |
20150279862 | THIN FILM TRANSISTOR SUBSTRATE AND DISPLAY DEVICE HAVING SAME - A thin film transistor (TFT) substrate includes a substrate which is a flexible substrate, and a TFT structure disposed on the substrate and including a gate layer, a gate insulator layer, a first channel island and a second channel island. The gate layer is disposed on the substrate and including a first gate electrode and a second gate electrode electrically connected to each other. The first and second gate electrodes are parts of the same TFT structure. The gate insulator layer covers the first and second gate electrodes. The first and second channel islands are disposed on the gate insulator layer and respectively correspond to the first and second gate electrodes. The source and drain layer is disposed on the gate insulator layer and next to the first and second channel islands, wherein the source and drain layer partially covers top surfaces of the first and second channel islands. | 10-01-2015 |
Keh-Shih Chuang, Hsinchu City TW
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20130015359 | SINGLE PHOTON EMISSION COMPUTED TOMOGRAPHY INSTRUMENT AND THE OPERATING METHOD THEREOFAANM CHUANG; Keh-ShihAACI Hsinchu CityAACO TWAAGP CHUANG; Keh-Shih Hsinchu City TW - A single photon emission computed tomography instrument is provided, which has a platform, at least one detector, at least one beam stopper, a signal processing device and a computer. The at least one detector is disposed at one side of the platform, and the at least one beam stopper is disposed between the platform and the detector. The signal processing device is electrically communicated with the at least one detector, and the computer is electrically communicated with the signal processing device. The present disclosure further provides an operating method which the beam stopper is added or removed respectively while scanning an analyze by the single photon emission computed tomography instrument in different angles. The projection dataset emitted from the focus could be estimated by subtracting the projecting data without the beam stopper from that with the beam stopper, and high resolution image could be obtained by using image reconstruction program. | 01-17-2013 |
Keng-Han Chuang, Hsinchu City TW
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20110199763 | LIGHT COMBINATION DEVICE - A light combination device includes a reflective element and a first color separating element. The reflective element guides first color light beams emitted from at least a first light source and a second light source to propagate in a first direction. The first light source and the second light source are differently positioned in a space. The first color separating element transmits the first color light beams and reflects second color light beams emitted from at least a third light source and a fourth light source. The third light source and the fourth light source are differently positioned in the space. The first color separating element has a coating curved surface, and a curvature of the coating curved surface is varied according to positions of the third light source and the fourth light source to guide the second color light beams to propagate in the first direction. | 08-18-2011 |
Kun-Lin Chuang, Hsinchu City TW
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20150231864 | COMPOSITE BOARD STRUCTURE AND FLEXIBLE DEVICE - A composite plate structure including a flexible substrate and a release layer is provided. The flexible substrate has an upper surface and a lower surface. The release layer is disposed on the lower surface of the flexible substrate, and includes a hydrophobic material and a bonding material. The hydrophobic material includes at least one fluorine atom. The bonding material at least includes an amide functional group or an epoxy functional group. The bonding material is bonded to the flexible substrate through the amide functional group or the epoxy functional group. A flexible apparatus including the composite plate structure is also provided. | 08-20-2015 |
Kuo-Liang Chuang, Hsinchu City TW
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20140118676 | DISPLAY DEVICE AND DISPLAY APPARATUS - A display device includes a first substrate, a second substrate, a space layer, and a protective film. The first substrate has a first surface, and the second substrate comprises a visible region and a non-visible region. The second substrate has a second surface, and the second surface is opposite to the first surface. The space layer includes a plurality of spacers and at least one space component. The spacers are located on the visible region, and the space component is located in the non-visible region. The protective film has water vapor barrier property. The protective film covers the space component, and forms at least one barrier wall. The barrier wall touches the first surface and the second surface. | 05-01-2014 |
Kuo-Sheng Chuang, Hsinchu City TW
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20130034966 | CHEMICAL DISPERSION METHOD AND DEVICE - A method of semiconductor fabrication including providing a semiconductor wafer and dispensing a first chemical spray onto the wafer using a first nozzle and dispensing a second chemical spray using a second nozzle onto the wafer. These dispensing may be performed simultaneously. The method may further include moving the first and second nozzle. The first and second nozzle may provide the first and second chemical spray having at least one different property. For example, different chemical compositions, concentrations, temperatures, angles of dispensing, or flow rate. A chemical dispersion apparatus providing two nozzles which are operable to be separately controlled is also provided. | 02-07-2013 |
20130045606 | SEMICONDUCTOR DEVICE CLEANING METHOD AND APPARATUS - A method includes providing a wafer and providing a first spray bar spaced a distance from the wafer. A first spray is dispensed from the first spray bar onto a first portion (e.g., half) of the wafer. Thereafter, the wafer is rotated. A second spray is dispensed from the first spray bar onto a second portion (e.g., half) of the rotated wafer. In embodiments, a plurality of spray bars are positioned above the wafer. One or more of the spray bars may be tunable in separation distance and/or angle of dispensing. | 02-21-2013 |
20130068248 | SEMICONDUCTOR DEVICE CLEANING METHOD - The present disclosure provides a method including providing a chamber having a first inlet and a second inlet. A solution of a de-ionized (DI) water and an acid (e.g., a dilute acid) is provided to the chamber via the first inlet. A carrier gas (e.g., N | 03-21-2013 |
20130074872 | IN-SITU BACKSIDE CLEANING OF SEMICONDUCTOR SUBSTRATE - The present disclosure provides a method and apparatus for cleaning a semiconductor wafer. In an embodiment of the method, a single wafer cleaning apparatus is provided and a wafer is positioned in the apparatus. A first chemical spray is dispensed onto a front surface of the wafer. A back surface of the wafer is cleaned while dispensing the first chemical spray. The cleaning of the back surface may include a brush and spray of cleaning fluids. An apparatus operable to clean the front surface and the back surface of a single semiconductor wafer is also described. | 03-28-2013 |
20130171336 | WAFER PROCESSING METHOD AND SYSTEM USING MULTI-ZONE CHUCK - In a wafer processing method and a wafer processing system, a first property on a back side of a wafer is measured. The back side of the wafer is supported on a multi-zone chuck having a plurality of zones with controllable clamping forces. The wafer is secured to the multi-zone chuck by controlling the clamping forces in the corresponding zones in accordance with measured values of the first property in the zones. | 07-04-2013 |
20140158172 | SYSTEM AND METHOD OF CLEANING FOUP - A system for cleaning a container such as semiconductor wafer carrier includes a housing, a cleaning unit in the housing, an analyzing unit within the housing, and a vacuum unit within the housing. The cleaning unit comprises a cleaning chamber, and is configured to spray a cleaning medium into the container in the cleaning chamber and dry the container. The analyzing unit is configured to analyze air inside the container coming out of the cleaning chamber, and provide a testing result for each ingredient of possible airborne molecular contamination (AMC) and humidity. The vacuum unit comprises a vacuum chamber configured to apply vacuum onto a container when the testing result for an ingredient is higher than a respective threshold. | 06-12-2014 |
20140202383 | WAFER PROCESSING SYSTEM USING MULTI-ZONE CHUCK - A wafer processing system includes at least one metrology chamber, a process chamber, and a controller. The at least one metrology chamber is configured to measure a thickness of a first layer on a back side of a wafer. The process chamber is configured to perform a treatment on a front side of the wafer. The front side is opposite the back side. The process chamber includes therein a multi-zone chuck. The multi-zone chuck is configured to support the back side of the wafer. The multi-zone chuck has a plurality of zones with controllable clamping forces for securing the wafer to the multi-zone chuck. The controller is coupled to the metrology chamber and the multi-zone chuck. The controller is configured to control the clamping forces in the corresponding zones in accordance with measured values of the thickness of the first layer in the corresponding zones. | 07-24-2014 |
20150068559 | Device Manufacturing Cleaning Process Using Vaporized Solvent - A cleaning method using vaporized solvent is provided. A solvent-containing vapor is generated, wherein the solvent-containing vapor comprises a solvent. The solvent-containing vapor is conducted to a substrate having debris or contaminants to clean the substrate, wherein the solvent-containing vapor condenses to form a liquid on a surface of the substrate. The liquid phase of the solvent-containing vapor is changed to a solid phase. The solid phase of the solvent-containing vapor is changed back to a liquid phase. The substrate is spun dried to remove the solvent-containing vapor in liquid phase and any debris or contaminants. | 03-12-2015 |
20150101482 | MECHANISMS FOR CONTROLLING GAS FLOW IN ENCLOSURE - Embodiments of mechanisms for controlling a gas flow in an interface module are provided. A method for controlling a gas flow in an enclosure includes providing the enclosure which is capable of containing a substrate. The method also includes providing a gas into the enclosure. The method further includes cleaning the gas. In addition, the method includes actuating the gas to generate the gas flow, and the gas flow passes through the substrate when the substrate is located in the enclosure. | 04-16-2015 |
20150101703 | ULTRA-LOW OXYGEN AND HUMILITY LOADPORT AND STOCKER SYSTEM - One or more apparatuses for adjusting at least one of an oxygen content or a water content in a pod and methods of their use are provided, where one or more semiconductor wafer are selectively stored within a storage chamber of the pod. The apparatus comprises the pod and a pipeline. The pod comprises the storage chamber and a port. The port comprises a receptacle having a first opening and a constraining ring proximate the first opening. The pipeline comprises a pipe, a diffuser attached to a first end of the pipe and a controller attached to a second end of the pipe. | 04-16-2015 |
20150144161 | DISPENSING APPARATUS AND DISPENSING METHOD - A dispensing method is disclosed that includes the following steps: a cleaning sleeve is provided to surround a spray member. A first fluid is previously dispensed from a first fluid outlet of the spray member. A second fluid is sprayed from a second fluid outlet of the cleaning sleeve to clean the spray member. The cleaning sleeve is opened or slid away from the spray member, such that the first fluid outlet of the spray member is exposed to a substrate. The first fluid is dispensed from the first fluid outlet of the spray member to the substrate. | 05-28-2015 |
20150147826 | Integrated System, Integrated System Operation Method And Film Treatment Method - An integrated system operation method is disclosed that includes the following steps: the film of a substrate is measured by a metrology apparatus to obtain a film information. The substrate is moved from the metrology apparatus to a process apparatus adjacent to the transfer apparatus. The film information is sent to the process apparatus. A film treatment is applied to the substrate in accordance with the film information. | 05-28-2015 |
Li-Heng Chuang, Hsinchu City TW
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20090129437 | PROBE COVER FOR EAR THERMOMETER AND MANUFACTURING METHOD THEREOF - The present invention provides a probe cover for an ear thermometer and a manufacturing method thereof. The probe cover is for sheathing a measuring probe of the ear thermometer, and an engaging means is provided at a bottom of the measuring probe. The probe cover comprises a main body of a hollow structure, an abutting segment and a base. Therein, the main body has an open end and a closed end opposite to the open end. An assembling direction extending from the open end toward the closed end is where the measuring probe is assembled along. Further, the main body has a diameter gradually reducing along the assembling direction. The closed end allows infrared rays to be received by the measuring probe to pass therethrough. Therein, the abutting segment is provided at the open end of the main body, and the base is annularly provided around a periphery of the abutting segment. The probe cover is characterized in being integrally formed, and having an annular shoulder provided at the abutting segment for accommodating the engaging means of the ear thermometer, as well as a plurality of separated protuberances, which are formed inwardly at a combining portion between the abutting segment and the base, for being engaged with the engaging means of the ear thermometer so that the probe cover can be firmly engaged with the measuring probe. | 05-21-2009 |
Meng-Ju Chuang, Hsinchu City TW
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20100195017 | ELECTRONIC DEVICE, LIQUID CRYSTAL DISPLAY MODULE, BACKLIGHT UNIT, AND FRONT FRAME THEREOF - The invention provides an electronic device including a liquid crystal display module and a control circuit. The liquid display module includes a backlight unit and a liquid display panel. The backlight unit has a front frame which includes a plastic frame and a conductive line. The conductive line extends from the rear surface to the rear surface to the front surface of the plastic frame so as to form a contact on the front surface. | 08-05-2010 |
Meng-Ping Chuang, Hsinchu City TW
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20130105864 | LAYOUT CONFIGURATION FOR MEMORY CELL ARRAY | 05-02-2013 |
20140035111 | LAYOUT CONFIGURATION FOR MEMORY CELL ARRAY - A layout configuration for a memory cell array includes at least a comb-like doped region having a first conductivity type and a fishbone-shaped doped region having a second conductivity type. The second conductivity type and the first conductivity type are complementary. Furthermore, the comb-like doped region and the fishbone-shaped doped region are interdigitated. | 02-06-2014 |
Ming-Chuen Chuang, Hsinchu City TW
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20150107441 | COLOR-BASED MUSIC OUTPUT SYSTEM AND METHOD THEREOF - The present invention discloses a color-based music output system and a method thereof. The system of the present invention comprises a pickup unit receiving a musical signal; a recognition unit electrically connected with the pickup unit to receive the musical signal and recognizing musical elements from the musical signal; a conversion unit electrically with the recognition unit to receive the musical elements and converting the musical elements into colored musical notes; and a processing unit electrically connected with the pickup unit, the recognition unit and the conversion unit, receiving the colored musical notes, and outputting a colored musical notation corresponding to the colored musical notes. The present invention provides an easy-to-read colored musical notation to simplify the conventional five-line staff and overcome the disadvantages thereof and also provides an innovative color-based music output system to make users read musical notations easier. | 04-23-2015 |
Min Lun Chuang, Hsinchu City TW
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20080238479 | REVERSIBLE SEQUENTIAL ELEMENT AND REVERSIBLE SEQUENTIAL CIRCUIT THEREOF - A reversible sequential element comprises a first logic gate and a second logic gate. The first logic gate includes a first input terminal, a second input terminal, a third input terminal, a first output terminal coupled to the first input terminal, a second output terminal and a third output terminal. The second logic gate includes a first input line, a second input line, a first output line and a second output line. When the first input terminal is set to a first state, the second input terminal is coupled to the third output terminal and the third input terminal is coupled to the second output terminal; otherwise, the second input terminal is coupled to the second output terminal and the third input terminal is coupled to the third output terminal. The third output terminal, second input line and second output line are coupled to each other. The input signal carried on the first input line is set as 0 so that the second output line and the first output line have the same output. | 10-02-2008 |
Shang-Yu Chuang, Hsinchu City TW
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20130312813 | SOLAR CELL AND MODULE THEREOF - A solar cell includes a silicon semiconductor substrate, a composite multifunctional protective film, a plurality of front electrodes and a plurality of back electrodes. The silicon semiconductor substrate has a roughened first surface. A depth of the doped layer arranged under the first surface ranges from 200 nm to 1000 nm. A surface doping concentration of the doped layer ranges from 1×10 | 11-28-2013 |
20140352773 | SOLAR CELL - A solar cell includes a photovoltaic substrate having a first surface and a second surface and a plurality of bus bar electrode net structures. The bus bar electrode net structures are separately disposed on the first surface, each bus bar electrode net structure includes a bus bar electrode, a plurality of finger electrodes, at least one connecting line electrode and at least one vertical finger electrode. The bus bar electrode is disposed on the first surface. The finger electrodes are separately disposed at two sides of the bus bar electrode. The connecting line electrode is disposed on the first surface. Each connecting line electrode connects with ends of at least two finger electrodes. The vertical finger electrode is disposed on the first surface, and is parallel to the bus bar electrode and disposed between the two ends of the finger electrode to connect with at least two adjacent finger electrodes. | 12-04-2014 |
Sheng-Yi Chuang, Hsinchu City TW
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20100045206 | LED Driving Circuit - An LED driving circuit to provide DC power to an LED to generate light includes a voltage-lowering regulation circuit, a rectification circuit and a filter and current-limiting circuit. The voltage-lowering regulation circuit aims to regulate impedance and provide a back electromotive force with polarity opposite to input voltage so that input power passed through the voltage-lowering regulation circuit is offset by the back electromotive force to a lower voltage. Then the input power passes through the rectification circuit to become DC power. The filter and current-limiting circuit receives the DC power and has at least one filter element to absorb or release the voltage to perform filtering and at least one current-limiting resistor to limit DC value. Therefore, the DC power has a steady voltage and current to energize the LED for lighting. | 02-25-2010 |
20100314808 | METHOD FOR MANUFACTURING LAMP SHELL - A method for manufacturing lamp shell to improve structural strength and light penetration includes steps of: providing a plastic material, injecting the plastic material into a injection molding equipment to form a preform containing a first space with an opening and a connecting section at one end and a closed another end to form a light penetrating section, and placing the preform in a blow molding equipment and blowing the plastic material by injecting gas to inflate the preform through gas pressure to form a second space at a greater size than the first space to become a lamp shell. The lamp shell thus formed has a greater structural strength to meet safety requirements, and also provides improved light penetration, and can reduce material consumption of the lamp shell to save production cost. | 12-16-2010 |
20110156583 | LED LAMP SET AND LIGHTING BULB OF THE SAME - An LED lamp set and a lighting bulb used thereon are provided. The LED lamp set comprises a plurality of circuit boards, a support post, an ignition circuit and two conducting wires. The circuit boards are spaced from each other in a parallel manner and mounted on the support post in series. Each of the circuit boards is connected to a plurality of LEDs surrounding the support post. The LEDs have a plurality of light emission surfaces tilted outwards. The ignition circuit receives an input power and transforms the input power to an ignition power. The two conducting wires have one end connected to the ignition circuit and linked to the circuit boards in series to ignite the LEDs. The LED lamp set further is coupled with a socket and a lamp shade to form a profile of a lighting bulb compatible to the socket of the ordinary lighting bulbs. | 06-30-2011 |
20110248631 | LED LAMP SET - An LED lamp set includes a socket connecting to electric power, an ignition circuit board held in the socket to form electric connection therewith and a lamp assembly controlled by the ignition circuit board. The lamp assembly includes a stem and a plurality of LED substrates fastened to the stem. The stem has a plurality of troughs formed on the circumference and a plurality of spacers to separate the troughs. The stem further has an upper holding portion at the upper circumference to form a retaining space with the troughs and a sealed lower side connecting to a circuit board. The circuit board and the ignition circuit board are electrically connected. Each LED substrate has at least a portion wedged in the retaining space and is electrically connected to a plurality of LEDs. The LED substrate has an electric connection portion electrically connected to the circuit board. | 10-13-2011 |
20120187817 | INSULATION REINFORCING LIGHT BULB - An insulation reinforcing light bulb includes a light penetrable shell, a power receiving base, a heat sink and an assembling holder located between the light penetrable shell and the power receiving base, at least one light source baseboard located in the light penetrable shell and a power conversion board electrically connected to the light source baseboard and the power receiving base. The heat sink has a housing chamber to hold the power conversion board. The light bulb further includes an isolation element held in the housing chamber. The isolation element has an isolation wall interposed between the power conversion board and the heat sink to form a circuit housing compartment to hold the power conversion board, and a wiring outlet formed on the isolation wall to allow wires to be led from the power conversion board to connect to the light source baseboard. | 07-26-2012 |
20120187818 | LED LIGHT BULB EQUIPPED WITH LIGHT TRANSPARENT SHELL FASTENING STRUCTURE - An LED light bulb includes a power conversion board, at least one light source baseboard electrically connected to the power conversion board, a heat sink and a light transparent shell to hold the light source baseboard. The heat sink has a wedged groove with a first holding portion formed thereon. The light transparent shell includes a sphere and a neck wedged in the wedged groove. The sphere and neck have an inner wall surrounded to hold the power conversion board and an outer wall opposite to the inner wall. The neck has a longitudinal shell retaining portion on the outer wall corresponding and fastening to the first holding portion and at least one transverse shell retaining portion. The wedged groove has at least one second holding portion corresponding and fastening to the transverse shell retaining portion to restrict relative turning of the light transparent shell and heat sink. | 07-26-2012 |
20120188775 | LED LIGHT BULB - An LED light bulb includes a light transparent shell, a power receiving base, a heat sink and a coupling holder located between the light transparent shell and power receiving base, at least one light source baseboard held in the light transparent shell, and a power conversion board electrically connected to the light source baseboard and power receiving base. The heat sink has a housing chamber to hold the power conversion board and an annular coupling wall surrounded to form an area to couple with the light source baseboard. The light source baseboard has a contact surface on the circumference to form compact coupling with the coupling wall so that the light source baseboard is securely held on the heat sink without deforming at high temperature to provide improved heat conduction capability. | 07-26-2012 |
20130208474 | LED LIGHT BULB PROVIDIG HIGH HEAT DISSIPATION EFFICIENCY - An LED light bulb includes a lamp shell, a light emitting assembly and a power receiving base. The lamp shell includes a light transmissive portion and a holding portion. The light emitting assembly includes a light source baseboard located in the light transmissive portion and a circuit board connecting to the light source baseboard. The circuit board is surrounded by a heat sink. The heat sink includes a heat collecting section and a holding section extended from the heat collecting section into the power receiving base such that the power receiving base fully encases the heat sink without exposing. The inner surface of the power receiving base connects to the outer surface of the holding section so that heat generated by the light source baseboard is absorbed by the heat collecting section and transmitted via the holding section to the power receiving base for dissipating. | 08-15-2013 |
20140043815 | LIGHT EMITTING DIODE BULB STRUCTURE FOR ENHANCING HEAT DISSIPATION EFFICIENCY - A light emitting diode (LED) bulb structure includes a lamp shell, a light emitting assembly, a heat conducting body and a heat dissipating body. The light emitting assembly includes a light source substrate carrying at least one light emitting element. The heat conducting body includes a heat collecting portion contacting the light source substrate, a heat conducting portion connecting to the heat collecting portion, and multiple heat conducting fins extended radially and outwardly from the heat conducting portion. The heat dissipating body is formed on the heat conducting body through injection molding and includes multiple heat dissipating fins disposed on the surface thereof correspondingly to the heat conducting fins such that the heat conducting fins are encased therein. Accordingly, heat generated by the light source substrate is absorbed by the heat collecting portion and then conducted from the heat conducting fins to the heat dissipating fins for dissipation. | 02-13-2014 |
20150070894 | LAMP STRING APPARATUS AND METHOD OF MANUFACTURING THEREOF - A lamp string apparatus and method of manufacturing thereof include a plurality of bases each holding a lighting bulb and including an internal thread portion corresponding to the lighting bulb, a first conductive terminal located on the internal thread portion and a second conductive terminal located at a bottom thereof. The first and second conductive terminals of the bases are electrically connected through at least one conductive wire to form a lamp string. Each base is encased by an outer shell which includes at least one insulation section to cover the base and the conductive wire, and a mask section at the junction of the base and the lighting bulb to tightly couple with the lighting bulb, thereby can prevent liquid from flowing through the base and the conductive wire or through a gap between the base and the lighting bulb, thereby can enhance watertight efficacy. | 03-12-2015 |
Shiao-Cheng Chuang, Hsinchu City TW
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20090239809 | Process For Preparing Peptide Products For Promoting Cholecystokinin Secretion And Use Of The Peptide Products - A process for producing a peptide product having cholecystokinin secretion promoting effect, said process comprising hydrolyzing soybean residues with one or more proteases so that the peptide product having cholecystokinin secretion promoting effect is obtained. Also disclosed is the composition containing the peptide product and the use thereof. | 09-24-2009 |
20120270813 | Process for Preparing Peptide Products for Promoting Cholecystokinin Secretion and Use of the Peptide Products - A process for producing a peptide product having cholecystokinin secretion promoting effect, said process comprising hydrolyzing soybean residues with one or more proteases so that the peptide product having cholecystokinin secretion promoting effect is obtained. Also disclosed is the composition containing the peptide product and the use thereof. | 10-25-2012 |
20130323360 | PROBIOTICS-CONTAINING SOYBEAN OLIGOSACCHARIDE PRODUCT AND PREPARATION THEREOF - Provided is a soybean oligosaccharide product containing acidic soluble saccharides of soybean and probiotics, which at least include fructose, glucose, sucrose, raffinose, and stachyose, with a percentage of the combined weight of raffinose and stachyose being at least 46%, a weight percentage of fructose being not greater than 8.5%, and a weight percentage of glucose being not greater than 1.0%, based on the total weight of fructose, glucose, sucrose, raffinose, and stachyose. The soybean oligosaccharide product is prepared by extracting a soybean raw material with water under a pH of 3-6 and at a temperature of 50-70° C. to obtain an extract containing acidic soluble saccharides of soybean, and inoculating and fermenting the extract with probiotics that are able to decompose monosaccharides and disaccharides, but substantially not able to decompose trisaccharides or tetrasaccharides. | 12-05-2013 |
20140066361 | PEPTIDES AND USE THEREOF IN THE INHIBITION OF ANGIOTENSIN CONVERTING ENZYME - Peptides useful as angiotensin converting enzyme inhibitors are provided. Also provided are compositions comprising one or more of the peptides and methods for preventing, treating and/or diminishing one or more syndromes associated with angiotensin converting enzyme by using the peptides. | 03-06-2014 |
Shih-Chang Chuang, Hsinchu City TW
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20110144467 | FLEXIBLE 3D MICROPROBE STRUCTURE - The present invention discloses a flexible 3D microprobe structure, which comprises at least one probe, a base and a hinge portion. The probe is connected to the base via the hinge portion. The probe forms a bend angle with respect to a normal of the base by attracting the probe through an electrostatic force to make the hinge portion bend with respect to the base, and thus to form a 3D structure having the bend angle. The probe, the base and the hinge portion are made of a flexible polymeric material to reduce the inflammation response of creatures. Further, a fixing element is used to enhance the structural strength of the flexible 3D microprobe structure. | 06-16-2011 |
Shih-Ching Chuang, Hsinchu City TW
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20120305919 | FULLERENE DERIVATIVES AND OPTOELECTRONIC DEVICES UTILIZING THE SAME - Disclosed is a fullerene derivative having a formula of F-Cy, wherein F is an open-cage fullerene, and Cy is a chalcogenyl group. The fullerene derivative can be applied to hydrogen storage material and an optoelectronic device such as an organic light emitting diode (OLED), a solar cell, or an organic thin film transistor (TFT). | 12-06-2012 |
Shih-Fang Chuang, Hsinchu City TW
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20130128061 | IMAGE PROCESSING APPARATUS AND PROCESSING METHOD THEREOF - An image processing apparatus and a processing method thereof are provided. The image processing apparatus includes an image capturing module, an image separation module, an image stabilization module, a temporal noise reduction module, and a spatial noise reduction module. The image capturing module captures a plurality of Bayer pattern images. The image separation module decreases the Bayer pattern images in size and transforms them into a plurality of YCbCr format images. The image stabilization module receives Y channel images of the YCbCr format images and the Bayer pattern images to perform motion estimation, to produce a plurality of global motion vectors (GMVs). The temporal noise reduction module performs temporal blending process on the Bayer pattern images according to the GMVs, to produce first noise reduction images. The spatial noise reduction module performs 2-dimensional spatial noise reduction on the first noise reduction images to produce second noise reduction images. | 05-23-2013 |
Tien-Shao Chuang, Hsinchu City TW
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20150096612 | BACK-CONTACT SOLAR CELL AND MANUFACTURING METHOD THEREOF - A back-contact solar cell and manufacturing method thereof includes steps of providing a substrate, forming a first conductive doping region and a second conductive doping region on the substrate, forming a passivation layer on the substrate to cover the first conductive doping region and the second conductive doping region, distantly disposing a plurality of first electrode paste clusters on the passivation layer, in which each first electrode paste cluster corresponds to the first conductive doping region and the second conductive doping region and includes a metal component and a glass component, enclosing the first electrode paste cluster by a plurality of second electrode pastes, and heating at least the first electrode paste clusters to an predetermined temperature so that the metal component, the metal component and the passivation layer contacted by the first electrode paste clusters forms a plurality of contacting regions. | 04-09-2015 |
Tzu-Shien Chuang, Hsinchu City TW
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20140139154 | CURRENT VECTOR CONTROLLED SYNCHRONOUS RELUCTANCE MOTOR AND CONTROL METHOD THEREOF - A current vector controlled synchronous reluctance motor and control method thereof, wherein the motor has a coil on each of the teeth. The coils form a U-phase winding, a V-phase winding and a W-phase winding. The phase windings receive a balanced three-phase current vector to induce closed magnetic field lines, such that the coils induce same magnetic poles adjacent to the rotor unit. Two short magnetic routes are formed along three adjacent teeth and the rotor unit. The efficiency of the reluctance motor is high. | 05-22-2014 |
Tzu-Sou Chuang, Hsinchu City TW
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20090275278 | ULTRA-PURE AIR SYSTEM FOR NANO WAFER ENVIRONMENT - In one embodiment, an air filtration system includes a first ventilation path connected between at least one external air supply and a clean room. The first ventilation path is configured to direct air from the at least one external air supply to the clean room. A second ventilation path is connected to the clean room. The second ventilation path is configured to recirculate air in the clean room. A third ventilation path, separate from the first path, is connected between the at least one external air supply and a tool environment disposed within the clean room. The third ventilation path includes an ultra-pure air filtration unit disposed between the outdoor air supply and the tool environment. The ultra-pure air filtration unit includes a compressor and a dryer. | 11-05-2009 |
20130153285 | MAGNETIC FIELD SHIELDING RAISED FLOOR PANEL - A magnetic field shielding raised floor panel having a plurality of grain-oriented electrical steel (GOES) sections. The orientation of each GOES section is parallel to a top surface of the section. The plurality of GOES sections can include sidewall and lip portions. The plurality of GOES sections can be perforated to permit air flow through the GOES section. Openings in adjacent perforated GOES sections do not substantially overlap. | 06-20-2013 |
20140065719 | DETECTION METHOD FOR SUBSTANCE AND SYSTEM THEREOF - A detection method for a substance and a system thereof are provided. The detection method for a substance contained in a sample includes providing a reagent in reaction with the substance to form a chelate; and pressurizing the substance to accumulate the chelate. | 03-06-2014 |
20140095083 | Method Of Identifying Airborne Molecular Contamination Source - The present disclosure provides a method of identifying an airborne molecular contamination (AMC) leaking source in a fab. The method includes distributing a sensor in the fab, executing a forward computational fluid dynamics (CFD) simulation of an air flow in the fab, setting an inversed modeling of the forward CFD simulation of the air flow in the fab, building up a database of a spatial response probability distribution matrix of the sensor using an AMC measurement data in the fab, and identifying the AMC leaking source using the database of the spatial response probability distribution matrix of the sensor. | 04-03-2014 |
20150182902 | MECHANISMS FOR AIR TREATMENT SYSTEM AND AIR TREATMENT METHOD - Embodiments of mechanisms of an air treatment system are provided. The air treatment system includes a heating tank having a heating chamber containing air. The air includes gas, water vapor, a number of contaminants floating thereon. The air treatment system further includes a cooling tank having a first cooling chamber receiving the air from the heating chamber. Some of the water vapor in the first cooling tank condenses to a number of droplets, and some of the contaminants are mixed with into the droplets. | 07-02-2015 |
20160061695 | METHOD AND APPARATUS FOR INSPECTING PROCESS SOLUTION, AND SAMPLE PREPARATION APPARATUS IN INSPECTION - A method for inspecting a process solution is provided. In this method, a process solution is disposed on a surface of a substrate. A liquid of the process solution is removed to form an inspection sample by a spinning method. The surface of the substrate of the inspection sample is inspected by the surface inspection device to identify whether a residue of the process solution is left on the surface of the substrate after removing the liquid of the process solution. Further, an apparatus for inspecting a process solution and a sample preparation apparatus in inspection are also provided herein. | 03-03-2016 |
Wei-Shun Chuang, Hsinchu City TW
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20120137264 | MULTIPLE LEVEL SPINE ROUTING - Multiple level spine routing is disclosed. In some embodiments, in response to receiving a specification of a net comprising a set of pins, a first wire for routing the net is generated, the set of pins comprising the net is partitioned into one or more groups based at least in part on a cost function, a second wire that connects to the first wire is generated for each group of the net, and a third wire that connects each pin to the second wire of its group is generated for each pin of each group of the net. | 05-31-2012 |
20120137265 | MULTIPLE LEVEL SPINE ROUTING - Multiple level spine routing is disclosed. In some embodiments, in response to receiving a specification of a plurality of nets and a specification of a set of routing tracks available for main spines, a main spine routing track is assigned to each of the plurality of nets based at least in part on a cost function and main spine wires are generated on the assigned main spine routing tracks for each of the plurality of nets. | 05-31-2012 |
20140033157 | Multiple Level Spine Routing - A computer implemented method for routing a net includes generating, using one or more computer systems, a first wire associated with the net in accordance with data associated with the net including a multitude of pins and partitioning, using the one or more computer systems, the multitude of pins into at least a first group of pins in accordance with a first cost function. The method further includes connecting, using the one or more computer systems, a second wire associated with the first group of pins to the first wire, and connecting, using the one or more computer systems, a third wire from a pin of the first group of pins to the second wire. | 01-30-2014 |
20140033158 | Multiple Level Spine Routing - A computer implemented method for routing a net includes selecting, using one or more computer systems, a first spine routing track from a first multitude of routing tracks in accordance with a first cost function, and further in accordance with data associated with the net and the first multitude of routing tracks. The method further includes generating, using one or more computer systems, a first spine wire on the selected first spine routing track. | 01-30-2014 |
Wen-Pin Chuang, Hsinchu City TW
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20150183948 | BIO-POLYOL COMPOSITION AND BIO-POLYURETHANE FOAM MATERIAL - A bio-polyol composition and a bio-polyurethane foam material are provided. By using the modifier and applying the dispersing and grinding process, the modified lignin is uniformly dispersed in the polyol solution and a bio-polyol composition is obtained. The obtained bio-polyol composition may be used to prepare the bio-polyurethane foam material with a high lignin content, a high compression strength and superior flame-resistance. | 07-02-2015 |
20160102170 | LIGNIN-BASED BIOMASS EPOXY RESIN, METHOD FOR MANUFACTURING THE SAME, AND COMPOSITIONS INCLUDING THE SAME - A method of forming a lignin-based biomass epoxy resin is provided, which includes: (a) mixing a lignin, an acid anhydride compound, and a solvent to react for forming a first intermediate product, (b) reacting the first intermediate compound with a first polyol to form a second intermediate compound, and (c) reacting the second intermediate compound with an epoxy compound to form a lignin-based biomass epoxy resin. | 04-14-2016 |
Ya-Hsuan Chuang, Hsinchu City TW
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20120148449 | ELECTRIC CONDUCTIVITY-BASED BIOSENSOR - An electric conductivity-based biosensor electrochemically detects the concentration of tested objects via measuring impedance or capacitance variation of the tested objects. The biosensor comprises a substrate, two electric-conduction electrodes arranged on the substrate, an antibody adhesion layer arranged on a region of the substrate and a plurality of antibodies arranged on the antibody adhesion layer. The antibody adhesion layer is between the two electric-conduction electrodes. The antibodies are connected with a plurality of tested objects. The tested objects connected with the antibodies form an electric-conduction group contacting the two electric-conduction electrodes. The concentration of the tested objects can be provided via measuring impedance or capacitance between the two electric-conduction electrodes. | 06-14-2012 |
Yao-Chun Chuang, Hsinchu City TW
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20140117532 | Bump Interconnection Ratio for Robust CPI Window - The disclosure is directed to a device and method for manufacture thereof. The device includes a first workpiece bonded to a second workpiece by a bump interconnection structure. The bump interconnection structure allows for optimized packaging assembly yield and bond integrity. | 05-01-2014 |
Ying-Ting Chuang, Hsinchu City TW
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20110296073 | TIME ALIGNING CIRCUIT AND TIME ALIGNING METHOD FOR ALIGNING DATA TRANSMISSION TIMING OF A PLURALITY OF LANES - A time aligning circuit includes a plurality of buffers, a plurality of delay selectors, a plurality of adjustment symbol generators, and a controller. Each buffer receives an ordered set on a corresponding lane. Each delay selector delays an output of the ordered set of the corresponding buffer. Each adjustment symbol generator outputs an adjustment symbol or the output received from the corresponding delay selector according to an adjustment control signal. When an initial symbol of a designated delay selector is detected but initial symbols of other delay selectors are not received yet, the controller generates the delay control signal to the designated delay selector and generates the adjustment control signal to control a designated adjustment symbol generator corresponding to the designated delay selector in order to output one adjustment symbol until initial signals of all delay selectors are detected. | 12-01-2011 |
Yuan-Cheng Chuang, Hsinchu City TW
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20150156288 | PARSER FOR PARSING HEADER IN PACKET AND RELATED PACKET PROCESSING APPARATUS - A parser is used for parsing a header in a packet. The parser includes a plurality of horizontal field selectors, a plurality of comparators, and a content addressable memory (CAM) based device. Each of the horizontal field selectors is configured to select a first bit group. The comparators are coupled to the horizontal field selectors, respectively. Each of the comparators is configured to compare a first bit group selected by a corresponding horizontal field selector with a designated value to generate a comparison result. The CAM based device is configured to receive a plurality of comparison results generated from the comparators, and use the comparison results as a first input search data. | 06-04-2015 |
Yu-Chun Chuang, Hsinchu City TW
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20080204293 | MULTI-CHANNEL DISPLAY DRIVER CIRCUIT INCORPORATING MODIFIED D/A CONVERTERS - A multi-channel display driver circuit incorporating modified D/A converters has a plurality of digital comparators connected to a number generator. Each digital comparator has an output, a digital data input and a reference input. The reference inputs of all digital comparators are connected to the number generator and the outputs are respectively connected to corresponding data channels of a display. By the proposed technique, each digital comparator obtains a unique non-sequence reference signal, and then compares it with the input digital data signal. Since the non-sequential signals are input to the reference input of the digital comparator, the overshoot distortion, the harmonic distortion and the electromagnetic interference problems are prevented. Therefore, the precise imaging can be obtained with this signal modulation technique in small circuit size. | 08-28-2008 |
Yueh-Lin Chuang, Hsinchu City TW
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20120128059 | Method of adaptive motion estimation in search windows for video coding - The invention discloses a method of adaptive motion estimation in search windows for video coding, which uses adjacent MBs to predict the range of search window, storing MVs of adjacent MBs respectively for each reference frame, then using MVs of three adjacent MBs to delimit the scope of search window on the same reference frame. It could derive the most similar MB from the scope of search window than the current MB. | 05-24-2012 |
Yu-Hsing Chuang, Hsinchu City TW
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20140375696 | IMAGE DISPLAY APPARATUS AND BACKLIGHT ADJUSTING METHOD THEREOF - An image display apparatus and a backlight adjusting method are provided. The image display apparatus has a backlight module. The image display apparatus includes an ambient light sensor, an image content analyzer and a backlight controller. The ambient light sensor detects a luminance of ambient light. The image content analyzer receives an image data. The backlight controller sets a backlight basic value according to the luminance of ambient light, and sets a backlight adjusting ratio according to the image data and the luminance of ambient light. The backlight controller further sets a luminance of the backlight module according to the backlight basic value and the backlight adjusting ratio. | 12-25-2014 |
20150340008 | DISPLAY APPARATUS AND METHOD AND COLOR TEMPERATURE COMPENSATION APPARATUS THEREOF - A color temperature compensation apparatus includes a compensation table and a controller. The compensation table records a relationship between a plurality of compensation values and each of a plurality of gray-levels, wherein the relationship is established based on a plurality of color temperature compensation curves. The controller is coupled to the compensation table, and generates a plurality of compensation values by referring to the compensation table according to a gray-level of each of a plurality of image data and a reference color temperature. The controller further calculates each of a plurality of compensated image data according to the compensation values, wherein the color temperature compensation curves respectively correspond to a plurality of color temperatures. | 11-26-2015 |
Yu-Min Chuang, Hsinchu City TW
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20080292009 | MULTIPLE-INPUT-MULTIPLE-OUTPUT WIRELESS TRANSMISSION SYSTEM AND TRANSMISSION METHOD THEREOF - The present invention relates to a multiple-input-multiple-output (MIMO) wireless transmission system and a transmission method thereof. A wireless transmitting system thereof receives encoded data via a first processing unit, which processes the encoded data and outputs the encoded data to a plurality of modulation units for modulating the encoded data to produce a plurality of modulated data. A plurality of first conversion units converts the plurality of modulated data to a plurality of transmitting signals. A plurality of radio-frequency (RF) circuits receives the plurality of transmitting signals and transmits RF signals according to the frequency-hopping sequence of a piconet. A plurality of receiving processing units of a wireless receiving system according to the present invention receives the RF signals, respectively, according to the frequency-hopping sequence of the piconet and transmits to a plurality of second conversion units for converting the RF signals to received data. A switching circuit switches the received data according to the frequency-hopping sequence of the piconet. A plurality of demodulation units demodulates the switched received data to produce demodulated data. A second processing unit received the demodulated data, and processes the demodulated data to output demodulated data. A decoding unit decodes the demodulated data output by the second processing unit to produce output data. | 11-27-2008 |
Yun-Chen Chuang, Hsinchu City TW
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20150042238 | DRIVING METHOD OF MULTI-COMMON ELECTRODES AND DISPLAY DEVICE - A driving method of multi-common electrodes and a display device are provided. The driving method includes following steps: providing a plurality of common voltages, in which the common voltages include a first common voltage and a second common voltage, and the first common voltage is different from the second common voltage. During a first period, the first common voltage is set to a first voltage level to drive a first common electrode of a first pixel region in the display panel, and the second common voltage is set to a third voltage level to drive a second common electrode of a second pixel region in the display panel. During a second period, the first common voltage is set to a second voltage level to drive the first common electrode, and the second common voltage is set to a fourth voltage level to drive the second common electrode. | 02-12-2015 |
Yung-Chun Chuang, Hsinchu City TW
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20130129744 | PLASMINOGEN-ACTIVATING ANTIBODY, USE AND PRODUCING METHOD THEREOF AND AGENT INCLUDING THE SAME - An antibody for activating plasminogen is provided. The antibody is produced from a hybridoma cell line deposited on Nov. 24, 2011 under accession number BCRC 960433 at Food Industry Research and Development Institute, 331 Shih-Pin Road, Hsinchu 300, Taiwan. The uses and producing method of the antibody, and an agent including the antibody used for treating stroke, myocardial infarction or syndromes cause by thrombus are also disclosed. | 05-23-2013 |
Yung-Hsu Chuang, Hsinchu City TW
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20140145749 | METHOD AND APPARATUS OF RFID TAG CONTACTLESS TESTING - A semiconductor wafer includes a plurality of dies. Each of the plurality of dies includes a radio frequency identification (RFID) tag circuit and a coil. The RFID tag circuit includes a tag core, an RF front-end circuit, an ID decoder, a comparator and conductive line for a unique ID. The RF front-end circuit is configured to receive electromagnetic signals through the coil in each of the plurality of dies and to convert the received electromagnetic signals into commands. The ID decoder is configured to receive the commands and to generate an expect ID. The comparator is configured to compare the unique ID with the expect ID to generate a comparison result. The comparison result is arranged to decide if the tag core is configured to receive commands. | 05-29-2014 |
20140184296 | MCML RETENTION FLIP-FLOP/LATCH FOR LOW POWER APPLICATIONS - The present disclosure relates to a device and method to reduce the dynamic/static power consumption of an MCML logic device. In order to retain register contents during power off mode, an MCML retention latch and flip-flop are disclosed. Retention Latch circuits in MCML architecture are used to retain critical register contents during power off mode, wherein combination logic including clock buffers on the clock tree paths are powered off to reduce dynamic/static power consumption. The MCML retention flip-flop comprises a master latch and a slave latch, wherein a power switch is added to the master latch to power the master latch off during power off mode. The slave latch includes pull-down circuits that remain active to enable the slave latch to retain data at a proper voltage level during power off mode. Other devices and methods are also disclosed. | 07-03-2014 |
Yung-Hui Chuang, Hsinchu City TW
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20100163105 | SOLAR CELL PACKAGE TYPE WITH SURFACE MOUNT TECHNOLOGY STRUCTURE - A solar cell package type with surface mount technology structure, comprising: a solar cell having a first electric terminal at the bottom thereof and a second electric terminal at the top thereof; at least a connection electric terminal capped at both sides of the solar cell in such a way that the top of the connection electric terminal is connected to the second electric terminal; and at least an insulation layer capped at both sides and partially placed at the bottom of the solar cell in such a way that it is interposed between the electric terminal and the solar cell for avoiding the short current and the water penetration. In this way, this package in accordance with the invention tends to increase the array density of the solar cells on the substrate and to minimize the manufacturing cost. | 07-01-2010 |
Yung-Sheng Chuang, Hsinchu City TW
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20110122086 | TOUCH DISPLAY MODULE AND TOUCH DISPLAY APPARATUS COMPRISING THE SAME - A touch display apparatus comprising a controller and a touch display module, electrically connected to the controller, are provided. The touch display module comprises a display panel and a sensor assembly. The display panel includes a display surface and a connection surface opposite the display surface, and the sensor assembly is disposed on the connection surface and electrically connected to the controller. The sensor assembly comprises a first sensing layer and a second sensing layer, with a first sheet conducting layer and a second sheet conducting layer, respectively. When the display surface is touched, the first sheet conducting layer and the second sheet conducting layer are electrically connected to generate a touch signal. Thereby, the controller may detect a touch position according to the touch signal. | 05-26-2011 |