Chua, MY
Chen Seong Chua, Melaka MY
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20130087901 | DESIGN FOR EXPOSED DIE PACKAGE - In one aspect of the present invention, an integrated circuit package with an exposed die and a protective housing will be described. The housing extends beyond the exposed back surface of the die to help protect it from damage. The integrated circuit package includes a lead frame and an integrated circuit die. The integrated circuit die is electrically and physically attached to the lead frame. The housing encapsulates the lead frame and the die. The housing also includes a recessed region at the bottom of the package where the back surface of the die is exposed. There is a protruding protective structure at the bottom of the package that helps to protect the die and prevent its exposed back surface from coming in contact with an external object. | 04-11-2013 |
20130127029 | TWO LEVEL LEADFRAME WITH UPSET BALL BONDING SURFACE AND DEVICE PACKAGE - A leadframe, device package, and mode of construction configured to attain a thin profile and improved thermal performance. Leadframes of this invention include a raised die attachment pad arrange above distal ends of leadframe leads. A package will further include a die electrically coupled with an underside surface of the raised die attachment pad, in one example, using ball bonds, the whole sealed in an encapsulant that exposed a bottom portion of the die and a portion of a lead. Two leadframe stacks of such packages are also disclosed as are methods of manufacture. | 05-23-2013 |
Gian Ping (vincent) Chua, Kedah MY
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20130001114 | UNIVERSAL DISK SHIPPER - System, methods, and components includes an improved universal disk container for use in transporting, storing and processing data storage disks or other disk-shaped articles; a disk shipping system and method for shipping disks that allows stocking a minimal number of components while still allowing packaging and shipment of different thickness of disks and different capacities of disks in a container, and components that present universality while still minimizing particulate generation, disk damage and providing ease of assembly. A universal disk cassette with slots having a narrowed lower portion configured for handling different disks of the same diameter but different thicknesses while preventing disk to disk contact when the disks are tilted. A universal top cover configured for cassettes loaded with different thicknesses of disks, i.e., a cassette loaded with 0.025 inch disks, or the same cassette loaded with 0.050 inch disks. Also the universal top cover configured for use on different capacity disk cassettes, that is a 65 mm disk cassette with a 25 capacity or a 65 mm cassette with a 35 capacity. The universal top cover can readily accommodate disks that are tilted in the cassette, and with vacuum bagging, more securely fix the disks in place in the container. | 01-03-2013 |
Hong Da Chua, Batu Pahat MY
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20160036483 | INTERFACE SYSTEM FOR COMMUNICATION DEVICES - An interface system for communication devices comprises a radio having a through-hole opening from a front surface to a back surface, the through-hole forming a coaxial connector shaped interface for coupling to an accessory. The coaxial connector shaped interface allows for a plurality of different interchangeable electronic accessories to interface to the radio. | 02-04-2016 |
Hui N. Chua, Kuala Lumpur MY
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20090276716 | Content Adaptation - A web page content adaptation process and system which prioritizes requested web page content for adaptation in accordance with a user's level of interest in the web page content is described. The requested web page content is grouped to form multiple content clusters and a priority value is assigned to each of the content clusters based on the user's browser history. The requested web page content is then adapted in order of the priority value assigned to each of the content clusters to provide a useful version of the original web page content. | 11-05-2009 |
Huina Chua, Kuala Lumpur MY
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20080201266 | Communications System - A method for controlling payment in a communications system including the steps of providing a service accessing a service provider from the or one user device, selecting a product for purchase from the service provider, the service agent receiving a request for payment from the service provider via a payment operator and the service agent issuing a payment authorisation to a payment provider via the payment operator. The service agent is installable in a variety of user devices and provides a uniform interface to the payment system from a plurality of the user devices. The service agent may also provide a uniform interface to an ordering system from a plurality of the user devices. | 08-21-2008 |
Hui Na Chua, Kuala Lumpur MY
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20110029558 | DYNAMIC SERVICE GENERATION IN IMS NETWORK - A service generation system in a communications network and a method for responding to a service request are provided. The system includes a processor ( | 02-03-2011 |
Janet Bee Yin Chua, Penang MY
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20090122515 | USING MULTIPLE TYPES OF PHOSPHOR IN COMBINATION WITH A LIGHT EMITTING DEVICE - Light is emitted from a light emitting device. The light emitted from the light emitting device is combined with light from a first type of phosphor and a second type of phosphor. The first type of phosphor and the second type of phosphor are within an epoxy placed over the light emitting device. The first type of phosphor, when excited, emits light of a first color. The second type of phosphor, when excited, emits light of a second color. The first color and the second color are different. | 05-14-2009 |
Kar Keng Chua, Penang MY
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20080258772 | CLOCK SIGNAL NETWORKS FOR STRUCTURED ASIC DEVICES - Clock distribution circuitry for a structured ASIC device includes a deterministic portion and configurable portions. The deterministic portion employs a predetermined arrangement of conductor segments and buffers for distributing a clock signal to a plurality of predetermined locations on the device. From each predetermined location, an associated configurable portion of the clock distribution circuitry distributes the clock signal to any clock utilization circuitry needing that clock signal in a predetermined area of the structured ASIC that is served from that predetermined location. | 10-23-2008 |
20110292711 | DATA ENCODING SCHEME TO REDUCE SENSE CURRENT - Techniques for encoding and decoding fuse data to reduce sense current are disclosed. An embodiment to encode fuse sense data includes inverting each of the bits of the fuse data and using an individual fuse as a flag bit to record the data inversion. The states of the respective fuses may represent different logic states. A fuse may be blown to indicate a logic one and likewise, an unblown fuse may indicate a logic zero. A blown fuse and an unblown fuse may have different current consumption. An unblown fuse may consume more sensing current compared to a blown fuse. Another embodiment to decode the encoded fuse data includes embedded logic circuits and a separate fuse as a flag bit. Encoding and decoding fuse data may reduce fuse sensing current. | 12-01-2011 |
20140077839 | CLOCK SIGNAL NETWORKS FOR STRUCTURED ASIC DEVICES - Clock, distribution circuitry for a structured ASIC device includes a deterministic portion, and configurable portions. The deterministic portion employs a predetermined arrangement of conductor segments and buffers for distributing a clock signal to a plurality of predetermined locations on the device. From each predetermined location, an associated configurable portion of the clock distribution circuitry distributes the clock signal to any clock utilization circuitry needing that clock signal in a predetermined area of the structured ASIC that is served, from that predetermined, location. | 03-20-2014 |
Kar Keng Chua, Bayan Lepas MY
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20110084727 | APPLICATION-SPECIFIC INTEGRATED CIRCUIT EQUIVALENTS OF PROGRAMMABLE LOGIC AND ASSOCIATED METHODS - Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA logic element (“LE”). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs. | 04-14-2011 |
20130002295 | APPLICATION-SPECIFIC INTEGRATED CIRCUIT EQUIVALENTS OF PROGRAMMABLE LOGIC AND ASSOCIATED METHODS - Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA logic element (“LE”). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs. | 01-03-2013 |
20130314122 | APPLICATION-SPECIFIC INTEGRATED CIRCUIT EQUIVALENTS OF PROGRAMMABLE LOGIC AND ASSOCIATED METHODS - Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA logic element (“LE”). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs. | 11-28-2013 |
Kaw Yan Chua, Kulai MY
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20110318274 | VARIANT OF MITE ALLERGEN AND USES THEREOF - The present invention relates to a new variant of the group 2 allergen from the house dust mite | 12-29-2011 |
Pei Shan Chua, Sarawak MY
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20120161276 | SEMICONDUCTOR DEVICE COMPRISING AN ISOLATION TRENCH INCLUDING SEMICONDUCTOR ISLANDS - The present invention provides semiconductor devices and methods for fabricating the same, in which superior dielectric termination of drift regions is accomplished by a plurality of intersecting trenches with intermediate semiconductor islands. Thus, a deep trench arrangement can be achieved without being restricted by the overall width of the isolation structure. | 06-28-2012 |
Poh Huay Chua, Selangor MY
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20110127309 | PET CARRIER - A pet carrier ( | 06-02-2011 |
Seng Yee Chua, Kuala Lumpur MY
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20080231326 | SIGNAL CONDITIONING FOR AN OPTICAL ENCODER - An encoder with signal conditioning of an emitter drive signal is described. In one embodiment, the encoder includes a peak comparator, a pulse generator, a threshold comparator, and digital circuitry. The peak comparator outputs a peak comparator signal based on a comparison of an input sinusoidal signal stored at a first time with the input sinusoidal signal stored at a second time. The pulse generator determines a peak of the input sinusoidal signal based on the peak comparator signal. The threshold comparator compares a differential signal amplitude with a differential signal amplitude window at approximately the peak of the input sinusoidal signal. The differential signal amplitude is associated with the input sinusoidal signal. The digital circuitry generates an emitter modification signal in response to a determination that the differential signal amplitude is outside of the differential signal amplitude window. | 09-25-2008 |
Sui Kwang Chua, Klang Selangor Darul Ehsan MY
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20110074160 | WAVE ENERGY CONVERSION PLANT - The present invention provides a structure driven by floats placed in a body of water such as a sea, an ocean or the like for converting wave energy into electricity. The structure comprises a floating body to float and stabilize the structure in the water wherein a platform is provided to house and hold energy conversion systems and mechanisms. The mechanisms include a plurality of pontoons that moves with the waves. | 03-31-2011 |