Patent application number | Description | Published |
20080198296 | LIQUID CRYSTAL DISPLAY DEVICE, BACKLIGHT MODULE AND FABRICATION METHOD THEREOF - The invention provides a liquid crystal display device, backlight module and method for fabricating the same. The backlight module comprises a frame; a plurality of light-emitting diodes disposed on a bottom surface of the frame; and a mixing light plate disposed over the light-emitting diodes. The backlight module further comprises a diffusion plate disposed on the mixing light plate and a reflective layer formed on an inner sidewall and the bottom surface of the frame. The backlight module has a high luminous uniformity and efficiency by the mixing light plate. | 08-21-2008 |
20090311774 | BIOASSAY SYSTEM INCLUDING OPTICAL DETECTION APPARATUSES, AND METHOD FOR DETECTING BIOMOLECULES - A bioassay system is disclosed. The bioassay system may include a plurality of optical detection apparatuses, each of which includes a substrate having a light detector, and a linker site formed over the light detector, the linker site being treated to affix the biomolecule to the linker site. The linker site is proximate to the light detector and is spaced apart from the light detector by a distance of less than or equal to 100 micrometers. The light detector collects light emitted from the biomolecule within a solid angle of greater than or equal to 0.8 SI steridian. The optical detection apparatus may further include an excitation light source formed over the substrate so as to provide a light source for exciting a fluorophore attached to the biomolecule. | 12-17-2009 |
20100165451 | OPTICAL DEFLECTOR AND OPTICAL DEFLECTING BOARD - An optical deflector includes a substrate, an electrode layer on the substrate, an insulating layer at a predetermined peripheral region on the electrode layer, exposing the central region of the electrode layer. First electrode sandwiched wall is on the insulating layer. Second electrode sandwiched wall is on the insulating layer corresponding to the first electrode sandwiched wall. A pair of insulating walls is between the first electrode sandwiched wall and the second electrode sandwiched wall in enclosing to form an inner space. An outer wall encloses the pair of insulating layers, the first and the second electrode sandwiched walls at outside. A cap layer covers on the outer wall. A first liquid is filled into the inner space in contact with the electrode layer. A second liquid is filled into the inner spacer without solving to each other and forms a liquid interface. | 07-01-2010 |
20110223590 | SINGLE-MOLECULE DETECTION SYSTEM AND METHODS - Embodiments encompass a single-molecule detection system and methods of using the detection system to detect an object. Further, embodiments encompass a detection system comprising a movable light coupler, a waveguide, and a light detector. Embodiments further encompass methods of single-molecule detection, including methods of single-molecule nucleic acid sequencing. | 09-15-2011 |
20110306039 | Apparatus for single-molecule detection - An apparatus for detecting an object capable of emitting light. The apparatus comprises a light source and a waveguide. The waveguide comprises a core layer and a first cladding layer. At least one nanowell is formed in at least the first cladding layer. The apparatus further comprises a light detector. The light detector can detect a light emitted from a single molecule object contained in the at least one nanowell. | 12-15-2011 |
20110306143 | Apparatus for single-molecule detection - An apparatus for detecting an object capable of emitting light. The apparatus includes a light source and a waveguide. The waveguide includes a core layer and a first cladding layer. At least one nanowell is formed in at least the first cladding layer. The apparatus further includes a light detector. The light detector can detect a light emitted from a single molecule object contained in the at least one nanowell. | 12-15-2011 |
20120262553 | DEPTH IMAGE ACQUIRING DEVICE, SYSTEM AND METHOD - A depth image acquiring device is provided, which includes at least one projecting device and at least one image sensing device. The projecting device projects a projection pattern to an object. The image sensing device senses a real image. In addition, the projecting device also serves as a virtual image sensing device. The depth image acquiring device generates a disparity image by matching three sets of dual-images formed by two real images and one virtual image, and generates a depth image according to the disparity image. In addition, the depth image acquiring device also generates a depth image by matching two real images, or a virtual image and a real image without verification. | 10-18-2012 |
20120277556 | APPARATUS FOR NON-INVASIVE BLOOD GLUCOSE MONITORING - An apparatus for non-invasive blood glucose monitoring includes a light source for generating at least one ray of light, a beam splitter with a focusing function leads the light into an eyeball and focuses on the eyeball, a set of photo detectors for measuring optical rotatory distribution (ORD) information and absorption energy information of the reflected light reflected from the eyeball and transmitted through the first beam splitter to the set of photo detectors, and a processing unit. The processing unit receives and processes the ORD information and the absorption energy information to obtain an ORD difference and an absorption energy difference resulting from the light emitted from the light source and the reflected light transmitted to the set of photo detectors, and analyzes the ORD difference and the absorption energy difference to obtain a glucose information to read the blood glucose information. | 11-01-2012 |
20120277557 | METHOD FOR NON-INVASIVE BLOOD GLUCOSE MONITORING AND METHOD FOR ANALYSING BIOLOGICAL MOLECULE - A method for non-invasive blood glucose monitoring includes the following steps. At least one ray of light is emitted from at least one light source. The light emitted from the light source is leaded into an eyeball and focused on the eyeball through a first beam splitter. The reflected light reflected from the eyeball is transmitted through the first beam splitter to a set of photo detectors. Optical rotatory distribution (ORD) information and absorption energy information of the reflected light transmitted to the set of photo detectors are measured. ORD difference and absorption energy difference resulting from the light emitted from the light source and the reflected light transmitted to the set of photo detectors are obtained. Glucose information is obtained by analyzing the ORD difference and the absorption energy difference, and since glucose information has a corresponding relationship with blood glucose information, blood glucose information may be read. | 11-01-2012 |
20130320190 | LIGHT SOURCE DEVICE - A light source device including at least one light source, an optical module, a diffractive optical element, and a shielding component is provided. The at least one light source emits at least one light beam, and the light beam has a wavelength range. The optical module is disposed on a transmission path of the light beam to provide a plurality of optical surfaces. The optical surfaces respectively have a plurality of different inclination angles, so as to transmit at least a portion of the light beam having at least a predefined wavelength to a plurality of different directions. The diffractive optical element is disposed on the transmission path of the light beam, so as to diffract the light beam. The shielding component has an outlet. A portion of the diffracted light beam passes through the outlet to the outside. | 12-05-2013 |
20130324722 | PHOSPHOR - A phosphor is provided, which has a chemical structure represented by General Formula I: | 12-05-2013 |
20140051955 | DETECTING DEVICE - A detecting device includes at least one detecting module. In the detecting module, a light source unit is configured to emit a first beam and a second beam. The wavelength of the first beam is different from that of the second beam. A packaging unit is disposed on the light source unit and a light detecting unit and on transmission paths of the first beam and the second beam from the light source unit. An optical microstructure unit is disposed on the transmission paths of the first beam and the second beam. The first beam and the second beam emitted from the light source unit pass through the packaging unit to pass the optical microstructure unit to be transmitted to a biological tissue, and then pass through the optical microstructure unit to pass the packaging unit to be transmitted to the light detecting unit in sequence. | 02-20-2014 |
20140171765 | APPARATUS FOR NON-INVASIVE GLUCOSE MONITORING - An apparatus for non-invasive glucose monitoring includes a light source for emitting at least one ray of light; a first beam splitter, a set of photo detectors for measuring optical rotatory distribution (ORD) information and absorption energy information; a reference component receiving the light from the first beam splitter, and the light reflected by the reference component being transmitted to the set of photo detectors by the first beam splitter, wherein the light emitted from the light source is transmitted to the set of photo detectors by the first beam splitter and the eyeball to form a first optical path, the light emitted from the light source is transmitted to the set of photo detectors by the first beam splitter and the reference component to form a second optical path; and a processing unit receiving and processing the ORD information and the absorption energy information to obtain a glucose information. | 06-19-2014 |
20140180041 | APPARATUS FOR NON-INVASIVE GLUCOSE MONITORING - An apparatus for non-invasive glucose monitoring includes a first light source for emitting at least one ray of first light; a first beam splitter with a focusing function; a set of photo detectors for measuring optical rotatory distribution (ORD) information and absorption energy information of the first light reflected from the eyeball and transmitted through the first beam splitter to the set of photo detectors, and the first light emitted from the first light source being transmitted to the set of photo detectors by the first beam splitter and the eyeball to form an optical path; a processing unit receiving and processing the ORD information and the absorption energy information to obtain glucose information; and an eye positioning device including a second beam splitter disposed on the optical path between the first beam splitter and the eyeball and a camera for receiving image information transmitted from the second beam splitter. | 06-26-2014 |
20140367589 | Apparatus For Single-Molecule Detection - An apparatus for detecting an object capable of emitting light. The apparatus includes a light source and a waveguide. The waveguide includes a core layer and a first cladding layer. At least one nanowell is formed in at least the first cladding layer. The apparatus further includes a light detector. The light detector can detect a light emitted from a single molecule object contained in the at least one nanowell. | 12-18-2014 |
Patent application number | Description | Published |
20120086649 | CONDUCTIVE CIRCUITS FOR A TOUCH PANEL AND THE MANUFACTURING METHOD THEREOF - A manufacturing method of conductive circuits of a touch panel includes the following steps: providing a substrate with a conductive area thereon; providing at least one hard coating layer on the conductive area of the substrate; forming a plurality of grooves on the hard coating layer; forming a metal layer on the hard coating layer and in the grooves; and heating the metal layer so as to condense the metallic materials thereof in the grooves due to surface tension, thus forming a plurality of conductive circuits. | 04-12-2012 |
20120148823 | TRANSPARENT CONDUCTIVE STRUCTURE AND METHOD OF MAKING THE SAME - A transparent conductive structure includes a substrate unit and a conductive unit. The substrate unit includes at least one plastic substrate. The conductive unit includes at least one transparent conductive film and at least one nanometer conductive group formed at the same time, wherein the transparent conductive film is formed on the plastic substrate, and the nanometer conductive group includes a plurality of conductive nanowire filaments mixed or embedded in the transparent conductive film. In other words, both the transparent conductive film and the nanometer conductive group in the instant disclosure can be respectively formed by two different forming methods (such as sputtering and vaporing) at the same time, and the conductive nanowire filaments of the nanometer conductive group can be formed inside the transparent conductive film. | 06-14-2012 |
20120156458 | DIFFUSION BARRIER STRUCTURE, TRANSPARENT CONDUCTIVE STRUCTURE AND METHOD FOR MAKING THE SAME - A transparent conductive structure includes a substrate unit, a first coating unit, a diffusion barrier structure, a second coating unit, a third coating unit and a conductive unit. The substrate unit includes a plastic substrate. The first coating unit includes a first coating layer formed on the plastic substrate. The diffusion barrier structure is formed on the first coating layer. The diffusion barrier structure includes a first oxide unit having a plurality of first oxide layers and a second oxide unit having a plurality of second oxide layers. The first oxide layers and the second oxide layers are stacked on top of each other alternately. The second coating unit includes a second coating layer formed on the diffusion barrier structure. The third coating unit includes a third coating layer formed on the second coating layer. The conductive unit includes a transparent conductive film formed on the third coating layer. | 06-21-2012 |
20120273256 | TRANSPARENT CONDUCTIVE STRUCTURE APPLIED TO A TOUCH PANEL AND METHOD OF MAKING THE SAME - A transparent conductive structure applied to a touch panel includes a substrate unit, a first coating unit, a transparent conductive unit, and a second coating unit. The substrate unit includes a transparent substrate. The first coating unit includes a first coating layer formed on the top surface of the transparent substrate. The transparent conductive unit includes a transparent conductive layer formed on the top surface of the first coating layer. The transparent conductive layer includes a plurality of conductive circuits arranged to form a predetermined circuit pattern. The second coating unit includes a second coating layer formed on the top surface of the transparent conductive layer to cover the conductive circuits. The second coating layer has a touching surface formed on the top side thereof, and the touching surface allows an external object (such as user's finger, any type of touch pen, or etc.) to touch. | 11-01-2012 |
20120273262 | TRANSPARENT CONDUCTIVE STRUCTURE APPLIED TO A TOUCH PANEL AND METHOD OF MAKING THE SAME - A transparent conductive structure applied to a touch panel includes a substrate unit, a first coating unit, a transparent conductive unit, and a second coating unit. The substrate unit includes a transparent substrate. The first coating unit includes a first coating layer formed on the top surface of the transparent substrate. The transparent conductive unit includes a transparent conductive layer formed on the top surface of the first coating layer. The transparent conductive layer includes two transparent conductive films stacked on top of each other and a plurality of embedded conductive circuits formed between the two transparent conductive films and arranged to form a predetermined embedded circuit pattern. The second coating unit includes a second coating layer formed on the top surface of the transparent conductive layer. The second coating layer has a touching surface on the top side thereof for an external object to touch. | 11-01-2012 |
20120279758 | TRANSPARENT CONDUCTIVE STRUCTURE APPLIED TO A TOUCH PANEL AND METHOD OF MAKING THE SAME - A transparent conductive structure applied to a touch panel includes a substrate unit, a first coating unit, a transparent conductive unit, and a second coating unit. The substrate unit includes a transparent substrate. The first coating unit includes a first coating layer formed on the top surface of the transparent substrate. The transparent conductive unit includes a transparent conductive layer formed on the top surface of the first coating layer. The transparent conductive layer includes a plurality of embedded conductive circuits embedded therein and arranged to form a predetermined embedded circuit pattern. The second coating unit includes a second coating layer formed on the top surface of the transparent conductive layer to cover the embedded conductive circuits. The second coating layer has a touching surface formed on the top side thereof, and the touching surface allows an external object (such as user's finger or touch pen) to touch. | 11-08-2012 |
20120279759 | TRANSPARENT CONDUCTIVE STRUCTURE APPLIED TO A TOUCH PANEL AND METHOD OF MAKING THE SAME - A transparent conductive structure applied to a touch panel includes a substrate unit, a first coating unit, a transparent conductive unit, and a second coating unit. The substrate unit includes a transparent substrate. The first coating unit includes a first coating layer formed on the top surface of the transparent substrate. The transparent conductive unit includes a transparent conductive layer formed on the top surface of the first coating layer. The transparent conductive layer includes a plurality of conductive circuits arranged to form a predetermined circuit pattern. The second coating unit includes a second coating layer formed on the top surface of the transparent conductive layer. The second coating layer has a touching surface formed on the top side thereof for an external object to touch. The second coating layer is substantially formed by mixing silicon oxide, aluminum oxide, lithium oxide and Teflon. | 11-08-2012 |
20130011644 | CONDUCTIVE MULTILAYER STRUCTURE AND TOUCH PANEL HAVING THE SAME - A conductive multilayer structure includes a substrate, a transparent conductive film, a hard-coated layer and a protective layer. The substrate has opposite first and second surfaces, and has non-organic powders mixed therein. The thickness of the substrate is ranged from 100 micrometers to 125 micrometers. The transparent conductive film is formed on the first surface. The hard-coated layer is formed on the second surface. The protective layer is formed on the hard-coated layer. | 01-10-2013 |
20130021670 | CONDUCTIVE FILM - The present invention discloses a conductive film including a substrate, a hard coated layer, a first refraction layer, a second refraction layer, and a transparent conductive layer. The hard coated layer may be disposed on the substrate with the silicon-based material accounting for certain percentages of the weight thereof. Placement of the first refraction layer, the second refraction layer, and the transparent conductive layer may be arranged in a predetermined order. The transparent conductive layer may cover parts of the second refraction layer. When a light enters into the transparent conductive layer and the second refraction layer with an incident angle, the light may be associated with a first reflectance and a second reflectance, respectively. The difference between the first reflectance and the second reflectance may be lower than a first threshold value for eliminating the display difference between an etched and a non-etched area of the conductive film. | 01-24-2013 |
20130022801 | CONDUCTIVE FILM - The present invention discloses a conductive film including a substrate, a first hard coated layer, a second hard coated layer, a first refraction layer, a second refraction layer, and a transparent conductive layer, which are arranged in a predetermined order. The second hard coated layer has the silicon-based material accounting for certain percentages of the weight thereof, and the transparent conductive layer may cover parts of the second refraction layer. When a light enters into the transparent conductive layer/the second refraction layer with an incident angle, the light may be associated with a first reflectance/a second reflectance. The difference between the first reflectance and the second reflectance is designed to be lower than a first threshold value. Accordingly, the present invention may eliminate the display difference between an etched and a non-etched area of the conductive film and improve the visual quality. | 01-24-2013 |
20130167924 | COMPOSITE POLY-SILICON SUBSTRATE AND SOLAR CELL HAVING THE SAME - A composite poly-silicon substrate for solar cell having a first substrate layer and a second substrate layer is disclosed. The purity of the first substrate layer ranges from 2N to 3N. The second substrate layer is formed on the first substrate layer, and the purity of the second substrate layer ranges from 6N to 9N. | 07-04-2013 |
20130171769 | MANUFACTURING METHOD OF COMPOSITE POLY-SILICON SUBSTRATE OF SOLAR CELL - A manufacturing method of a composite poly-silicon substrate of solar cells includes the following steps: providing a first substrate layer having a purity ranging from 2N to 3N; and forming a second substrate layer on the first substrate layer, where the purity of the second substrate layer ranges from 6N to 9N. | 07-04-2013 |
Patent application number | Description | Published |
20080308829 | VERTICAL LED WITH CURRENT GUIDING STRUCTURE - Techniques for controlling current flow in semiconductor devices, such as LEDs are provided. For some embodiments, a current guiding structure may be provided including adjacent high and low contact areas. For some embodiments, a second current path (in addition to a current path between an n-contact pad and a metal alloy substrate) may be provided. For some embodiments, both a current guiding structure and second current path may be provided. | 12-18-2008 |
20090093075 | METHOD OF SEPARATING SEMICONDUCTOR DIES - A method for the separation of multiple dies during semiconductor fabrication is described. On an upper surface of a semiconductor wafer containing multiple dies, metal layers are deposited everywhere except where a block of stop electroplating material exists. The stop electroplating material is obliterated, and a barrier layer is formed above the entire remaining structure. A sacrificial metal element is added above the barrier layer, and then the substrate is removed. After the semiconductor material between the individual dies is eradicated, any desired bonding pads and patterned circuitry are added to the semiconductor surface opposite the sacrificial metal element, a passivation layer is added to this surface, and then the sacrificial metal element is removed. Tape is added to the now exposed barrier layer, the passivation layer is removed, the resulting structure is flipped over, and the tape is expanded to separate the individual dies. | 04-09-2009 |
20100258834 | VERTICAL LED WITH CURRENT GUIDING STRUCTURE - Techniques for controlling current flow in semiconductor devices, such as LEDs are provided. For some embodiments, a current guiding structure may be provided including adjacent high and low contact areas. For some embodiments, a second current path (in addition to a current path between an n-contact pad and a metal alloy substrate) may be provided. For some embodiments, both a current guiding structure and second current path may be provided. | 10-14-2010 |
20110037082 | Smart Integrated Semiconductor Light Emitting System Including Light Emitting Diodes And Application Specific Integrated Circuits (ASIC) - A light emitting diode (LED) system includes a substrate, an application specific integrated circuit (ASIC) on the substrate, and at least one light emitting diode (LED) on the substrate in electrical communication with the application specific integrated circuit (ASIC). The light emitting diode (LED) system can also include a polymer lens, and a phosphor layer on the lens or light emitting diode (LED) for producing white light. In addition, multiple light emitting diodes (LEDs) can be mounted on the substrate, and can have different colors for smart color control lighting. The substrate and the application specific integrated circuit (ASIC) are configured to provide an integrated system having smart functionality. In addition, the substrate is configured to compliment and expand the functions of the application specific integrated circuit (ASIC), and can also include built in integrated circuits for performing additional electrical functions. | 02-17-2011 |
20110042803 | Method For Fabricating A Through Interconnect On A Semiconductor Substrate - A method for fabricating a through interconnect on a semiconductor substrate includes the steps of forming a via on a first side of the substrate part way through the substrate, forming an electrically insulating layer on the first side and in the via, forming an electrically conductive layer at least partially lining the via, forming a first contact on the conductive layer in the via, and thinning the substrate from a second side at least to the insulating layer in the via. The method can also include the step of forming a second contact on a second side of the substrate in electrical contact with the first contact. The method can be performed on a semiconductor wafer to form a wafer scale interconnect component. In addition, the interconnect component can be used to construct semiconductor systems such as a light emitting diode (LED) systems. | 02-24-2011 |
20110101400 | LIGHT EMITTING DIODES (LEDS) WITH IMPROVED LIGHT EXTRACTION BY ROUGHENING - Systems and methods are disclosed for fabricating a semiconductor light-emitting diode (LED) device by forming an n-doped gallium nitride (n-GaN) layer on the LED device and roughening the surface of the n-GaN layer to extract light from an interior of the LED device. | 05-05-2011 |
20110217799 | METHOD OF SEPARATING SEMICONDUCTOR DIES - A method for the separation of multiple dies during semiconductor fabrication is described. On an upper surface of a semiconductor wafer containing multiple dies, metal layers are deposited everywhere except where a block of stop electroplating material exists. The stop electroplating material is obliterated, and a barrier layer is formed above the entire remaining structure. A sacrificial metal element is added above the barrier layer, and then the substrate is removed. After the semiconductor material between the individual dies is eradicated, any desired bonding pads and patterned circuitry are added to the semiconductor surface opposite the sacrificial metal element, a passivation layer is added to this surface, and then the sacrificial metal element is removed. Tape is added to the now exposed barrier layer, the passivation layer is removed, the resulting structure is flipped over, and the tape is expanded to separate the individual dies. | 09-08-2011 |
20110316034 | Side By Side Light Emitting Diode (LED) Having Separate Electrical And Heat Transfer Paths And Method Of Fabrication - A light emitting diode includes a thermal conductive substrate having at least one electrical isolation layer configured to provide vertical electrical isolation and a heat transfer path through the substrate from a front side (first side) to a back side (second side) thereof. The light emitting diode includes an anode having a through interconnect, and a cathode having a through interconnect, which are arranged side by side on the substrate. The light emitting diode also includes a LED chip mounted to the substrate between the anode and the cathode. A method for fabricating the light emitting diode includes the steps of providing a thermal conductive substrate having an electrical isolation layer, forming an anode via and a cathode via side by side on a first side of the substrate part way through the substrate, forming an anode through interconnect in the anode via and a cathode through interconnect in the cathode via, thinning the substrate from a second side of the substrate to the anode through interconnect and the cathode through interconnect, and mounting a LED chip to the first side in electrical communication with the cathode through interconnect and the anode through interconnect. | 12-29-2011 |
20110316039 | VERTICAL LED WITH CURRENT GUIDING STRUCTURE - Techniques for controlling current flow in semiconductor devices, such as LEDs are provided. For some embodiments, a current guiding structure may be provided including adjacent high and low contact areas. For some embodiments, a second current path (in addition to a current path between an n-contact pad and a metal alloy substrate) may be provided. For some embodiments, both a current guiding structure and second current path may be provided. | 12-29-2011 |
20120074384 | PROTECTION FOR THE EPITAXIAL STRUCTURE OF METAL DEVICES - Techniques for fabricating metal devices, such as vertical light-emitting diode (VLED) devices, power devices, laser diodes, and vertical cavity surface emitting laser devices, are provided. Devices produced accordingly may benefit from greater yields and enhanced performance over conventional metal devices, such as higher brightness of the light-emitting diode and increased thermal conductivity. Moreover, the invention discloses techniques in the fabrication arts that are applicable to GaN-based electronic devices in cases where there is a high heat dissipation rate of the metal devices that have an original non-(or low) thermally conductive and/or non-(or low) electrically conductive carrier substrate that has been removed. | 03-29-2012 |
20120091466 | Smart Integrated Semiconductor Light Emitting System Including Nitride Based Light Emitting Diodes (LED) And Application Specific Integrated Circuits (ASIC) - A light emitting diode (LED) system includes a substrate, an application specific integrated circuit (ASIC), and at least one light emitting diode (LED) that includes a Group-III nitride based material such as GaN, InGaN, AlGaN, AlInGaN or other (Ga, In or Al) N-based materials. The light emitting diode (LED) system can also include a polymer lens, and a phosphor layer on the lens or light emitting diode (LED) for producing white light. In addition, multiple light emitting diodes (LEDs) can be mounted on the substrate, and can have different colors for smart color control lighting. The substrate and the application specific integrated circuit (ASIC) are configured to provide an integrated LED circuit having smart functionality. In addition, the substrate is configured to compliment and expand the functions of the application specific integrated circuit (ASIC), and can also include built in integrated circuits for performing additional electrical functions. | 04-19-2012 |
20120146083 | VERTICAL LED WITH CURRENT-GUIDING STRUCTURE - Techniques for controlling current flow in semiconductor devices, such as LEDs are provided. For some embodiments, a current-guiding structure may be provided including adjacent high and low contact areas. For some embodiments, a second current path (in addition to a current path between an n-contact pad and a substrate) may be provided. For some embodiments, both a current-guiding structure and second current path may be provided. | 06-14-2012 |
20120168714 | VERTICAL LIGHT EMITTING DIODE (VLED) DIE AND METHOD OF FABRICATION - A vertical light emitting diode (VLED) die includes a first metal having a first surface and an opposing second surface; a second metal on the second surface of the first metal; a p-type semiconductor layer on the first surface of the first metal; a multiple quantum well (MQW) layer on the p-type semiconductor layer configured to emit light; and an n-type semiconductor layer on the multiple quantum well (MQW) layer. | 07-05-2012 |
20120168716 | Light Emitting Diode (LED) Die Having Stepped Substrates And Method Of Fabrication - A light emitting diode (LED) die includes a first substrate having a first surface and an opposing second surface; a second substrate on the second surface of the first substrate; a p-type semiconductor layer on the first surface of the first substrate; a multiple quantum well (MQW) layer on the p-type semiconductor layer configured to emit light; and an n-type semiconductor layer on the multiple quantum well (MQW) layer. | 07-05-2012 |
20130001510 | OPTOELECTRONIC DEVICE HAVING CURRENT BLOCKING INSULATION LAYER FOR UNIFORM TEMPERATURE DISTRIBUTION AND METHOD OF FABRICATION - An optoelectronic device includes a conductive base, a reflective conductive layer on the conductive base, a first semiconductor layer on the conductive layer configured as a first confinement layer, an active layer on the first semiconductor layer configured to emit electromagnetic radiation, a second semiconductor layer on the active layer configured as a second confinement layer, an electrode on the second semiconductor layer, and a current blocking structure on the reflective conductive layer comprising a thin transparent insulation layer aligned with the electrode configured to block current flow from the electrode, to dissipate heat generated at an interface between the first semiconductor layer and the reflective conductive layer, and to transmit electromagnetic radiation reflected from the reflective conductive layer, | 01-03-2013 |
20130026448 | LIGHT EMITTING DIODE (LED) DIE HAVING PERIPHERAL ELECTRODE FRAME AND METHOD OF FABRICATION - A light emitting diode (LED) die includes a first-type semiconductor layer, a multiple quantum well (MQW) layer and a second-type semiconductor layer. The light emitting diode (LED) die also includes a peripheral electrode on the first-type semiconductor layer located proximate to an outer periphery of the first-type semiconductor layer configured to spread current across the first-type semiconductor layer. A method for fabricating the light emitting diode (LED) die includes the step of forming an electrode on the outer periphery of the first-type semiconductor layer at least partially enclosing and spaced from the multiple quantum well (MQW) layer configured to spread current across the first-type semiconductor layer. | 01-31-2013 |
20130277702 | Light Emitting Diode Device Having Electrode With Low Illumination Side And High Illumination Side - A high-brightness vertical light emitting diode (LED) device includes an outwardly located metal electrode having a low illumination side and a high illumination side. The LED device is formed by: forming the metal electrode on an edge of a surface of a LED epitaxy structure using a deposition method, such as physical vapor deposition (PVD), chemical vapor deposition (CVD), evaporation, electro-plating, or any combination thereof; and then performing a packaging process. The composition of the LED may be a nitride, a phosphide or an arsenide. The LED has the following advantages: improving current spreading performance, reducing light-absorption of the metal electrode, increasing brightness, increasing efficiency, and thereby improving energy efficiency. The metal electrode is located on the edge of the device and on the light emitting side. The metal electrode has two side walls, among which one side wall can receive more emission light from the device in comparison with the other one. | 10-24-2013 |
20130302926 | METHOD FOR FABRICATING SEMICONDUCTOR DICE BY SEPARATING A SUBSTRATE FROM SEMICONDUCTOR STRUCTURES USING MULTIPLE LASER PULSES - A method for fabricating semiconductor dice includes the steps of providing a wafer assembly having a substrate and semiconductor structures on the substrate; and defining the semiconductor dice on the substrate. The method also includes the step of separating the substrate from the semiconductor structures by applying a first laser pulse to each semiconductor die on the substrate having first parameters selected to break an interface between the substrate and the semiconductor structures and then applying a second laser pulse to each semiconductor die on the substrate having second parameters selected to complete separation of the substrate from the semiconductor structures. The method can also include the steps of forming one or more intermediate structures between the semiconductor dice on the substrate configured to protect the semiconductor dice during the separating step. | 11-14-2013 |
20130334982 | METHOD FOR GUIDING CURRENT IN A LIGHT EMITTING DIODE (LED) DEVICE - Methods for controlling current flow in semiconductor devices, such as LEDs are provided. For some embodiments, a current-guiding structure may be provided including adjacent high and low contact areas. For some embodiments, a second current path (in addition to a current path between an n-contact pad and a substrate) may be provided. For some embodiments, both a current-guiding structure and second current path may be provided. | 12-19-2013 |
20130337590 | METHOD FOR FABRICATING SIDE BY SIDE LIGHT EMITTING DIODE (LED) HAVING SEPARATE ELECTRICAL AND HEAT TRANSFER PATHS - A method for fabricating a light emitting diode includes the steps of providing a thermal conductive substrate having an electrical isolation layer, forming an anode via and a cathode via side by side on a first side of the substrate part way through the substrate, forming an anode through interconnect in the anode via and a cathode through interconnect in the cathode via, thinning the substrate from a second side of the substrate to the anode through interconnect and the cathode through interconnect, and mounting a LED chip to the first side in electrical communication with the cathode through interconnect and the anode through interconnect. | 12-19-2013 |
20140048766 | METHOD FOR FABRICATING LIGHT EMITTING DIODE (LED) DICE USING BOND PAD DAM AND WAVELENGTH CONVERSION LAYERS - A method for fabricating light emitting diode (LED) dice includes the step of forming a light emitting diode (LED) die having a multiple quantum well (MQW) layer configured to emit electromagnetic radiation, and a confinement layer on the multiple quantum well (MQW) layer having a wire bond pad. The method also includes the steps of forming a dam on the wire bond pad configured to protect a wire bond area on the wire bond pad, forming an adhesive layer on the confinement layer and the wire bond pad with the dam protecting the wire bond area, and forming a wavelength conversion layer on the adhesive layer. A light emitting diode (LED) die includes the dam on the wire bond pad, the adhesive layer on the confinement layer and the wavelength conversion layer on the adhesive layer configured to convert the electromagnetic radiation to a second spectral region. | 02-20-2014 |
20140051197 | METHOD FOR FABRICATING A VERTICAL LIGHT EMITTING DIODE (VLED) DIE HAVING EPITAXIAL STRUCTURE WITH PROTECTIVE LAYER - A method for fabricating a vertical light emitting diode (VLED) die includes the steps of: providing a substrate; forming an epitaxial structure on the substrate; forming an electrically insulative insulation layer covering the lateral surfaces of the epitaxial structure; forming an electrically non-conductive material on the electrically insulative insulation layer; and forming a mirror on the p-doped layer, with the electrically insulative insulation layer configured to protect the epitaxial structure during formation of the mirror. | 02-20-2014 |
20140087499 | METHOD FOR HANDLING A SEMICONDUCTOR WAFER ASSEMBLY - Systems and methods for fabricating a light emitting diode include forming a multilayer epitaxial structure above a carrier substrate; depositing at least one metal layer above the multilayer epitaxial structure; removing the carrier substrate. | 03-27-2014 |
20140151630 | PROTECTION FOR THE EPITAXIAL STRUCTURE OF METAL DEVICES - Techniques for fabricating metal devices, such as vertical light-emitting diode (VLED) devices, power devices, laser diodes, and vertical cavity surface emitting laser devices, are provided. Devices produced accordingly may benefit from greater yields and enhanced performance over conventional metal devices, such as higher brightness of the light-emitting diode and increased thermal conductivity. Moreover, the invention discloses techniques in the fabrication arts that are applicable to GaN-based electronic devices in cases where there is a high heat dissipation rate of the metal devices that have an original non-(or low) thermally conductive and/or non-(or low) electrically conductive carrier substrate that has been removed. | 06-05-2014 |
20140151635 | METHOD FOR FABRICATING A LIGHT EMITTING DIODE (LED) DIE HAVING PROTECTIVE SUBSTRATE - A method for fabricating a light emitting diode die includes the steps of providing a carrier substrate and forming an epitaxial structure on the carrier substrate including a first type semiconductor layer, a multiple quantum well (MQW) layer on the first type semiconductor layer configured to emit light, and a second type semiconductor layer on the multiple quantum well (MQW) layer. The method also includes the steps of forming a plurality of trenches through the epitaxial structure, forming a reflector layer on the second type semiconductor layer, forming a seed layer on the reflector layer and in the trenches, and forming a substrate on the seed layer having an area configured to protect the epitaxial structure. | 06-05-2014 |
20140339496 | Vertical Light Emitting Diode (VLED) Dice Having Confinement Layers With Roughened Surfaces And Methods Of Fabrication - A vertical light emitting diode (VLED) die includes an epitaxial structure having a first-type confinement layer, an active layer on the first-type confinement layer configured as a multiple quantum well (MQW) configured to emit light, and a second-type confinement layer having a roughened surface. In a first embodiment, the roughened surface includes a pattern of holes with a depth (d) in a major surface thereof surrounded by a pattern of protuberances with a height (h) on the major surface. In a second embodiment, the roughened surface includes a pattern of primary protuberances surrounded by a pattern of secondary protuberances. | 11-20-2014 |
20150340346 | STRUCTURE OF A SEMICONDUCTOR ARRAY - A structure of a semiconductor array comprises multiple semiconductor units, an isolation layer and a decomposed or buffer unit. Multiple semiconductor units combined the semiconductor array. The isolation layer coated each semiconductor unit. The decomposed or buffer unit coated the isolation layer and filled between each semiconductor unit to enhance structure of the semiconductor units. Wherein, the isolation layer protected by edge of the semiconductor units and the decomposed or buffer unit. | 11-26-2015 |
20150362165 | Light Engine Array - The invention discloses a light engine array comprises a multiple light engines arranged into an array, multiple dams located on a first surface of the light engines; and the dams combined a dam array. | 12-17-2015 |
Patent application number | Description | Published |
20080197885 | Circuit for detecting maximal frequency of pulse frequency modulation and method thereof - The circuit for detecting the maximal frequency of the pulse frequency modulation includes an oscillator-controlling unit, a delay circuit and a master-slave register. The oscillator-controlling unit is connected to an oscillator, which generates the pulse frequency modulation signals, and includes a first-half pulse-generating module and a second-half pulse-generating module. The delay circuit is connected to the second-half pulse-generating module. The master-slave register includes a clock, an input end and an output end, wherein the input end is connected to the oscillator-controlling unit, and the clock is connected to the delay circuit. | 08-21-2008 |
20080205099 | Power transistor circuit and the method thereof - The power transistor circuit with high-voltage endurance includes a first power transistor, a second power transistor and an enabling circuit. The first power transistor includes a first voltage endurance and a first inner resistance, while the second power transistor includes a second voltage endurance and a second inner resistance. The first voltage endurance and the first inner resistance are smaller than the second voltage endurance and the second inner resistance, respectively. The drain of the second power transistor is connected to the drain of the first power transistor and the enabling circuit. The enabling circuit enables the second power transistor first, and when the drain voltage of the first power transistor is smaller than the first endurance, the enabling circuit then enables the first power transistor. | 08-28-2008 |
20080218284 | Circuit and method for switching PFM and PWM - The switching method between pulse frequency modulation and pulse width modulation signals is first based on an output voltage of a power transistor to generate a corresponding pulse frequency modulation signal. Next, it is determined whether the corresponding pulse frequency modulation signal has reached its maximal frequency. If so, the initial pulse width modulation signal is adjusted to have the same width as the pulse frequency modulation signal. Thereafter, the adjusted pulse width modulation signal is outputted. | 09-11-2008 |
20080224673 | Circuit for starting up a synchronous step-up DC/DC converter and the method thereof - The low voltage circuit for starting up a synchronous step-up DC/DC converter, which connects to a voltage source through an inductor, includes a P-type power transistor, an N-type power transistor and a controller. The P-type power transistor includes a body diode, and one end of the P-type power transistor acts as a power source of an oscillator. The N-type power transistor connects the P-type power transistor in series, and both of the power transistors are not enabled at the same time. The oscillator electrically connects to the controller, which enables the P-type power transistor at initialization time, and enables the N-type power transistor a period after the initialization time. | 09-18-2008 |
20080231348 | Circuit for fixing peak current of an inductor and method thereof - The circuit for fixing the peak current of an inductor includes an operating current, a ramp-type boost converter and a comparator. The magnitude of the operating current is proportional to that of the voltage source of the inductor. The ramp-type boost converter is connected to the operating current. One input end of the comparator is connected to a reference voltage, and the other end is connected to the output of the ramp-type boost converter. The output of the comparator is connected to the gate of a power transistor, which controls the turn-on time of the inductor. | 09-25-2008 |
20080231386 | Oscillation circuit and the method for using the same - The oscillation circuit includes an output current mirror, a P-N complementary current mirror, a P-type current mirror and an N-type current mirror. The P-N complementary current mirror has the same structure as the output current mirror but has current that is only 1/k times the current of the output current mirror, wherein k is greater than 1. The P-type current mirror connects to the P-N complementary current mirror, and has current that is m times the current of the P-N complementary current mirror, where m is greater than 1. The N-type current mirror has one end connected to the P-type current mirror and another end connected to the output current mirror. The N-type current mirror has current that is n times the current of the P-type current mirror, where | 09-25-2008 |
Patent application number | Description | Published |
20130240984 | TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A manufacture includes a doped layer, a body structure over the doped layer, a trench defined in the doped layer, an insulator partially filling the trench, and a first conductive feature buried in, and separated from the doped layer and the body structure by, the insulator. The doped layer has a first type doping. The body structure has an upper surface and includes a body region. The body region has a second type doping different from the first type doping. The trench has a bottom surface. The first conductive feature extends from a position substantially leveled with the upper surface of the body structure toward the bottom surface of the trench. The first conductive feature overlaps the doped layer for an overlapping distance, and the overlapping distance ranging from 0 to 2 μm. | 09-19-2013 |
20130256833 | TRIPLE WELL ISOLATED DIODE AND METHOD OF MAKING - A triple well isolate diode including a substrate having a first conductivity type and a buried layer formed in the substrate, where the buried layer has a second conductivity type. The triple well isolated diode including an epi-layer formed over the substrate and the buried layer, where the epi-layer has the first conductivity type. The triple well isolated diode including a first well formed in the epi-layer, where the first well has the second conductivity type, a second well formed in the epi-layer, where the second well has the first conductivity type and surrounds the first well, a third well formed in the epi-layer, where the third well has the second conductivity type and surrounds the second well. The triple well isolated diode including a deep well formed in the epi-layer, where the deep well has the first conductivity type and extends beneath the first well. | 10-03-2013 |
20140312414 | TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A method of forming a manufacture includes forming a trench in a doped layer. The trench has an upper portion and a lower portion, and a width of the upper portion is greater than that of the lower portion. A first insulating layer is formed along sidewalls of the lower portion of the trench and a bottom surface of the trench. A gate dielectric layer is formed along sidewalls of the upper portion of the trench. A first conductive feature is formed along sidewalls of the gate dielectric layer. A second insulating layer covering the first conductive feature and the first insulating layer is formed, and a second conductive feature is formed along sidewalls of the second insulating layer and a bottom surface of the second insulating layer. | 10-23-2014 |
20150061011 | MOS TRANSISTOR - A novel MOS transistor including a well region, a gate dielectric layer, a gate electrode, a source region and a drain region is provided. The well region of a first conductivity type extends into a semiconductor substrate. The gate dielectric layer is located over the well region. The gate electrode is located over the gate dielectric layer. The source region of a second conductivity type opposite to the first conductivity type and a drain region of the second conductivity type are located in the well region and on opposite sides of the gate electrode. The gate dielectric layer has a first portion and a second portion respectively closest to the source region and the drain region. The thickness of the second portion is greater than that of the first portion, so as to raise breakdown voltage and to maintain current simultaneously. | 03-05-2015 |
20150069507 | MOS TRANSISTOR AND METHOD FOR MANUFACTURING MOS TRANSISTOR - A novel MOS transistor, which includes a source region, a drain region, a channel region, an isolation region, a drift region, a gate dielectric layer, a gate electrode and a field plate, is provided. The gate electrode has a first portion and a second portion. The first portion of a first conductivity type is located over the channel region and has a width equal to or greater than a distance of the gate electrode overlapped with the channel region. The second portion is un-doped and located over the isolation region. Accordingly, the MOS transistor allows higher process freedom saves production cost, as well as improves reliability. | 03-12-2015 |
Patent application number | Description | Published |
20090165835 | THERMOELECTRIC DEVICE WITH THIN FILM ELEMENTS, APPARATUS AND STACKS HAVING THE SAME - A thermoelectric device at least includes a ring-shaped insulative substrate and plural sets of thermoelectric thin film material pair (TEP) disposed thereon. The ring-shaped insulative substrate has an inner rim, an outer rim and a first surface. The sets of TEP electrically connected to each other are disposed on the first surface of the ring-shaped insulative substrate. Each set of TEP includes a P-type and an N-type thermoelectric thin film elements (TEE) electrically connected to each other. Also, the N-type TEE of each set is electrically connected to the P-type TEE of the adjacent set of TER When a current flows through the sets of TEP along a direction parallel to the surfaces of P-type and N-type thermoelectric thin film elements, a temperature difference is generated between the inner rim and the outer rim of the ring-shaped insulative substrate. | 07-02-2009 |
20090277490 | THERMOELECTRIC MODULE DEVICE WITH THIN FILM ELEMENTS AND FABRICATION THEREOF - A thermoelectric module device with thin film elements is disclosed. A pillar structure with a hollow region is formed by stacking a plurality of thin-film type thermoelectric module elements, each including a plurality thin-film thermoelectric pairs arranged in a ring. An insulating and thermal conducting layer covers the inner sidewalls of the hollow region of the pillar structure and the outer sidewalls of the pillar structure. A cool source and a heat source are disposed in the hollow region or outer side of the pillar structure, respectively. | 11-12-2009 |
20120132242 | THERMOELECTRIC GENERATOR APPARATUS WITH HIGH THERMOELECTRIC CONVERSION EFFICIENCY - A thermoelectric generator apparatus disposed on a high-temperature surface of an object (as a heat source), at least includes a heat concentrator, a thermoelectric module and a cold-side heat sink. The heat concentrator has a top surface and a bottom surface contacting a high-temperature surface of the object, and an area of the bottom surface is smaller than that of the high-temperature surface. The thermoelectric module is disposed on the top surface of the heat concentrator. The cold-side heat sink is disposed on the thermoelectric module. Heat generated by the heat source is concentrated on the heat concentrator and flows to the hot side of the thermoelectric module for increasing the heat flux (Q′) passing the thermoelectric module and the hot side temperature of the thermoelectric module. Consequently, the thermoelectric conversion efficiency (η) is improved, and the power generation of the thermoelectric module is increased. | 05-31-2012 |
20120167937 | THERMOELECTRIC MODULE AND METHOD OF MANUFACTURING THE SAME - A thermoelectric module includes a first and a second substrates, plural thermoelectric elements, plural first and second metal electrodes, plural first and second solder layers, and spacers. The thermoelectric elements are disposed between the first and second substrates, and each pair includes a P-type and an N-type thermoelectric elements. An N-type thermoelectric element is electrically connected to the other P-type thermoelectric element of the adjacent pair of thermoelectric element by the second metal electrode. The first metal electrodes and the lower end surfaces of the P/N type thermoelectric elements are jointed by the first solder layers. The second metal electrodes and the upper end surfaces of the P/N type thermoelectric elements are jointed by the second solder layers. The spacers are positioned at one of the first and second solder layers. The melting point of the spacer is higher than the liquidus temperatures of the first and second solder layers. | 07-05-2012 |
20130152990 | SOLID-LIQUID INTERDIFFUSION BONDING STRUCTURE OF THERMOELECTRIC MODULE AND FABRICATING METHOD THEREOF - A solid-liquid interdiffusion bonding structure of a thermoelectric module and a fabricating method thereof are provided. The method includes coating a silver, nickel, or copper layer on surfaces of a thermoelectric component and an electrode plate, and then coating a tin layer. A thermocompression treatment is performed on the thermoelectric component and the electrode plate, such that the melted tin layer reacts with the silver, nickel, or copper layer to form a silver-tin intermetallic compound, a nickel-tin intermetallic compound, or a copper-tin intermetallic compound. After cooling, the thermoelectric component and the electrode plate are bonded together. | 06-20-2013 |
20130153819 | THERMOELECTRIC COMPOSITE MATERIAL - An embodiment of the present disclosure provides a thermoelectric composite material including: a thermoelectric matrix including a thermoelectric material; and a plurality of nano-carbon material units located in the thermoelectric matrix and spaced apart from each other, wherein a spacing between two neighboring nano-carbon material unit is about 50 nm to 2 μm. | 06-20-2013 |
20140158178 | THERMOELECTRIC GENERATOR AND THERMOELECTRIC GENERATING SYSTEM - A thermoelectric generator (TEG) including a cooling element, a heat-collection element and at least one thermoelectric generating module is provided. The heat-collection element is disposed at a side of the cooling element, wherein the heat-collection element has a first surface and a second surface opposite to the first surface, and the heat-collection element is suitable for facing a thermal radiation source with the first surface so as to receive thermal energy thereof in a predetermined distance without contacting the thermal radiation source. The thermoelectric generating module is disposed between the second surface of the heat-collection element and the cooling element, wherein the emissivity of the heat-collection element is larger than 0.8. A thermoelectric generating system is also provided. | 06-12-2014 |
20140174492 | THERMOELECTRIC MATERIAL AND METHOD FOR MANUFACTURING THE SAME - A thermoelectric material and a method for manufacturing the same are provided. The thermoelectric material includes a mixture of nano-thermoelectric crystal particles, micron-thermoelectric crystal particles and nano-metal particles. | 06-26-2014 |
20150176904 | SAMPLE HOLDER FOR ANNEALING APPARATUS AND ELECTRICALLY ASSISTED ANNEALING APPARATUS USING THE SAME - A sample holder for annealing apparatus and electrically assisted annealing apparatus using the same are provided. The sample holder includes a heat conductive shell, high thermal conductive and electrical insulation blocks, first and second electrodes. The heat conductive shell includes a base frame and a top cover. The high thermal conductive and electrical insulation blocks are adjacent to the base frame and the top cover, respectively, and a sample pallet is sandwiched therebetween. Length and width of the sample pallet is smaller than that of the high thermal conductive and electrical insulation blocks. The first and the second electrodes are fixed to two sides of the sample pallet, and are connected to electrifying wire respectively. Thickness of the first and the second electrodes is smaller than that of the sample pallet, while the width of the first and the second electrodes is longer than that of the sample pallet. | 06-25-2015 |
Patent application number | Description | Published |
20110215403 | High Voltage Metal Oxide Semiconductor Device and Method for Making Same - The present invention discloses a high voltage metal oxide semiconductor (HVMOS) device and a method for making same. The high voltage metal oxide semiconductor device comprises: a substrate; a gate structure on the substrate; a well in the substrate, the well defining a device region from top view; a first drift region in the well; a source in the well; a drain in the first drift region, the drain being separated from the gate structure by a part of the first drift region; and a P-type dopant region not covering all the device region, wherein the P-type dopant region is formed by implanting a P-type dopant for enhancing the breakdown voltage of the HVMOS device (for N-type HVMOS device) or reducing the ON resistance of the HVMOS device (for P-type HVMOS device). | 09-08-2011 |
20110220997 | LDMOS Device Having Increased Punch-Through Voltage and Method For Making Same - The present invention discloses an LDMOS device having an increased punch-through voltage and a method for making same. The LDMOS device includes: a substrate; a well of a first conductive type formed in the substrate; an isolation region formed in the substrate; a body region of a second conductive type in the well; a source in the body region; a drain in the well; a gate structure on the substrate; and a first conductive type dopant region beneath the body region, for increasing a punch-through voltage. | 09-15-2011 |
20120319202 | High Voltage Device and Manufacturing Method Thereof - The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device includes: a first conductive type substrate having a device region; a gate, which is located on a surface of the substrate; a second conductive type source and a second conductive type drain in the device region at different sides of the gate respectively; and a second conductive type drift region, which is located in the device region, between the source and the drain. The gate includes: a conductive layer for receiving a gate voltage; and multiple dielectric layers with different thicknesses, located at different horizontal positions. From cross-section view, each dielectric layer is between the conductive layer and the substrate, and the multiple dielectric layers are arranged in an order from thinner to thicker from a side closer to the source to a side closer to the drain. | 12-20-2012 |
20130032880 | HIGH VOLTAGE DEVICE AND MANUFACTURING METHOD THEREOF - The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device is formed in a first conductive type substrate, wherein the substrate has an upper surface. The high voltage device includes: a second conductive type buried layer, which is formed in the substrate; a first conductive type well, which is formed between the upper surface and the buried layer; and a second conductive type well, which is connected to the first conductive type well and located at different horizontal positions. The second conductive type well includes a well lower surface, which has a first part and a second part, wherein the first part is directly above the buried layer and electrically coupled to the buried layer; and the second part is not located above the buried layer and forms a PN junction with the substrate. | 02-07-2013 |
20130217196 | High Voltage Device and Manufacturing Method Thereof - The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device is formed in a first conductive type substrate, wherein the substrate has an upper surface. The high voltage device includes: a second conductive type buried layer, which is formed in the substrate; a first conductive type well, which is formed between the upper surface and the buried layer; and a second conductive type well, which is connected to the first conductive type well and located at different horizontal positions. The second conductive type well includes a well lower surface, which has a first part and a second part, wherein the first part is directly above the buried layer and electrically coupled to the buried layer; and the second part is not located above the buried layer and forms a PN junction with the substrate. | 08-22-2013 |
20140175545 | DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: a first conductive type substrate, a second conductive type high voltage well, a gate, a first conductive type body region, a second conductive type source, a second conductive type drain, a first conductive type body electrode, and a first conductive type floating region. The floating region is formed in the body region, which is electrically floating and is electrically isolated from the source and the gate, such that the electrostatic discharge (ESD) effect is mitigated. | 06-26-2014 |
Patent application number | Description | Published |
20120313104 | ANALOG MEMORY CELL CIRCUIT FOR THE LTPS TFT-LCD - The present invention provides an analog memory cell circuit for the LTPS TFT-LCD. The circuit comprises the first transistor, second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the capacitor. It comprises a plurality of operation period, wherein the transistors are controlled in accordance with the first scan signal, the second scan signal, and the third scan signal, the output signal is output in the opposite to the output jack. | 12-13-2012 |
20130320348 | Analog Memory Cell Circuit for the LTPS TFT-LCD - The present invention provides an analog memory cell circuit for the LTPS TFT-LCD. The circuit comprises the first transistor, second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the capacitor. It comprises a plurality of operation period, wherein the transistors are controlled in accordance with the first scan signal, the second scan signal, and the third scan signal, the output signal is output in the opposite to the output jack. | 12-05-2013 |
20140139958 | ESD PROTECTION CIRCUITS AND METHODS - An electrostatic discharge protection circuit includes a first LC resonator circuit coupled to an input node and disposed in parallel with an internal circuit that is also coupled to the input node, and a second LC resonator circuit coupled in series with the first LC resonator circuit at a first node. The first LC resonator circuit is configured to resonate at a different frequency than a frequency the second LC resonator circuit is configured to resonate. | 05-22-2014 |
20140268439 | ELECTROSTATIC DISCHARGE (ESD) CONTROL CIRCUIT - One or more electrostatic discharge (ESD) control circuit are disclosed herein. In an embodiment, an ESD control circuit has first and second trigger transistors, first and second ESD transistors, and first and second feedback transistors. The ESD transistors provide ESD current paths for ESD current generated during an ESD event. The first and second trigger transistors are on during normal operation to maintain the ESD transistors in an off state. During an ESD event, the first and second transistors are turned off to enable the first and second ESD transistors to provide ESD current paths. The first and second feedback transistors turn on during an ESD event to reinforce the on state of the ESD transistors and to reinforce the off state of the trigger transistors. In this way, the ESD control circuit stably provides multiple ESD current paths to discharge ESD current. | 09-18-2014 |
20150228770 | Robust ESD Protection with Silicon-Controlled Rectifier - Some embodiments relate to a silicon controlled rectifier (SCR) that includes a current path which couples an SCR anode to an SCR cathode. The current path includes a first vertical current path component coupled to the SCR anode, and a second vertical current path component coupled to the SCR cathode. A horizontal current path component includes a first well region and a second well region that meet at a junction lying along a first plane. The first and second well regions cooperatively span a distance between the first and second vertical current path components. The first and second vertical current path components mirror one another symmetrically about the first plane. | 08-13-2015 |
20150311342 | FINFET WITH ESD PROTECTION - In some embodiments, a field effect transistor structure includes a substrate, a fin structure and a gate structure. The fin structure is formed over the substrate. The fin structure includes a first channel region, a first source or drain region and a second source or drain region. The first source or drain region and the second source or drain region are formed on opposite ends of the first channel region, respectively. The well region is formed of the same conductivity type as the second source or drain region, connected to the second source or drain region, and extended to the substrate. The first gate structure wraps around the first channel region in the fin structure. | 10-29-2015 |
20160079229 | SEMICONDUCTOR DEVICE - A semiconductor device is provided. The semiconductor device includes a first transistor on a first side of a shallow trench isolation (STI) region and a second transistor on a second side of the STI region. The first transistor includes a first conductive portion having a second conductivity type formed within a well having a first conductivity type, a first nanowire connected to the first conductive portion and a first active area, and a first gate surrounding the first nanowire. The second transistor includes a second conductive portion having the second conductivity type formed within the well, a second nanowire connected to the second conductive portion and a second active area, and a second gate surrounding the second nanowire. Excess current from an ESD event travels through the first conductive portion through the well to the second conductive portion bypassing the first nanowire and the second nanowire. | 03-17-2016 |
20160093608 | SEMICONDUCTOR DEVICE - A semiconductor device is provided. The semiconductor device includes a first conductive portion on a first side of a first shallow trench isolation (STI) region. The first conductive portion is formed within a first well having a first conductivity type. The first conductive portion has the first conductivity type. The first conductive portion is connected to an electro static discharge (ESD) circuit. A second conductive portion is on a second side of the first STI region. The second conductive portion is formed within a second well having a second conductivity type. The second conductive portion having the first conductivity type is connected to a first nanowire and an input output I/O port. | 03-31-2016 |
Patent application number | Description | Published |
20090179214 | LIGHT EITTING DEVICE WITH MAGNETIC FIELD - A light emitting device with magnetic field includes a light-emitting structure and a first magnetic-source layer. The light-emitting structure includes a first doped structural layer, a second doped structural layer, an active layer between the two doped structural layers, a first electrode, and a second electrode. The first magnetic-source layer is integrated with the light-emitting structure to produce a magnetic field in the light-emitting structure. The magnetic field transversely shifts a driving current of the light-emitting structure to redistribute in the light-emitting structure. | 07-16-2009 |
20100282304 | SOLAR CELL AND METHOD OF MANUFACTURING THE SAME - A bi-functional photovoltaic device is provided. The bi-functional photovoltaic device includes at least one solar cell and a control device. Each of the solar cell includes a multilayer semiconductor layer of group III-V compound semiconductor, a first electrode disposed on the back of the multilayer semiconductor layer, and a second electrode disposed on the front of the multilayer semiconductor layer. The control device connects with the at least one solar cell in order to control them functioning as solar cell or light emitting diode. | 11-11-2010 |
20110140540 | CHARGE APPARATUS - A charge apparatus including a natural energy conversion module, an energy converter, an energy transmitter, and an energy receiver is provided. The natural energy conversion module receives a natural energy and converts the natural energy into a first electric energy. The energy converter is electrically connected to the natural energy conversion module and converts the first electric energy into a wireless energy. The energy transmitter is electrically connected to the energy converter and transmits the wireless energy in a wireless manner. The energy receiver receives the wireless energy in a wireless manner and converts the wireless energy into a second electric energy. | 06-16-2011 |
20120168801 | LIGHT EMITTING DEVICE AND PACKAGE STRUCTURE THEREOF - A light-emitting device package structure includes a carrier, at least one light-emitting device and a magnetic element. The magnetic element aids in enhancing overall luminous output efficiency. | 07-05-2012 |
20130114243 | CEILING FIXTURE - A ceiling fixture including a first heat dissipation structure, a circuit board and a flexible light source is provided. The first heat dissipation structure has a curved surface, a containing cavity and a plurality of heat dissipation channels. Each heat dissipation channel is connected to the containing cavity and the external environment. The circuit board is disposed in the containing cavity and contacts the first heat dissipation structure. The flexible light source is disposed on the curved surface. | 05-09-2013 |
20130135507 | PHOTOGRAPHY AND PROJECTION APPARATUS AND LIGHT EMITTING AND SENSING MODULE - A photography and projection apparatus including a light emitting and sensing module and a projection lens is provided. The light emitting and sensing module has a light emitting and sensing area, and includes a light emitting unit array and a light sensing unit array. The light emitting unit array includes a plurality of light emitting units arranged in an array. The light emitting units are distributed in the light emitting and sensing area. The light emitting unit array is adapted to provide an image beam. The light sensing unit array includes a plurality of light sensing units arranged in an array. The light sensing units are distributed in the light emitting and sensing area. The projection lens is disposed on a transmission path of the image beam. A light emitting and sensing module is also provided. | 05-30-2013 |
20130235578 | ILLUMINATION DEVICE AND ASSEMBLING METHOD THEREOF - An illumination device including a base and a heat dissipation member is provided. The heat dissipation member disposed on the base has a central axis and at least one heat dissipation channel. At least one virtual circle having a radius R | 09-12-2013 |
20130250630 | METHOD FOR CONTROLLING ALTERNATING CURRENT OUTPUT OF PHOTOVOLTAIC DEVICE AND ALTERNATING CURRENT PHOTOVOLTAIC DEVICE - A method for controlling an alternating current (AC) output of a photovoltaic (PV) device, and an AC PV device are introduced herein. The method includes: receiving solar radiant energy by using a PV cell array and then converting the solar radiant energy into a direct current (DC) energy output; and selecting an arrangement and combination sequence of the PV cells by using a control module, to vary a voltage according to a timing (frequency), so that a sine-like wave output is obtained at an output terminal. | 09-26-2013 |
20140217955 | CHARGE APPARATUS - A charge apparatus including a natural energy conversion module, an energy converter, an energy transmitter, an energy receiver, and an electricity storage device is provided. The natural energy conversion module receives the natural energy and converts the natural energy into a first electric energy. The energy converter is electrically connected to the natural energy conversion module and converts the first electric energy into a wireless energy. The energy transmitter is electrically connected to the energy converter and transmits the wireless energy. The energy receiver receives the wireless energy and converts the wireless energy into a second electric energy to charge an external apparatus. The energy transmitter monitors the current charge status of the external apparatus so as to adjust transmitting the wireless energy. The electricity storage device is electrically connected to the natural energy conversion module to store the first electric energy. | 08-07-2014 |
20150108508 | DISPLAY PANEL - A display panel comprising a substrate, a meshed shielding pattern, a plurality of light-emitting devices and a solar cell is provided. The substrate has a first surface and a second surface opposite to the first surface, the substrate comprises a first circuit layer disposed over the first surface and a second circuit layer disposed over the second surface. The meshed shielding pattern is disposed on first surface of the substrate to define a plurality of pixel regions over the substrate. The light-emitting devices are disposed on the first surface of the substrate and electrically connected to the first circuit layer, and at least one of the light-emitting devices is disposed in one of the pixel regions. The solar cell is disposed on the second surface of the substrate and electrically connected to the second circuit layer. | 04-23-2015 |
20150111329 | TRANSFER-BONDING METHOD FOR LIGHT EMITTING DEVICES - A transfer-bonding method for light emitting devices including following steps is provided. A plurality of light emitting devices is formed over a first substrate and is arranged in array, wherein each of the light emitting devices includes a device layer and an interlayer sandwiched between the device layer and the first substrate. A protective layer is formed over the first substrate to selectively cover parts of the light emitting devices, and other parts of the light emitting devices are uncovered by the protective layer. The device layers uncovered by the protective layer are bonded with a second substrate. The interlayers uncovered by the protective layer are removed, so that parts of the device layers uncovered by the protective layer are separated from the first substrate and are transfer-bonded to the second substrate. | 04-23-2015 |
Patent application number | Description | Published |
20100287364 | BOOT SYSTEMS AND METHODS, AND RELATED DEVICES - Boot systems and methods are provided. The boot system includes an IO (Input/Output) chip, a memory device, and a BIOS (Basic Input/Output System). The memory device is coupled to the IO chip, and includes at least a rescue OS (Operating System). The BIOS reads the rescue OS from the memory device via the IO chip, and boots an electronic device based on the rescue OS. | 11-11-2010 |
20120191965 | BOOT SYSTEMS AND METHODS, AND RELATED DEVICES - Boot systems and methods are provided. The boot system includes an IO (Input/Output) chip, a memory device, and a BIOS (Basic Input/Output System). The memory device is coupled to the IO chip, and includes at least a rescue OS (Operating System). The BIOS reads the rescue OS from the memory device via the IO chip, and boots an electronic device based on the rescue OS. | 07-26-2012 |
20140223212 | POWER MANAGEMENT CIRCUIT, POWER MANAGEMENT METHOD, AND COMPUTER SYSTEM - A power management circuit is provided. The power management circuit includes a power switch, a current/voltage detector, a current setting unit, and a control unit. The power switch is coupled to a power supply of the computer system. When the power switch is turned on, it supplies an output current and an output voltage of the power supply to an external device. The current/voltage detector detects the magnitudes of the output current and the output voltage. The current setting unit sets a plurality of current thresholds. When the computer system is in a power-saving state and when the output current is greater than a first current threshold and smaller than a second current threshold or the output voltage is smaller than a first voltage threshold and larger than a second voltage threshold, the control unit issues a notification signal to execute a predetermined operation on the power supply. | 08-07-2014 |
20150085416 | INTEGRATED CIRCUIT WITH PROTECTION FUNCTION - An integrated circuit generating a driving signal to a load according to an input voltage and including an impedance switching unit, a first protection unit, a first detection unit and a control unit is disclosed. The impedance switching unit takes the input voltage as the driving signal according to a control signal. The first protection unit generates a first detection signal when a current passing through the impedance switching unit is higher than a predetermined current. The first detection unit detects a voltage of the impedance switching unit to generate a detection result. The control unit controls the control signal according to the first detection signal. | 03-26-2015 |
20150214734 | Control Chip, Control Method and Connection Device Utilizing the Same - A control chip including a plurality of first pins, a plurality of second pins, a plurality of third pins, a level detection unit, a determining unit and a control unit is provided. The first pins are coupled to a host device via a first connection port. The second pins are coupled to an electronic device via a second connection port. The third pins are coupled to a peripheral device via a third connection port. The level detection unit detects the first and second pins to generate a first detection result. The determining unit determines whether a portion of the first and second pins transmit data to generate a determination result. The control unit adjusts a level of a specific pin among the first and second pins according to the first detection result and the determination result. | 07-30-2015 |
20160049802 | TRANSMISSION DEVICE AND CONTROL METHOD THEREOF - A chip is provided. A power transmission path and a data transmission path are coupled between an upstream port and a downstream port. A first detection unit generates a first trigger signal when a voltage level of the power transmission path reaches a first predetermined value. A first control unit turns on the data transmission path according to the first trigger signal. A second detection unit detects a voltage level of the data transmission path. When the voltage level of the data transmission path matches a pre-determined condition, the second detection unit generates a second trigger signal, and the first control unit turns off the data transmission path according to the second trigger signal. A setting unit sets the voltage level of the data transmission path when the first control unit turns off the data transmission path. | 02-18-2016 |
Patent application number | Description | Published |
20120011217 | MASTER/SLAVE DECISION DEVICE AND MASTER/SLAVE DECISION METHOD APPLIED TO NETWORK DEVICE - A master/slave decision device applied to a first network device is provided, where the first network device is coupled to a second network device, and the master/slave decision device includes a seed distance detection unit and a decision unit. The seed distance decision unit is utilized for detecting a seed distance between a first seed utilized in a first scrambler of the first network device and a second seed utilized in a second scrambler of the second network device. The decision unit is coupled to the seed distance detecting unit, and is utilized for determining the first network device to be a master device or a slave device according to the seed distance. | 01-12-2012 |
20120137151 | NETWORK DEVICE AND NETWORK CONNECTING METHOD FOR SUPPORTING POWER SAVING MECHANISM THROUGH AUTO-NEGOTIATION OF HDMI - A network device, for supporting a power saving mechanism through an auto-negotiation of HDMI, includes a transmitting circuit and a receiving circuit. The transmitting circuit is arranged for generating a link pulse signal to a second network device, wherein the network device and the second network device perform the auto-negotiation of a network connection by using the link pulse signal through HDMI in order to support the power saving mechanism. After the receiving circuit of the network device receives another link pulse signal transmitted from the second network device through HDMI, the network device is controlled to be operated under the power saving mechanism. | 05-31-2012 |
20120163243 | COMMUNICATION DEVICE WITH ENERGY SAVING MODE AND METHOD THEREOF - A communication device has a transmitting circuit, a receiving circuit, and a controller. The transmitting circuit transmits a first data to a transmission line. The first data is generated by a first scrambler wherein the values of the registers of the first scrambler are characterized by a first combination number. The receiving circuit receives a second data scrambled by a second scrambler from the transmission line. The first and the second scramblers have the same scrambler generator polynomial. The receiving circuit has a descrambler having a plurality of registers for descrambling the second data. The values of the registers of the second scrambler are characterized by a second combination number when the descrambler descrambles the second data. The controller configures the values of the registers of the first scrambler according to the first combination number, the second combination number, and/or a difference between the first and the second combination numbers. | 06-28-2012 |
20120314748 | NETWORK RECEIVER AND ADJUSTING METHOD THEREOF - A network receiver and the adjusting method thereof, the network receiver includes a first delay unit, a second delay unit, a first processing unit and an adjusting circuit. The first delay unit is for delaying a first signal received from a first transmission line to generate a delayed first signal. The second delay unit is for delaying a second signal received from a second transmission line to generate a delayed second signal. The first processing unit is for processing a difference between the delayed first signal and the delayed second signal to generate first data. The adjusting circuit adjusts the first and second delay units to have a plurality of delay amount combinations, the first processing unit generates a plurality of first data respectively corresponding to the delay amount combinations, and the adjusting circuit adjusts delay amount of the first and second delay units according to the first data. | 12-13-2012 |
20120317608 | NETWORK RECEIVER AND CONTROL METHOD THEREOF - A network receiver includes a first variable resistor, a second variable resistor, a first processing unit, a second processing unit and an adjusting circuit. The first variable resistor is coupled to a first transmission line via a first terminal for transmitting a first signal. The second variable resistor is coupled to a second transmission line via a second terminal for transmitting a second signal. The first processing unit is utilized for obtaining a difference according to the first signal and the second signal, and processing the difference to generate first data. The second processing unit is utilized for obtaining a summation according to the first signal and the second signal, and processing the summation to generate second data. The adjusting circuit is utilized for adjusting resistance(s) of at least one of the first variable resistor and the second variable resistor according to the first data and the second data. | 12-13-2012 |
20130051578 | NETWORK SIGNAL RECEIVING SYSTEM AND NETWORK SIGNAL RECEIVING METHOD - The disclosure provides a network signal receiving system and a network signal receiving method. The network signal receiving system comprises: a high pass filter, a canceller, and an adder. The high pass filter is utilized for performing a high pass filtering operation for an audio data signal to output at least a signal corresponding to transitions of the audio data signal, wherein the audio data signal is synchronized with a network data signal. The canceller is coupled to the high pass filter, and utilized for generating a noise cancelling signal according to the at least a signal output by the high pass filter. The adder is coupled to the canceller, utilized for receiving the network data signal and the noise cancelling signal, so as to use the noise cancelling signal to cancel at least a noise in the network data signal, which is corresponding to the at least a signal. | 02-28-2013 |
20130072133 | SIGNAL TRANSCEIVING METHOD, SIGNAL TRANSCEIVER UTILIZING THE SIGNAL TRANSCEIVING METHOD, NETWORK CONNECTION METHOD AND NETWORK DEVICE UTILIZING THE NETWORK CONNECTION METHOD - A signal transceiving method, applied to a signal transceiver, includes: adjusting to approximate a value of a clock frequency of a signal to be transmitted from the signal transceiver to a value of a clock frequency of a received signal; performing an echo cancellation operation; computing a distance between a first certification code transmitted by the signal transceiver and a second certification code received by the signal transceiver; and stopping the echo cancellation operation when the distance is smaller than a threshold value. | 03-21-2013 |
20130100990 | TRANSCEIVER CAPABLE OF DYNAMICALLY ADJUSTING TRANSMITTER CLOCK AND RELATED METHOD THEREOF - A transceiver for dynamically adjusting a transmission clock includes: a transmitting unit, a receiving unit, and a transmission clock tracking unit. The transmitting unit is arranged for transmitting a transmission signal according to the transmission clock. The receiving unit is arranged for receiving a reception signal. The transmission clock tracking unit is coupled to the transmitting unit and the receiving unit, and arranged for dynamically controlling the transmission clock of the transmitting unit according to a reception clock corresponding to the reception signal. | 04-25-2013 |
20130114390 | NETWORK APPARATUS AND METHOD FOR ELIMINATING INTERFERENCE BETWEEN TRANSPORT PORTS - A network apparatus for eliminating interference between transport ports includes a plurality of transport ports, a plurality of seed comparators, and a control unit. The plurality of seed comparators are coupled to the plurality of transport ports, respectively, wherein a first seed comparator is utilized for comparing a first seed of a first transport port with a second seed of a second transport port and accordingly generating a comparing result. The controlling unit is coupled to the plurality of seed comparators and the plurality of transport ports, for generating a control signal to cancel interference between the plurality of transport ports according to the comparing result. | 05-09-2013 |
20130128933 | TRANSCEIVER WITHOUT USING A CRYSTAL OSCILLATOR - A transceiver includes a transceiver and a clock generation unit. The clock generation unit includes a clock generator, a multiplexer, and a frequency difference detector. The transceiver exchanges data with a link partner according to a first clock generated by a phase-locked loop. The clock generator is used for generating and outputting a second clock. The multiplexer is used for receiving a calibration clock or a receiver clock of the link partner, and outputting the calibration clock or the receiver clock of the link partner. The frequency difference detector is used for generating a difference signal according to a difference between the calibration clock and the second clock, or a difference between the receiver clock of the link partner and the second clock. The clock generator adjusts the shift of the second clock according to the difference signal. The phase-locked loop generates the first clock according to the second clock. | 05-23-2013 |