Patent application number | Description | Published |
20080254615 | Method for reducing dielectric overetch using a dielectric etch stop at a planar surface - A substantially planar surface coexposes conductive or semiconductor features and a dielectric etch stop material. A second dielectric material, different from the dielectric etch stop material, is deposited on the substantially planar surface. A selective etch etches a hole or trench in the second dielectric material, so that the etch stops on the conductive or semiconductor feature and the dielectric etch stop material. In a preferred embodiment the substantially planar surface is formed by filling gaps between the conductive or semiconductor features with a first dielectric such as oxide, recessing the oxide, filling with a second dielectric such as nitride, then planarizing to coexpose the nitride and the conductive or semiconductor features. | 10-16-2008 |
20080308903 | POLYCRYSTALLINE THIN FILM BIPOLAR TRANSISTORS - A semiconductor device comprising a bipolar transistor having a base region, an emitter region and a collector region, wherein the base region comprises polycrystalline semiconductor material formed by crystallizing silicon, germanium or silicon germanium in contact with a silicide, germanide or silicide germanide is described. The emitter region and collector region also may comprise polycrystalline semiconductor material formed by crystallizing silicon, germanium or silicon germanium in contact with a silicide, germanide or silicide germanide forming metal. The polycrystalline semiconductor material is preferably silicided polysilicon, which is formed in contact with C49 phase titanium silicide. | 12-18-2008 |
20080311710 | METHOD TO FORM LOW-DEFECT POLYCRYSTALLINE SEMICONDUCTOR MATERIAL FOR USE IN A TRANSISTOR - A method is described for forming a thin film transistor having its current-switching region in polycrystalline semiconductor material which has been crystallized in contact with titanium silicide, titanium silicide-germanide, or titanium germanide. The titanium silicide, titanium silicide-germanide, or titanium germanide is formed having feature size no more than 0.25 micron in the smallest dimension. The small feature size tends to inhibit the phase transformation from C49 to C54 phase titanium silicide. The C49 phase of titanium silicide has a very close lattice match to silicon, and thus provides a crystallization template for the silicon as it forms, allowing formation of large-grain, low-defect silicon. Titanium does not tend to migrate through the silicon during crystallization, limiting the danger of metal contamination. In preferred embodiments, the transistors thus formed may be, for example, field-effect transistors or bipolar junction transistors. | 12-18-2008 |
20080311722 | METHOD FOR FORMING POLYCRYSTALLINE THIN FILM BIPOLAR TRANSISTORS - A method is described for forming a semiconductor device comprising a bipolar transistor having a base region, an emitter region and a collector region, wherein the base region comprises polycrystalline semiconductor material formed by crystallizing silicon, germanium or silicon germanium in contact with a silicide, germanide or silicide germanide. The emitter region and collector region also may be formed from polycrystalline semiconductor material formed by crystallizing silicon, germanium or silicon germanium in contact with a silicide, germanide or silicide germanide forming metal. The polycrystalline semiconductor material is preferably silicided polysilicon, which is formed in contact with C49 phase titanium silicide. | 12-18-2008 |
20090001347 | 3D R/W cell with reduced reverse leakage - A nonvolatile memory device includes a semiconductor diode steering element, and a semiconductor read/write switching element. | 01-01-2009 |
20090003036 | Method of making 3D R/W cell with reduced reverse leakage - A method of making a nonvolatile memory device includes forming a semiconductor diode steering element, and forming a semiconductor read/write switching element. | 01-01-2009 |
20090004844 | Forming Complimentary Metal Features Using Conformal Insulator Layer - A method is provided to form densely spaced metal lines. A first set of metal lines is formed by etching a first metal layer. A thin dielectric layer is conformally deposited on the first metal lines. A second metal is deposited on the thin dielectric layer, filling gaps between the first metal lines. The second metal layer is planarized to form second metal lines interposed between the first metal lines, coexposing the thin dielectric layer and the second metal layer at a substantially planar surface. In some embodiments, planarization continues to remove the thin dielectric covering tops of the first metal lines, coexposing the first metal lines and the second metal lines, separated by the thin dielectric layer, at a substantially planar surface. | 01-01-2009 |
20090086521 | MULTIPLE ANTIFUSE MEMORY CELLS AND METHODS TO FORM, PROGRAM, AND SENSE THE SAME - Methods are described to fabricate, program, and sense a multilevel one-time-programmable memory cell including a steering element such as a diode and two, three, or more dielectric antifuses in series. The antifuses may be of different thicknesses, or may be formed of dielectric materials having different dielectric constants, or both. The antifuses and programming pulses are selected such that when the cell is programmed, the largest voltage drop in the memory cell is across only one of the antifuses, while the other antifuses allow some leakage current. In some embodiments, the antifuse with the largest voltage drop breaks down, while the other antifuses remain intact. In this way, the antifuses can be broken down individually, so a memory cell having two, three, or more antifuses may achieve any of three, four, or more unique data states. | 04-02-2009 |
20090142921 | METHOD FOR REDUCING DIELECTRIC OVERETCH WHEN MAKING CONTACT TO CONDUCTIVE FEATURES - In a first preferred embodiment of the present invention, conductive features are formed on a first dielectric etch stop layer, and a second dielectric material is deposited over and between the conductive features. A via etch to the conductive features which is selective between the first and second dielectrics will stop on the dielectric etch stop layer, limiting overetch. In a second embodiment, a plurality of conductive features is formed in a subtractive pattern and etch process, filled with a dielectric fill, and then a surface formed coexposing the conductive features and dielectric fill. A dielectric etch stop layer is deposited on the surface, then a third dielectric covers the dielectric etch stop layer. When a contact is etched through the third dielectric, this selective etch stops on the dielectric etch stop layer. A second etch makes contact to the conductive features. | 06-04-2009 |
20090155962 | Method for fabricating pitch-doubling pillar structures - A method of making a semiconductor device includes forming at least one device layer over a substrate, forming at least two spaced apart features over the at least one device layer, forming sidewall spacers on the at least two features, filling a space between a first sidewall spacer on a first feature and a second sidewall spacer on a second feature with a filler feature, selectively removing the sidewall spacers to leave the first feature, the filler feature and the second feature spaced apart from each other, and etching the at least one device layer using the first feature, the filler feature and the second feature as a mask. | 06-18-2009 |
20090168480 | Three dimensional hexagonal matrix memory array - A nonvolatile memory device includes a plurality of nonvolatile memory cells arranged in a substantially hexagonal pattern. The nonvolatile memory cells may be pillar shaped non-volatile memory cells which can be patterned using triple or quadruple exposure lithography or by using a self-assembling layer. | 07-02-2009 |
20090168507 | Method of programming cross-point diode memory array - A method of programming a nonvolatile memory array including a plurality of nonvolatile memory cells, a plurality of bit lines, and a plurality of word lines, wherein each memory cell comprises a diode, or a diode and a resistivity switching element is disclosed. The method includes both bias programming the memory cells of the device. | 07-02-2009 |
20090170030 | Method of making a pillar pattern using triple or quadruple exposure - Methods of making pillar shaped device array using a triple or quadruple exposure technique are described. A plurality of pillar shaped devices are formed arranged in a hexagonal or rectangular pattern. | 07-02-2009 |
20090181515 | Selective germanium deposition for pillar devices - A method of making a pillar device includes providing an insulating layer having an opening, and selectively depositing germanium or germanium rich silicon germanium semiconductor material into the opening to form the pillar device. | 07-16-2009 |
20090194153 | PHOTOVOLTAIC CELL COMPRISING A THIN LAMINA HAVING LOW BASE RESISTIVITY AND METHOD OF MAKING - Fabrication of a photovoltaic cell comprising a thin semiconductor lamina may require additional processing after the semiconductor lamina is bonded to a receiver. To minimize high-temperature steps after bonding, the p-n junction is formed at the back of the cell, at the bonded surface. In some embodiments, the front surface of the semiconductor lamina is not doped or is locally doped using low-temperature methods. The base resistivity of the photovoltaic cell may be reduced, allowing a front surface field to be reduced or omitted. | 08-06-2009 |
20090194162 | METHOD TO FORM A PHOTOVOLTAIC CELL COMPRISING A THIN LAMINA - A very thin photovoltaic cell is formed by implanting gas ions below the surface of a donor body such as a semiconductor wafer. Ion implantation defines a cleave plane, and a subsequent step exfoliates a thin lamina from the wafer at the cleave plane. A photovoltaic cell, or all or a portion of the base or emitter of a photovoltaic cell, is formed within the lamina. In preferred embodiments, the wafer is affixed to a receiver before the cleaving step. Electrical contact can be formed to both surfaces of the lamina, or to one surface only. | 08-06-2009 |
20090194163 | METHOD TO FORM A PHOTOVOLTAIC CELL COMPRISING A THIN LAMINA - A very thin photovoltaic cell is formed by implanting gas ions below the surface of a donor body such as a semiconductor wafer. Ion implantation defines a cleave plane, and a subsequent step exfoliates a thin lamina from the wafer at the cleave plane. A photovoltaic cell, or all or a portion of the base or emitter of a photovoltaic cell, is formed within the lamina. In preferred embodiments, the wafer is affixed to a receiver before the cleaving step. Electrical contact can be formed to both surfaces of the lamina, or to one surface only. | 08-06-2009 |
20090194164 | METHOD TO FORM A PHOTOVOLTAIC CELL COMPRISING A THIN LAMINA - A very thin photovoltaic cell is formed by implanting gas ions below the surface of a donor body such as a semiconductor wafer. Ion implantation defines a cleave plane, and a subsequent step exfoliates a thin lamina from the wafer at the cleave plane. A photovoltaic cell, or all or a portion of the base or emitter of a photovoltaic cell, is formed within the lamina. In preferred embodiments, the wafer is affixed to a receiver before the cleaving step. Electrical contact can be formed to both surfaces of the lamina, or to one surface only. | 08-06-2009 |
20090197367 | METHOD TO FORM A PHOTOVOLTAIC CELL COMPRISING A THIN LAMINA - A very thin photovoltaic cell is formed by implanting gas ions below the surface of a donor body such as a semiconductor wafer. Ion implantation defines a cleave plane, and a subsequent step exfoliates a thin lamina from the wafer at the cleave plane. A photovoltaic cell, or all or a portion of the base or emitter of a photovoltaic cell, is formed within the lamina. In preferred embodiments, the wafer is affixed to a receiver before the cleaving step. Electrical contact can be formed to both surfaces of the lamina, or to one surface only. | 08-06-2009 |
20090197368 | METHOD TO FORM A PHOTOVOLTAIC CELL COMPRISING A THIN LAMINA - A very thin photovoltaic cell is formed by implanting gas ions below the surface of a donor body such as a semiconductor wafer. Ion implantation defines a cleave plane, and a subsequent step exfoliates a thin lamina from the wafer at the cleave plane. A photovoltaic cell, or all or a portion of the base or emitter of a photovoltaic cell, is formed within the lamina. In preferred embodiments, the wafer is affixed to a receiver before the cleaving step. Electrical contact can be formed to both surfaces of the lamina, or to one surface only. | 08-06-2009 |
20090230571 | MASKING OF REPEATED OVERLAY AND ALIGNMENT MARKS TO ALLOW REUSE OF PHOTOMASKS IN A VERTICAL STRUCTURE - A monolithic three dimensional semiconductor device structure includes a first layer including a first occurrence of a first reference mark at a first location, and a second layer including a second occurrence of the first reference mark at a second location, wherein the second location is substantially directly above the first location. The device structure also includes an intermediate layer between the first layer and the second layer, the intermediate layer including a blocking structure, wherein the blocking structure is vertically interposed between the first occurrence of the first reference mark and the second occurrence of the first reference mark. Other aspects are also described. | 09-17-2009 |
20090269932 | Method for fabricating self-aligned complimentary pillar structures and wiring - A method of making a semiconductor device includes forming at least one device layer over a substrate, forming at least two spaced apart features over the at least one device layer, forming sidewall spacers on the at least two features, selectively removing the spaced apart features, filling a space between a first sidewall spacer and a second sidewall spacer with a filler feature, selectively removing the sidewall spacers to leave a plurality of the filler features spaced apart from each other, and etching the at least one device layer using the filler feature as a mask. | 10-29-2009 |
20090293931 | ASYMMETRIC SURFACE TEXTURING FOR USE IN A PHOTOVOLTAIC CELL AND METHOD OF MAKING - A novel surface texturing provides improved light-trapping characteristics for photovoltaic cells. The surface is asymmetric and includes shallow slopes at between about 5 and about 30 degrees from horizontal as well as steeper slopes at about 70 degrees or more from horizontal. It is advantageously used as either the front or back surface of a thin semiconductor lamina, for example between about 1 and about 20 microns thick, which comprises at least the base or emitter of a photovoltaic cell. In embodiments of the present invention, the shallow slopes are formed using imprint photolithography. | 12-03-2009 |
20090309089 | Non-Volatile Memory Arrays Comprising Rail Stacks with a Shared Diode Component Portion for Diodes of Electrically Isolated Pillars - An integrated circuit including vertically oriented diode structures between conductors and methods of fabricating the same are provided. Two-terminal devices such as passive element memory cells can include a diode steering element in series with an antifuse and/or other state change element. The devices are formed using pillar structures at the intersections of upper and lower sets of conductors. The height of the pillar structures are reduced by forming part of the diode for each pillar in a rail stack with one of the conductors. A diode in one embodiment can include a first diode component of a first conductivity type and a second diode component of a second conductivity type. A portion of one of the diode components is divided into first and second portions with one on the portions being formed in the rail stack where it is shared with other diodes formed using pillars at the rail stack. | 12-17-2009 |
20100009488 | METHOD TO FORM A PHOTOVOLTAIC CELL COMPRISING A THIN LAMINA - A very thin photovoltaic cell is formed by implanting gas ions below the surface of a donor body such as a semiconductor wafer. Ion implantation defines a cleave plane, and a subsequent step exfoliates a thin lamina from the wafer at the cleave plane. A photovoltaic cell, or all or a portion of the base or emitter of a photovoltaic cell, is formed within the lamina. In preferred embodiments, the wafer is affixed to a receiver before the cleaving step. Electrical contact can be formed to both surfaces of the lamina, or to one surface only. | 01-14-2010 |
20100031995 | PHOTOVOLTAIC MODULE COMPRISING THIN LAMINAE CONFIGURED TO MITIGATE EFFICIENCY LOSS DUE TO SHUNT FORMATION - A photovoltaic cell can be formed from a thin semiconductor lamina cleaved from a substantially crystalline wafer. Shunts may inadvertently be formed through such a lamina, compromising device performance. By physically severing the lamina into a plurality of segments, the segments of the lamina preferably electrically connected in series, loss of efficiency due to shunt formation may be substantially reduced. In some embodiments, adjacent laminae are connected in series into strings, and the strings are connected in parallel to compensate for the reduction in current caused by severing the lamina into segments. | 02-11-2010 |
20100032007 | PHOTOVOLTAIC CELL COMPRISING A THIN LAMINA HAVING A REAR JUNCTION AND METHOD OF MAKING - Fabrication of a photovoltaic cell comprising a thin semiconductor lamina may require additional processing after the semiconductor lamina is bonded to a receiver. To minimize high-temperature steps after bonding, the p−n junction is formed at the back of the cell, at the bonded surface. In some embodiments, the front surface of the semiconductor lamina is not doped or is locally doped using low-temperature methods. The base resistivity of the photovoltaic cell may be reduced, allowing a front surface field to be reduced or omitted. | 02-11-2010 |
20100032010 | METHOD TO MITIGATE SHUNT FORMATION IN A PHOTOVOLTAIC CELL COMPRISING A THIN LAMINA - A photovoltaic cell can be formed from a thin semiconductor lamina cleaved from a substantially crystalline wafer. Shunts may inadvertently be formed through such a lamina, compromising device performance. By physically severing the lamina into a plurality of segments, the segments of the lamina preferably electrically connected in series, loss of efficiency due to shunt formation may be substantially reduced. In some embodiments, adjacent laminae are connected in series into strings, and the strings are connected in parallel to compensate for the reduction in current caused by severing the lamina into segments. | 02-11-2010 |
20100139755 | FRONT CONNECTED PHOTOVOLTAIC ASSEMBLY AND ASSOCIATED METHODS - A photovoltaic device is disclosed herein that, in various aspects, includes a conductive layer, and a substantially crystalline lamina with a first surface oriented toward the conductive layer and a second surface oriented away from the conductive layer. The lamina thickness is within the range between about 0.2 microns and about 50 microns. An aperture passes through the lamina from the first surface to the second surface. A connector in electrical communication with the conductive layer is disposed through the aperture. Methods of manufacture of the photovoltaic devise are also disclosed. | 06-10-2010 |
20100154873 | PHOTOVOLTAIC CELL COMPRISING CCONTACT REGIONS DOPED THROUGH LAMINA - In aspects of the present invention, a lamina is formed having opposing first and second surfaces. Heavily doped contact regions extend from the first surface to the second surface. Generally the lamina is formed by affixing a semiconductor donor body to a receiver element, then cleaving the lamina from the semiconductor donor body wherein the lamina remains affixed to the receiver element. In the present invention, the heavily doped contact regions are formed by doping the semiconductor donor body before cleaving of the lamina. A photovoltaic cell comprising the lamina is then fabricated. By forming the heavily doped contact regions before bonding to the receiver element and cleaving, post-bonding high-temperature steps can be avoided, which may be advantageous. | 06-24-2010 |
20100159630 | METHOD FOR MAKING A PHOTOVOLTAIC CELL COMPRISING CONTACT REGIONS DOPED THROUGH A LAMINA - In aspects of the present invention, a method is disclosed to form a lamina having opposing first and second surfaces. Heavily doped contact regions extend from the first surface to the second surface. Generally the lamina is formed by affixing a semiconductor donor body to a receiver element, then cleaving the lamina from the semiconductor donor body wherein the lamina remains affixed to the receiver element. In the present invention, the heavily doped contact regions are formed by doping the semiconductor donor body before cleaving of the lamina. A photovoltaic cell comprising the lamina is then fabricated. By forming the heavily doped contact regions before bonding to the receiver element and cleaving, post-bonding high-temperature steps can be avoided, which may be advantageous. | 06-24-2010 |
20100224238 | PHOTOVOLTAIC CELL COMPRISING AN MIS-TYPE TUNNEL DIODE - A photovoltaic cell comprising a thin semiconductor lamina is described; the lamina is formed by cleaving from a donor wafer while the wafer is bonded to a receiver element which provides mechanical support. Thus fabrication steps performed following cleaving are advantageously performed at temperatures that will not damage the receiver element. By fabricating a cell comprising an MIS-type tunnel diode, rather than a conventional p-n diode, a high-temperature doping step may be avoided. | 09-09-2010 |
20100229928 | BACK-CONTACT PHOTOVOLTAIC CELL COMPRISING A THIN LAMINA HAVING A SUPERSTRATE RECEIVER ELEMENT - A photovoltaic assembly comprises a thin semiconductor lamina and a receiver element, where the receiver element serves as a superstrate in the completed device. The photovoltaic assembly includes a photovoltaic cell. The photovoltaic cell is a back-contact cell; photocurrent passes into and out of the back surface of the cell, but does not pass through the light-facing surface. The lamina is typically substantially crystalline and has a thickness less than about 100 microns, in some embodiments 10 microns or less. | 09-16-2010 |
20100240169 | METHOD TO MAKE ELECTRICAL CONTACT TO A BONDED FACE OF A PHOTOVOLTAIC CELL - A photovoltaic cell is formed by bonding a donor body to a receiver element and cleaving a thin lamina from the donor body. Electrical contact is made to the bonded surface of the lamina through vias formed in the lamina. In some embodiments the emitter exists only at the bonded surface or only at the cleaved surface face; the emitter does not wrap through the vias between the surfaces. Wiring contacting each of the two surfaces is formed only at the cleaved face, and one set of wiring contacts the bonded surface through conductive material formed in the vias, insulated from the via sidewalls. | 09-23-2010 |
20100290262 | Three dimensional hexagonal matrix memory array - A nonvolatile memory device includes a plurality of nonvolatile memory cells arranged in a substantially hexagonal pattern. The nonvolatile memory cells may be pillar shaped non-volatile memory cells which can be patterned using triple or quadruple exposure lithography or by using a self-assembling layer. | 11-18-2010 |
20100297834 | METHOD FOR REDUCING DIELECTRIC OVERETCH USING A DIELECTRIC ETCH STOP AT A PLANAR SURFACE - A substantially planar surface coexposes conductive or semiconductor features and a dielectric etch stop material. A second dielectric material, different from the dielectric etch stop material, is deposited on the substantially planar surface. A selective etch etches a hole or trench in the second dielectric material, so that the etch stops on the conductive or semiconductor feature and the dielectric etch stop material. In a preferred embodiment the substantially planar surface is formed by filling gaps between the conductive or semiconductor features with a first dielectric such as oxide, recessing the oxide, filling with a second dielectric such as nitride, then planarizing to coexpose the nitride and the conductive or semiconductor features. | 11-25-2010 |
20100302836 | NONVOLATILE MEMORY CELL COMPRISING A DIODE AND A RESISTANCE-SWITCHING MATERIAL - In a novel nonvolatile memory cell formed above a substrate, a diode is paired with a reversible resistance-switching material, preferably a metal oxide or nitride such as, for example, Ni | 12-02-2010 |
20110073175 | PHOTOVOLTAIC CELL COMPRISING A THIN LAMINA HAVING EMITTER FORMED AT LIGHT-FACING AND BACK SURFACES - A photovoltaic cell is described having emitter portions formed at both a light-facing surface and a back surface of the cell. In some embodiments, heavily doped emitter regions extend between the front and back emitter regions, connecting them electrically. Use of this structure is particularly well-adapted to a cell formed by implanting a semiconductor donor body with hydrogen and/or helium ions, affixing the donor body to a receiver element, cleaving a lamina from the donor body, and completing fabrication of a photovoltaic cell comprising the lamina. The emitter portion formed at the unbonded surface may comprise amorphous silicon. The lamina may be thin, for example 10 microns thick or less. | 03-31-2011 |
20110095338 | METHODS OF FORMING PILLARS FOR MEMORY CELLS USING SEQUENTIAL SIDEWALL PATTERNING - The present invention provides apparatus, methods, and systems for fabricating memory structures methods of forming pillars for memory cells using sequential sidewall patterning. The invention includes forming first features from a first template layer disposed above a memory layer stack; forming first sidewall spacers adjacent the first features; forming second features that extend in a first direction in a mask layer by using the first sidewall spacers as a hardmask; depositing a second template layer on the mask layer; forming third features from the second template layer; forming second sidewall spacers adjacent the third features; and forming fourth features that extend in a second direction in the mask layer by using the second sidewall spacers as a hardmask. Numerous additional aspects are disclosed. | 04-28-2011 |
20110095438 | METHODS AND APPARATUS FOR LAYOUT OF THREE DIMENSIONAL MATRIX ARRAY MEMORY FOR REDUCED COST PATTERNING - The present invention provides apparatus, methods, and systems for a memory layer layout for a three-dimensional memory. The memory layer includes a plurality of memory array blocks; a plurality of memory lines coupled to the memory array blocks; and a plurality of zia contact areas for coupling the memory layer to other memory layers in a three-dimensional memory. The memory lines extend from the memory array blocks and are formed using a sidewall defined process. The memory lines have a half pitch dimension smaller than the nominal minimum feature size capability of a lithography tool used in forming the memory lines. The zia contact areas have a dimension that is approximately four times the half pitch dimension of the memory lines. The memory lines are arranged in a pattern adapted to allow a single memory line to intersect a single zia contact area and to provide area between other memory lines for other zia contact areas. Numerous additional aspects are disclosed. | 04-28-2011 |
20110156044 | DENSE ARRAYS AND CHARGE STORAGE DEVICES - There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing. | 06-30-2011 |
20110162688 | ASSYMETRIC SURFACE TEXTURING FOR USE IN A PHOTOVOLTAIC CELL AND METHOD OF MAKING - A novel surface texturing provides improved light-trapping characteristics for photovoltaic cells. The surface is asymmetric and includes shallow slopes at between about 5 and about 30 degrees from horizontal as well as steeper slopes at about 70 degrees or more from horizontal. It is advantageously used as either the front or back surface of a thin semiconductor lamina, for example between about 1 and about 20 microns thick, which comprises at least the base or emitter of a photovoltaic cell. In embodiments of the present invention, the shallow slopes are formed using imprint photolithography. | 07-07-2011 |
20110189840 | METHOD FOR REDUCING DIELECTRIC OVERETCH WHEN MAKING CONTACT TO CONDUCTIVE FEATURES - In a first aspect, a method is provided that includes: forming a plurality of conductive or semiconductive features above a first dielectric material; depositing a second dielectric material above the conductive or semiconductive features; etching a void in the second dielectric material, wherein the etch is selective between the first and the second dielectric material and the etch stops on the first dielectric material; and exposing a portion of the conductive or semiconductive features. Numerous other aspects are provided. | 08-04-2011 |
20110306177 | METHOD FOR REDUCING DIELECTRIC OVERETCH USING A DIELECTRIC ETCH STOP AT A PLANAR SURFACE - A method is described for reducing dielectric overetch. The method includes: ( | 12-15-2011 |
20120167969 | Zener Diode Within a Diode Structure Providing Shunt Protection - A structure to provide a Zener diode to avoid shunt formation is disclosed. An undoped or lightly doped monocrystalline thin semiconductor lamina is cleaved from a donor body which is not permanently affixed to a support element. The lamina may be annealed at high temperature to remove damage from a prior implant. At least one aperture is formed through the lamina, either due to flaws in the cleaving process, or intentionally following cleaving. Heavily doped amorphous silicon layers having opposite conductivity types are deposited on opposite faces of the lamina, one forming the emitter and one a base contact to a photovoltaic cell, while the lamina forms the base of the cell. The heavily doped layers contact in the aperture, forming a Zener diode. This Zener diode prevents formation of shunts, and may behave as a bypass diode if the cell is placed under heavy reverse bias, as when one cell in a series string is shaded while the rest of the string is exposed to sun. | 07-05-2012 |
20120187361 | Non-Volatile Memory Arrays Comprising Rail Stacks With A Shared Diode Component Portion For Diodes Of Electrically Isolated Pillars - An integrated circuit including vertically oriented diode structures between conductors and methods of fabricating the same are provided. Two-terminal devices such as passive element memory cells can include a diode steering element in series with an antifuse and/or other state change element. The devices are formed using pillar structures at the intersections of upper and lower sets of conductors. The height of the pillar structures are reduced by forming part of the diode for each pillar in a rail stack with one of the conductors. A diode in one embodiment can include a first diode component of a first conductivity type and a second diode component of a second conductivity type. A portion of one of the diode components is divided into first and second portions with one on the portions being formed in the rail stack where it is shared with other diodes formed using pillars at the rail stack. | 07-26-2012 |
20120192935 | BACK-CONTACT PHOTOVOLTAIC CELL COMPRISING A THIN LAMINA HAVING A SUPERSTRATE RECEIVER ELEMENT - A method to fabricate a photovoltaic device includes forming first and second contact regions at the first surface of a semiconductor donor body. A cleave plane may be formed by implanting ions into the donor body, and a lamina that includes the contact regions is cleaved from the donor body at the cleave plane. The first surface of the lamina may be contacted with a temporary support and fabricated into a photovoltaic device, wherein the lamina comprises the base of the photovoltaic device. | 08-02-2012 |
20120208317 | Intermetal Stack for Use in a Photovoltaic Cell - A donor silicon wafer may be bonded to a substrate and a lamina cleaved from the donor wafer. A photovoltaic cell may be formed from the lamina bonded to the substrate. An intermetal stack is described that is optimized for use in such a cell. The intermetal stack may include a transparent conductive oxide layer serving as a quarter-wave plate, a low resistance layer, an adhesion layer to help adhesion to the receiver element, and may also include a barrier layer to prevent or impede unwanted diffusion within the stack. | 08-16-2012 |
20120220068 | Method to Form a Device by Constructing a Support Element on a Thin Semiconductor Lamina - A semiconductor assembly is described in which a support element is constructed on a surface of a semiconductor lamina. Following formation of the thin lamina, which may have a thickness about 50 microns or less, the support element is formed, for example by plating, or by application of a precursor and curing in situ, resulting in a support element which may be, for example, metal, ceramic, polymer, etc. This is in contrast to pre-formed support element which is affixed to the lamina following its formation, or to a donor wafer from which the lamina is subsequently cleaved. | 08-30-2012 |
20120223380 | DENSE ARRAYS AND CHARGE STORAGE DEVICES - There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing. | 09-06-2012 |
20130087188 | Photovoltaic Cell Comprising A Thin Lamina Having A Rear Junction And Method Of Making - Fabrication of a photovoltaic cell comprising a thin semiconductor lamina may require additional processing after the semiconductor lamina is bonded to a receiver. To minimize high-temperature steps after bonding, the p-n junction is formed at the back of the cell, at the bonded surface. In some embodiments, the front surface of the semiconductor lamina is not doped or is locally doped using low-temperature methods. The base resistivity of the photovoltaic cell may be reduced, allowing a front surface field to be reduced or omitted. | 04-11-2013 |
20130121061 | NONVOLATILE MEMORY CELL COMPRISING A DIODE AND A RESISTANCE-SWITCHING MATERIAL - A method is provided for programming a memory cell in a memory array. The memory cell includes a resistivity-switching layer of a metal oxide or nitride compound, and the metal oxide or nitride compound includes exactly one metal. The method includes programming the memory cell by changing the resistivity-switching layer from a first resistivity state to a second programmed resistivity state, wherein the second programmed resistivity state stores a data state of the memory cell. Numerous other aspects are provided. | 05-16-2013 |
20130183790 | ASYMMETRIC SURFACE TEXTURING FOR USE IN A PHOTOVOLTAIC CELL AND METHOD OF MAKING - A novel surface texturing provides improved light-trapping characteristics for photovoltaic cells. The surface is asymmetric and includes shallow slopes at between about 5 and about 30 degrees from horizontal as well as steeper slopes at about 70 degrees or more from horizontal. It is advantageously used as either the front or back surface of a thin semiconductor lamina, for example between about 1 and about 20 microns thick, which comprises at least the base or emitter of a photovoltaic cell. In embodiments of the present invention, the shallow slopes are formed using imprint photolithography. | 07-18-2013 |
20130200497 | MULTI-LAYER METAL SUPPORT - The invention provides a method of forming an electronic device from a lamina that has a coefficient of thermal expansion that is matched or nearly matched to a constructed metal support. In some embodiments the method comprises implanting the top surface of a donor body with an ion dosage to form a cleave plane followed by exfoliating a lamina from the donor body. After exfoliating the lamina, a flexible metal support that has a coefficient of thermal expansion with a value that is within 10% of the value of the coefficient of thermal expansion of the lamina is constructed on the lamina. In some embodiments the coefficients of thermal expansion of the metal support and the lamina are within 10% or within 5% of each other between the temperatures of 500 and 1050° C. | 08-08-2013 |
20130203205 | Method for Fabricating Backside-Illuminated Sensors - A method for fabricating a backside-illuminated sensor includes providing a thin film semiconductor lamina having a first conductivity, and forming a doped region having a second conductivity within the lamina and at a front surface of the lamina. The lamina may be provided as a free-standing lamina, or may be provided as a semiconductor donor body from which the lamina is cleaved. An electrical connection is formed to the doped region. A temporary carrier is contacted to the back surface of the semiconductor and later removed. A backside-illuminated sensor is fabricated from the semiconductor lamina, in which the thickness of the semiconductor lamina remains substantially unchanged during the fabrication process. | 08-08-2013 |
20130295764 | METHOD FOR REDUCING DIELECTRIC OVERETCH WHEN MAKING CONTACT TO CONDUCTIVE FEATURES - A method is provided that includes forming conductive or semiconductive features above a first dielectric material, depositing a second dielectric material above the conductive or semiconductive features, etching a void in the second dielectric material, wherein the etch stops on the first dielectric material, and exposing a portion of the conductive or semiconductive features. Numerous other aspects are provided | 11-07-2013 |
20140030836 | Silicon Carbide Lamina - A method of fabricating an electronic device includes providing a silicon carbide or diamond-like carbon donor body and implanting ions into a first surface of the donor body to define a cleave plane. After implanting, an epitaxial layer is formed on the first surface, and a temporary carrier is coupled to the epitaxial layer. A lamina is cleaved from the donor body at the cleave plane, and the temporary carrier is removed from the lamina. In some embodiments a light emitting diode or a high electron mobility transistor is fabricated from the lamina and epitaxial layer. | 01-30-2014 |
20140038329 | EPITAXIAL GROWTH ON THIN LAMINA - Methods and apparatus are provided for forming an electronic device from a lamina and an epitaxially grown semiconductor material. The method includes providing a donor body comprising a top surface, epitaxially growing a semiconductor material on the top surface and implanting the top surface of the donor body with an ion dosage to form a cleave plane. After implantation, a lamina may be exfoliated from the donor body, wherein the top surface of the donor body becomes a first surface of the lamina. Exfoliating the lamina forms a second surface of the lamina, wherein the first surface is opposite the second surface. A metal support may be constructed on the lamina. | 02-06-2014 |
20140133074 | MOBILE ELECTRONIC DEVICE COMPRISING AN ULTRATHIN SAPPHIRE COVER PLATE - An electronic device comprising a cover plate is disclosed. The cover plate comprises one or more sapphire layers having a thickness of less than 50 microns. Also disclosed are methods for preparing these ultrathin sapphire layers using an ion implantation/exfoliation method. | 05-15-2014 |
20140166968 | NONVOLATILE MEMORY CELL COMPRISING A DIODE AND A RESISTANCE-SWITCHING MATERIAL - A nonvolatile memory cell is provided that includes a diode and a reversible resistance-switching element that includes a resistance-switching metal oxide or nitride, the metal oxide or nitride including only one metal. Numerous other aspects are provided. | 06-19-2014 |
20140241031 | DIELECTRIC-BASED MEMORY CELLS HAVING MULTI-LEVEL ONE-TIME PROGRAMMABLE AND BI-LEVEL REWRITEABLE OPERATING MODES AND METHODS OF FORMING THE SAME - In some aspects, a memory cell is provided that includes a steering element and a memory element. The memory element includes a first conductive material layer, a first dielectric material layer disposed above the first conductive material layer, a second conductive material layer disposed above the first dielectric material layer, a second dielectric material layer disposed above the second conductive material layer, and a third conductive material layer disposed above the second dielectric material layer. One or both of the first conductive material layer and the second conductive material layer comprise a stack of a metal material layer and a highly doped semiconductor material layer. Numerous other aspects are provided. | 08-28-2014 |
20140328105 | METHODS AND APPARATUS FOR LAYOUT OF THREE DIMENSIONAL MATRIX ARRAY MEMORY FOR REDUCED COST PATTERNING - Apparatus, methods, and systems are provided for a memory layer layout for a three-dimensional memory. The memory layer includes a plurality of memory array blocks; a plurality of memory lines coupled thereto; and a plurality of zia contact areas for coupling the memory layer to other memory layers in a three-dimensional memory. The memory lines extend from the memory array blocks, are formed using a sidewall defined process, and have a half pitch dimension smaller than the nominal minimum feature size capability of a lithography tool used in forming the memory lines. The zia contact areas have a dimension that is approximately four times the half pitch dimension of the memory lines. The memory lines are arranged in a pattern that allows a single memory line to intersect a single zia contact area and to provide area between other memory lines for other zia contact areas. Other aspects are disclosed. | 11-06-2014 |