| Patent application number | Description | Published |
|---|
| 20080211100 | METHOD AND STRUCTURE FOR REDUCING CONTACT RESISTANCE BETWEEN SILICIDE CONTACT AND OVERLYING METALLIZATION - A semiconductor structure in which the contact resistance in the contact opening is reduced as well as a method of forming the same are provided. This is achieved in the present invention by replacing conventional contact metallurgy, such as tungsten, or a metal silicide, such as Ni silicide or Cu silicide, with a metal germanide-containing contact material. The term “metal germanide-containing” is used in the present application to denote a pure metal germanide (i.e., MGe alloy) or a metal germanide that includes Si (i.e., MSiGe alloy). | 09-04-2008 |
| 20080217780 | ELIMINATING METAL-RICH SILICIDES USING AN AMORPHOUS Ni ALLOY SILICIDE STRUCTURE - The present invention provides a method for producing thin nickel (Ni) monosilicide or NiSi films (having a thickness on the order of about 30 nm or less), as contacts in CMOS devices wherein an amorphous Ni alloy silicide layer is formed during annealing which eliminates (i.e., completely by-passing) the formation of metal-rich silicide layers. By eliminating the formation of the metal-rich silicide layers, the resultant NiSi film formed has improved surface roughness as compared to a NiSi film formed from a metal-rich silicide phase. The method of the present invention also forms Ni monosilicide films without experiencing any dependence of the dopant type concentration within the Si-containing substrate that exists with the prior art NiSi films. | 09-11-2008 |
| 20080217781 | ELIMINATING METAL-RICH SILICIDES USING AN AMORPHOUS Ni ALLOY SILICIDE STRUCTURE - The present invention provides a method for producing thin nickel (Ni) monosilicide or NiSi films (having a thickness on the order of about 30 nm or less), as contacts in CMOS devices wherein an amorphous Ni alloy silicide layer is formed during annealing which eliminates (i.e., completely by-passing) the formation of metal-rich silicide layers. By eliminating the formation of the metal-rich silicide layers, the resultant NiSi film formed has improved surface roughness as compared to a NiSi film formed from a metal-rich silicide phase. The method of the present invention also forms Ni monosilicide films without experiencing any dependence of the dopant type concentration within the Si-containing substrate that exists with the prior art NiSi films. | 09-11-2008 |
| 20080220581 | OPTO-THERMAL ANNEALING METHODS FOR FORMING METAL GATE AND FULLY SILICIDED GATE-FIELD EFFECT TRANSISTORS - An opto-thermal annealing method for forming a field effect transistor uses a reflective metal gate so that electrical properties of the metal gate and also interface between the metal gate and a gate dielectric are not compromised when opto-thermal annealing a source/drain region adjacent the metal gate. Another opto-thermal annealing method may be used for simultaneously opto-thermally annealing: (1) a silicon layer and a silicide forming metal layer to form a fully silicided gate; and (2) a source/drain region to form an annealed source/drain region. An additional opto-thermal annealing method may use a thermal insulator layer in conjunction with a thermal absorber layer to selectively opto-thermally anneal a silicon layer and a silicide forming metal layer to form a fully silicide gate. | 09-11-2008 |
| 20080220606 | SELF-ALIGNED METAL TO FORM CONTACTS TO Ge CONTAINING SUBSTRATES AND STRUCTURE FORMED THEREBY - A method for forming germano-silicide contacts atop a Ge-containing layer that is more resistant to etching than are conventional silicide contacts that are formed from a pure metal is provided. The method of the present invention includes first providing a structure which comprises a plurality of gate regions located atop a Ge-containing substrate having source/drain regions therein. After this step of the present invention, a Si-containing metal layer is formed atop the said Ge-containing substrate. In areas that are exposed, the Ge-containing substrate is in contact with the Si-containing metal layer. Annealing is then performed to form a germano-silicide compound in the regions in which the Si-containing metal layer and the Ge-containing substrate are in contact; and thereafter, any unreacted Si-containing metal layer is removed from the structure using a selective etch process. In some embodiments, an additional annealing step can follow the removal step. The method of the present invention provides a structure having a germano-silicide contact layer atop a Ge-containing substrate, wherein the germano-silicide contact layer contains more Si than the underlying Ge-containing substrate. | 09-11-2008 |
| 20080227259 | SELF-ALIGNED PROCESS FOR NANOTUBE/NANOWIRE FETs - A complementary metal oxide semiconductor (CMOS) device, e.g., a field effect transistor (FET), that includes at least one one-dimensional nanostructure that is typically a carbon-based nanomaterial, as the device channel, and a metal carbide contact that is self-aligned with the gate region of the device is described. The present invention also provides a method of fabricating such a CMOS device. | 09-18-2008 |
| 20080227283 | SELF-ALIGNED METAL TO FORM CONTACTS TO Ge CONTAINING SUBSTRATES AND STRUCTURE FORMED THEREBY - A method for forming gennano-silicide contacts atop a Ge-containing layer that is more resistant to etching than are conventional silicide contacts that are formed from a pure metal is provided. The method of the present invention includes first providing a structure which comprises a plurality of gate regions located atop a Ge-containing substrate having source/drain regions therein. After this step of the present invention, a Si-containing metal layer is formed atop the said Ge-containing substrate. In areas that are exposed, the Ge-containing substrate is in contact with the Si-containing metal layer. Annealing is then performed to form a germano-silicide compound in the regions in which the Si-containing metal layer and the Ge-containing substrate are in contact; and thereafter, any unreacted Si-containing metal layer is removed from the structure using a selective etch process. In some embodiments, an additional annealing step can follow the removal step. The method of the present invention provides a structure having a germano-silicide contact layer atop a Ge-containing substrate, wherein the germano-silicide contact layer contains more Si than the underlying Ge-containing substrate. | 09-18-2008 |
| 20080246120 | REDUCTION OF SILICIDE FORMATION TEMPERATURE ON SiGe CONTAINING SUBSTRATES - A method that solves the increased nucleation temperature that is exhibited during the formation of cobalt disilicides in the presence of Ge atoms is provided. The reduction in silicide formation temperature is achieved by first providing a structure including a Co layer including at least Ni, as an additive element, on top of a SiGe containing substrate. Next, the structure is subjected to a self-aligned silicide process which includes a first anneal, a selective etching step and a second anneal to form a solid solution of (Co, Ni) disilicide on the SiGe containing substrate. The Co layer including at least Ni can comprise an alloy layer of Co and Ni, a stack of Ni/Co or a stack of Co/Ni. A semiconductor structure including the solid solution of (Co, Ni) disilicide on the SiGe containing substrate is also provided. | 10-09-2008 |
| 20080268600 | MOSFET STRUCTURE WITH MULTIPLE SELF-ALIGNED SILICIDE CONTACTS - A metal oxide semiconductor field effect transistor (MOSFET) structure that includes multiple and distinct self-aligned silicide contacts and methods of fabricating the same are provided. The MOSFET structure includes at least one metal oxide semiconductor field effect transistor having a gate conductor including a gate edge located on a surface of a Si-containing substrate; a first inner silicide having an edge that is substantially aligned to the gate edge of the at least one metal oxide semiconductor field effect transistor; and a second outer silicide located adjacent to the first inner silicide. In accordance with the present invention, the second outer silicide has second thickness is greater than the first thickness of the first inner silicide. Moreover, the second outer silicide has a resistivity that is lower than the resistivity of the first inner silicide. | 10-30-2008 |
| 20080274611 | METHOD AND PROCESS FOR FORMING A SELF-ALIGNED SILICIDE CONTACT - The present invention provides a method for forming a self-aligned Ni alloy silicide contact. The method of the present invention begins by first depositing a conductive Ni alloy with Pt and optionally at least one of the following metals Pd, Rh, Ti, V, Cr, Zr, Nb, Mo, Hf, Ta, W or Re over an entire semiconductor structure which includes at least one gate stack region. An oxygen diffusion barrier comprising, for example, Ti, TiN or W is deposited over the structure to prevent oxidation of the metals. An annealing step is then employed to cause formation of a NiSi, PtSi contact in regions in which the metals are in contact with silicon. The metal that is in direct contact with insulating material such as SiO | 11-06-2008 |
| 20080299720 | STABILIZATION OF Ni MONOSILICIDE THIN FILMS IN CMOS DEVICES USING IMPLANTATION OF IONS BEFORE SILICIDATION - A method for forming a stabilized metal silicide film, e.g., contact (source/drain or gate), that does not substantially agglomerate during subsequent thermal treatments, is provided. In the present invention, ions that are capable of attaching to defects within the Si-containing layer are implanted into the Si-containing layer prior to formation of metal silicide. The implanted ions stabilize the film, because the implants were found to substantially prevent agglomeration or at least delay agglomeration to much higher temperatures than in cases in which no implants were used. | 12-04-2008 |
| 20090155996 | PLATING SEED LAYER INCLUDING AN OXYGEN/NITROGEN TRANSITION REGION FOR BARRIER ENHANCEMENT - An interconnect structure which includes a plating seed layer that has enhanced conductive material, preferably, Cu, diffusion properties is provided that eliminates the need for utilizing separate diffusion and seed layers. Specifically, the present invention provides an oxygen/nitrogen transition region within a plating seed layer for interconnect metal diffusion enhancement. The plating seed layer may include Ru, Ir or alloys thereof, and the interconnect conductive material may include Cu, Al, AlCu, W, Ag, Au and the like. Preferably, the interconnect conductive material is Cu or AlCu. In more specific terms, the present invention provides a single seeding layer which includes an oxygen/nitrogen transition region sandwiched between top and bottom seed regions. The presence of the oxygen/nitrogen transition region within the plating seed layer dramatically enhances the diffusion barrier resistance of the plating seed. | 06-18-2009 |
| 20090309228 | METHOD FOR FORMING SELF-ALIGNED METAL SILICIDE CONTACTS - The present invention relates to a method for forming self-aligned metal silicide contacts over at least two silicon-containing semiconductor regions that are spaced apart from each other by an exposed dielectric region. Preferably, each of the self-aligned metal silicide contacts so formed comprises at least nickel silicide and platinum silicide with a substantially smooth surface, and the exposed dielectric region is essentially free of metal and metal silicide. More preferably, the method comprises the steps of nickel or nickel alloy deposition, low-temperature annealing, nickel etching, high-temperature annealing, and aqua regia etching. | 12-17-2009 |
| 20100003800 | BIPOLAR TRANSISTOR WITH SILICIDED SUB-COLLECTOR - Embodiments of the invention provide a method of fabricating a semiconductor device. The method includes defining a sub-collector region in a layer of doped semiconductor material; forming an active region, a dielectric region, and a reach-through region on top of the layer of doped semiconductor material with the dielectric region separating the active region from the reach-through region; and siliciding the reach-through region and a portion of the sub-collector region to form a partially silicided conductive pathway. A semiconductor device made thereby is also provided. | 01-07-2010 |
| 20100304563 | MOSFET STRUCTURE WITH MULTIPLE SELF-ALIGNED SILICIDE CONTACTS - A metal oxide semiconductor field effect transistor (MOSFET) structure that includes multiple and distinct self-aligned silicide contacts and methods of fabricating the same are provided. The MOSFET structure includes at least one metal oxide semiconductor field effect transistor having a gate conductor including a gate edge located on a surface of a Si-containing substrate; a first inner silicide having an edge that is substantially aligned to the gate edge of the at least one metal oxide semiconductor field effect transistor; and a second outer silicide located adjacent to the first inner silicide. In accordance with the present invention, the second outer silicide has second thickness is greater than the first thickness of the first inner silicide. Moreover, the second outer silicide has a resistivity that is lower than the resistivity of the first inner silicide. | 12-02-2010 |
| 20110227156 | SOI Schottky Source/Drain Device Structure to Control Encroachment and Delamination of Silicide - A Schottky field effect transistor is provided that includes a substrate having a layer of semiconductor material atop a dielectric layer, wherein the layer of semiconductor material has a thickness of less than 10.0 nm. A gate structure is present on the layer of semiconductor material. Raised source and drain regions comprised of a metal semiconductor alloy are present on the layer of semiconductor material on opposing sides of the gate structure. The raised source and drain regions are Schottky source and drain regions. In one embodiment, a first portion of the Schottky source and drain regions that is adjacent to a channel region of the Schottky field effect transistor contacts the dielectric layer, and a non-reacted semiconductor material is present between a second portion of the Schottky source and drain regions and the dielectric layer. | 09-22-2011 |
| 20110230017 | Method for Forming an SOI Schottky Source/Drain Device to Control Encroachment and Delamination of Silicide - A method of fabricating a Schottky field effect transistor is provided that includes providing a substrate having at least a first semiconductor layer overlying a dielectric layer, wherein the first semiconductor layer has a thickness of less than 10.0 nm. A gate structure is formed directly on the first semiconductor layer. A raised semiconductor material is selectively formed on the first semiconductor layer adjacent to the gate structure. The raised semiconductor material is converted into Schottky source and drain regions composed of a metal semiconductor alloy. A non-reacted semiconductor material is present between the Schottky source and drain regions and the dielectric layer. | 09-22-2011 |
| 20110253980 | Source/Drain Technology for the Carbon Nano-tube/Graphene CMOS with a Single Self-Aligned Metal Silicide Process - Electronic devices having carbon-based materials and techniques for making contact to carbon-based materials in electronic devices are provided. In one aspect, a device is provided having a carbon-based material; and at least one electrical contact to the carbon-based material comprising a metal silicide, germanide or germanosilicide. The carbon-based material can include graphene or carbon nano-tubes. The device can further include a segregation region, having an impurity, separating the carbon-based material from the metal silicide, germanide or germanosilicide, wherein the impurity has a work function that is different from a work function of the metal silicide, germanide or germanosilicide. A method for fabricating the device is also provided. | 10-20-2011 |
| 20110256675 | SELF-ALIGNED PROCESS FOR NANOTUBE/NANOWIRE FETs - A complementary metal oxide semiconductor (CMOS) device, e.g., a field effect transistor (FET), that includes at least one one-dimensional nanostructure that is typically a carbon-based nanomaterial, as the device channel, and a metal carbide contact that is self-aligned with the gate region of the device is described. The present invention also provides a method of fabricating such a CMOS device. | 10-20-2011 |
| 20110260252 | USE OF EPITAXIAL NI SILICIDE - An epitaxial Ni silicide film that is substantially non-agglomerated at high temperatures, and a method for forming the epitaxial Ni silicide film, is provided. The Ni silicide film of the present disclosure is especially useful in the formation of ETSOI (extremely thin silicon-on-insulator) Schottky junction source/drain FETs. The resulting epitaxial Ni silicide film exhibits improved thermal stability and does not agglomerate at high temperatures. | 10-27-2011 |
| 20110309508 | Method and Structure of Forming Silicide and Diffusion Barrier Layer With Direct Deposited Film on Silicon - A semiconductor device or a photovoltaic cell having a contact structure, which includes a silicon (Si) substrate; a metal alloy layer deposited on the silicon substrate; a metal silicide layer and a diffusion layer formed simultaneously from thermal annealing the metal alloy layer; and a metal layer deposited on the metal silicide and barrier layers. | 12-22-2011 |
| 20110316565 | SCHOTTKY JUNCTION SI NANOWIRE FIELD-EFFECT BIO-SENSOR/MOLECULE DETECTOR - A Schottky junction silicon nanowire field-effect biosensor/molecule detector with a nanowire thickness of 10 nanometer or less and an aligned source/drain workfunction for increased sensitivity. The nanowire channel is coated with a surface treatment to which a molecule of interest absorbs, which modulates the conductivity of the channel between the Schottky junctions sufficiently to qualitatively and quantitatively measure the presence and amount of the molecule. | 12-29-2011 |
| 20120098042 | SEMICONDUCTOR DEVICE WITH REDUCED JUNCTION LEAKAGE AND AN ASSOCIATED METHOD OF FORMING SUCH A SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device having a p-n junction with reduced junction leakage in the presence of metal silicide defects that extend to the junction and a method of forming the device. Specifically, a semiconductor layer having a p-n junction is formed. A metal silicide layer is formed on the semiconductor layer and a dopant is implanted into the metal silicide layer. An anneal process is performed causing the dopant to migrate toward the metal silicide-semiconductor layer interface such that the peak concentration of the dopant will be within a portion of the metal silicide layer bordering the metal silicide-semiconductor layer interface and encompassing the defects. As a result, the silicide to silicon contact is effectively engineered to increase the Schottky barrier height at the defect, which in turn drastically reduces any leakage that would otherwise occur, when the p-n junction is in reverse polarity. | 04-26-2012 |
| 20120132989 | MULTIGATE STRUCTURE FORMED WITH ELECTROLESS METAL DEPOSITION - A multigate structure which comprises a semiconductor substrate; an ultra-thin silicon or carbon bodies of less than 20 nanometers thick located on the substrate; an electrolessly deposited metallic layer selectively located on the side surfaces and top surfaces of the ultra-thin silicon or carbon bodies and selectively located on top of the multigate structures to make electrical contact with the ultra-thin silicon or carbon bodies and to minimize parasitic resistance, and wherein the ultra-thin silicon or carbon bodies and metallic layer located thereon form source and drain regions is provided along with a process to fabricate the structure. | 05-31-2012 |
| 20120181697 | METHOD TO CONTROL METAL SEMICONDUCTOR MICRO-STRUCTURE - A method of forming a metal semiconductor alloy that includes forming an intermixed metal semiconductor region to a first depth of a semiconductor substrate without thermal diffusion. The intermixed metal semiconductor region is annealed to form a textured metal semiconductor alloy. A second metal layer is formed on the textured metal semiconductor alloy. The second metal layer on the textured metal semiconductor alloy is then annealed to form a metal semiconductor alloy contact, in which metal elements from the second metal layer are diffused through the textured metal semiconductor alloy to provide a templated metal semiconductor alloy. The templated metal semiconductor alloy includes a grain size that is greater than 2× for the metal semiconductor alloy, which has a thickness ranging from 15 nm to 50 nm. | 07-19-2012 |
| 20120187460 | METHOD FOR FORMING METAL SEMICONDUCTOR ALLOYS IN CONTACT HOLES AND TRENCHES - A method of forming a semiconductor device is provided that includes forming a first metal semiconductor alloy on a semiconductor containing surface, forming a dielectric layer over the first metal semiconductor alloy, forming an opening in the dielectric layer to provide an exposed surface the first metal semiconductor alloy, and forming a second metal semiconductor alloy on the exposed surface of the first metal semiconductor alloy. In another embodiment, the method includes forming a gate structure on a channel region of a semiconductor substrate, forming a dielectric layer over at least a source region and a drain region, forming an opening in the dielectric layer to provide an exposed surface the semiconductor substrate, forming a first metal semiconductor alloy on the exposed surface of the semiconductor substrate, and forming a second metal semiconductor alloy on the first metal semiconductor alloy. | 07-26-2012 |
| 20120196424 | METHOD OF FABRICATING A DEEP TRENCH (DT) METAL-INSULATOR-METAL (MIM) CAPACITOR - A method includes providing an SOI substrate including a layer of silicon disposed atop a layer of an oxide, the layer of an oxide being disposed atop the semiconductor substrate; forming a deep trench having a sidewall extending through the layer of silicon and the layer of an oxide and into the substrate; depositing a continuous spacer on the sidewall to cover the layer of silicon, the layer of an oxide and a part of the substrate; depositing a first conformal layer of a conductive material throughout the inside of the deep trench; creating a silicide within the deep trench in regions extending through the sidewall into an uncovered part of the substrate; removing the first conformal layer from the continuous spacer; removing the continuous spacer; depositing a layer of a high k dielectric material throughout the inside of the deep trench, and depositing a second conformal layer of a conductive material onto the layer of a high-k dielectric material. | 08-02-2012 |
| 20120298965 | MULTIGATE STRUCTURE FORMED WITH ELECTROLESS METAL DEPOSITION - A multigate structure which comprises a semiconductor substrate; an ultra-thin silicon or carbon bodies of less than 20 nanometers thick located on the substrate; an electrolessly deposited metallic layer selectively located on the side surfaces and top surfaces of the ultra-thin silicon or carbon bodies and selectively located on top of the multigate structures to make electrical contact with the ultra-thin silicon or carbon bodies and to minimize parasitic resistance, and wherein the ultra-thin silicon or carbon bodies and metallic layer located thereon form source and drain regions is provided along with a process to fabricate the structure. | 11-29-2012 |
| 20130001784 | METHOD AND STRUCTURE OF FORMING SILICIDE AND DIFFUSION BARRIER LAYER WITH DIRECT DEPOSITED FILM ON SI - A semiconductor device or a photovoltaic cell having a contact structure, which includes a silicon (Si) substrate; a metal alloy layer deposited on the silicon substrate; a metal silicide layer and a diffusion layer formed simultaneously from thermal annealing the metal alloy layer; and a metal layer deposited on the metal silicide and barrier layers. | 01-03-2013 |
| 20130012020 | USE OF EPITAXIAL NI SILICIDE - An epitaxial Ni silicide film that is substantially non-agglomerated at high temperatures, and a method for forming the epitaxial Ni silicide film, is provided. The Ni silicide film of the present disclosure is especially useful in the formation of ETSOI (extremely thin silicon-on-insulator) Schottky junction source/drain FETs. The resulting epitaxial Ni silicide film exhibits improved thermal stability and does not agglomerate at high temperatures. | 01-10-2013 |
| 20130040454 | Annealing Copper Interconnects - A method for modifying the chemistry or microstructure of silicon-based technology via an annealing process is provided. The method includes depositing a reactive material layer within a selected proximity to an interconnect, igniting the reactive material layer, and annealing the interconnect via heat transferred from the ignited reactive material layer. The method can also be implemented in connection with a silicide/silicon interface as well as a zone of silicon-based technology. | 02-14-2013 |
| 20130241007 | USE OF BAND EDGE GATE METALS AS SOURCE DRAIN CONTACTS - A method includes providing a semiconductor substrate having intentionally doped surface regions, the intentionally doped surface regions corresponding to locations of a source and a drain of a transistor; depositing a layer a band edge gate metal onto a gate insulator layer in a gate region of the transistor while simultaneously depositing the band edge gate metal onto the surface of the semiconductor substrate to be in contact with the intentionally doped surface regions; and depositing a layer of contact metal over the band edge gate metal in the gate region and in the locations of the source and the drain. The band edge gate metal in the source/drain regions reduces a Schottky barrier height of source/drain contacts of the transistor and serves to reduce contact resistance. A transistor fabricated in accordance with the method is also described. | 09-19-2013 |
| 20130241008 | Use of Band Edge Gate Metals as Source Drain Contacts - A device includes a gate stack formed over a channel in a semiconductor substrate. The gate stack includes a layer of gate insulator material, a layer of gate metal overlying the layer of gate insulator material, and a layer of contact metal overlying the layer band edge gate metal. The device further includes source and drain contacts adjacent to the channel. The source and drain contacts each include a layer of the gate metal that overlies and is in direct electrical contact with a doped region of the semiconductor substrate, and a layer of contact metal that overlies the layer of gate metal. | 09-19-2013 |
| 20130249099 | Techniques to Form Uniform and Stable Silicide - In one aspect, a method of fabricating a metal silicide includes the following steps. A semiconductor material selected from the group consisting of silicon and silicon germanium is provided. A metal(s) is deposited on the semiconductor material. A first anneal is performed at a temperature and for a duration sufficient to react the metal(s) with the semiconductor material to form an amorphous layer including an alloy formed from the metal(s) and the semiconductor material, wherein the temperature at which the first anneal is performed is below a temperature at which a crystalline phase of the alloy is formed. An etch is used to selectively remove unreacted portions of the metal(s). A second anneal is performed at a temperature and for a duration sufficient to crystallize the alloy thus forming the metal silicide. A device contact and a method of fabricating a FET device are also provided. | 09-26-2013 |
| 20130267090 | METHOD TO CONTROL METAL SEMICONDUCTOR MICRO-STRUCTURE - A method of forming a metal semiconductor alloy that includes forming an intermixed metal semiconductor region to a first depth of a semiconductor substrate without thermal diffusion. The intermixed metal semiconductor region is annealed to form a textured metal semiconductor alloy. A second metal layer is formed on the textured metal semiconductor alloy. The second metal layer on the textured metal semiconductor alloy is then annealed to form a metal semiconductor alloy contact, in which metal elements from the second metal layer are diffused through the textured metal semiconductor alloy to provide a templated metal semiconductor alloy. The templated metal semiconductor alloy includes a grain size that is greater than 2× for the metal semiconductor alloy, which has a thickness ranging from 15 nm to 50 nm. | 10-10-2013 |
| 20130334693 | RAISED SILICIDE CONTACT - A method for forming a raised silicide contact, the method including depositing a layer of silicon using a gas cluster implant technique which accelerates clusters of silicon atoms causing them to penetrate a surface oxide on a top surface of the silicide; heating the silicide including the silicon layer to a temperature from about 300° C. to about 950° and holding the temperature for about 0.1 miliseconds to about 600 seconds in an inert atmosphere causing silicon from the layer of silicon to react with the remaining silicide partially formed in the silicon containing substrate; and forming a raised silicide from the layer of silicon, wherein the thickness of the raised silicide is greater than the thickness of the silicide and the raised silicide protrudes above a top surface of the silicon containing substrate. | 12-19-2013 |
| 20140073130 | FORMING NICKEL-PLATINUM ALLOY SELF-ALIGNED SILICIDE CONTACTS - A method of performing a silicide contact process comprises a forming a nickel-platinum alloy (NiPt) layer over a semiconductor device structure; performing a first rapid thermal anneal (RTA) so as to react portions of the NiPt layer in contact with semiconductor regions of the semiconductor device structure, thereby forming metal rich silicide regions; performing a first wet etch to remove at least a nickel constituent of unreacted portions of the NiPt layer; performing a second wet etch using a dilute Aqua Regia treatment comprising nitric acid (HNO | 03-13-2014 |
| 20140103457 | FIELD EFFECT TRANSISTOR DEVICE HAVING A HYBRID METAL GATE STACK - A semiconductor device including a gate structure present on a channel portion of a semiconductor substrate and at least one gate sidewall spacer adjacent to the gate structure. In one embodiment, the gate structure includes a work function metal layer present on a gate dielectric layer, a metal semiconductor alloy layer present on a work function metal layer, and a dielectric capping layer present on the metal semiconductor alloy layer. The at least one gate sidewall spacer and the dielectric capping layer may encapsulate the metal semiconductor alloy layer within the gate structure. | 04-17-2014 |
| 20140106531 | FIELD EFFECT TRANSISTOR DEVICE HAVING A HYBRID METAL GATE STACK - A semiconductor device including a gate structure present on a channel portion of a semiconductor substrate and at least one gate sidewall spacer adjacent to the gate structure. In one embodiment, the gate structure includes a work function metal layer present on a gate dielectric layer, a metal semiconductor alloy layer present on a work function metal layer, and a dielectric capping layer present on the metal semiconductor alloy layer. The at least one gate sidewall spacer and the dielectric capping layer may encapsulate the metal semiconductor alloy layer within the gate structure. | 04-17-2014 |
| 20140210011 | Dual Silicide Process - In one aspect, a method for silicidation includes the steps of: (a) providing a wafer having at least one first active area and at least one second active area defined therein; (b) masking the first active area with a first hardmask; (c) doping the second active area; (d) forming a silicide in the second active area, wherein the first hardmask serves to mask the first active area during both the doping step (c) and the forming step (d); (e) removing the first hardmask; (f) masking the second active area with a second hardmask; (g) doping the first active area; (h) forming a silicide in the first active area, wherein the second hardmask serves to mask the second active area during both the doping step (g) and the forming step (h); and (i) removing the second hardmask. | 07-31-2014 |
| 20140332903 | Integrated Circuit Having Raised Source Drains Devices with Reduced Silicide Contact Resistance and Methods to Fabricate Same - A structure has at least one field effect transistor having a gate stack disposed between raised source drain structures that are adjacent to the gate stack. The gate stack and raised source drain structures are disposed on a surface of a semiconductor material. The structure further includes a layer of field dielectric overlying the gate stack and raised source drain structures and first contact metal and second contact metal extending through the layer of field dielectric. The first contact metal terminates in a first trench formed through a top surface of a first raised source drain structure, and the second contact metal terminates in a second trench formed through a top surface of a second raised source drain structure. Each trench has silicide formed on sidewalls and a bottom surface of at least a portion of the trench. Methods to fabricate the structure are also disclosed. | 11-13-2014 |
| 20140374844 | METHOD FOR FORMING METAL SEMICONDUCTOR ALLOYS IN CONTACT HOLES AND TRENCHES - A semiconductor device is provided that includes a gate structure on a channel region of a substrate. A source region and a drain region are present on opposing sides of the channel region. A first metal semiconductor alloy is present on an upper surface of at least one of the source and drain regions. The first metal semiconductor alloy extends to a sidewall of the gate structure. A dielectric layer is present over the gate structure and the first metal semiconductor alloy. An opening is present through the dielectric layer to a portion of the first metal semiconductor alloy that is separated from the gate structure. A second metal semiconductor alloy is present in the opening, is in direct contact with the first metal semiconductor alloy, and has an upper surface that is vertically offset and is located above the upper surface of the first metal semiconductor alloy. | 12-25-2014 |
| 20150044845 | METHOD FOR FORMING METAL SEMICONDUCTOR ALLOYS IN CONTACT HOLES AND TRENCHES - A semiconductor device is provided that includes a gate structure on a channel region of a substrate. A source region and a drain region are present on opposing sides of the channel region. A first metal semiconductor alloy is present on an upper surface of at least one of the source and drain regions. The first metal semiconductor alloy extends to a sidewall of the gate structure. A dielectric layer is present over the gate structure and the first metal semiconductor alloy. An opening is present through the dielectric layer to a portion of the first metal semiconductor alloy that is separated from the gate structure. A second metal semiconductor alloy is present in the opening, is in direct contact with the first metal semiconductor alloy, and has an upper surface that is vertically offset and is located above the upper surface of the first metal semiconductor alloy. | 02-12-2015 |
