| Patent application number | Description | Published |
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| 20090193308 | Method and an Apparatus for Controlling an Unreliable Data Transfer in a Data Channel - Controlling an unreliable data transfer in a data channel from a transmitting unit to a receiving unit. A bypass mode or a buffer mode is activated depending on the error rate in the data channel. If bypass mode is selected, data packets are directly transferred in probation from the transmitting unit to the receiving unit by a bypass line. The data packets are error checked after the data transfer. If buffer mode is selected, data is transfer from the transmitting unit to the receiving unit by a buffer line via an error detecting and correcting unit and a buffer unit. The errors are detected and corrected during the data transfer. | 07-30-2009 |
| 20090204766 | METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR HANDLING ERRORS IN A CACHE WITHOUT PROCESSOR CORE RECOVERY - A method for handling errors in a cache memory without processor core recovery includes receiving a fetch request for data from a processor and simultaneously transmitting fetched data and a parity matching the parity of the fetched data to the processor. The fetched data is received from a higher-level cache into a low level cache of the processor. Upon determining that the fetched data failed an error check indicating that the fetched data is corrupted, the method includes requesting an execution pipeline to discontinue processing and flush its contents, and initiating a clean up sequence, which includes sending an invalidation request to the low level cache causing the low level cache to remove lines associated with the corrupted data, and requesting the execution pipeline to restart. The execution pipeline accesses a copy of the requested data from a higher-level storage location. | 08-13-2009 |
| 20090210627 | METHOD AND SYSTEM FOR HANDLING CACHE COHERENCY FOR SELF-MODIFYING CODE - A method for handling cache coherency includes allocating a tag when a cache line is not exclusive in a data cache for a store operation, and sending the tag and an exclusive fetch for the line to coherency logic. An invalidation request is sent within a minimum amount of time to an I-cache, preferably only if it has fetched to the line and has not been invalidated since, which request includes an address to be invalidated, the tag, and an indicator specifying the line is for a PSC operation. The method further includes comparing the request address against stored addresses of prefetched instructions, and in response to a match, sending a match indicator and the tag to an LSU, within a maximum amount of time. The match indicator is timed, relative to exclusive data return, such that the LSU can discard prefetched instructions following execution of the store operation that stores to a line subject to an exclusive data return, and for which the match is indicated. | 08-20-2009 |
| 20090216949 | METHOD AND SYSTEM FOR A MULTI-LEVEL VIRTUAL/REAL CACHE SYSTEM WITH SYNONYM RESOLUTION - Method and system for a multi-level virtual/real cache system with synonym resolution. An exemplary embodiment includes a multi-level cache hierarchy, including a set of L1 caches associated with one or more processor cores and a set of L2 caches, wherein the set of L1 caches are a subset of the set of L2 caches, wherein the set of L1 caches underneath a given L2 cache are associated with one or more of the processor cores. | 08-27-2009 |
| 20090300560 | METHOD AND SYSTEM FOR FORMAL VERIFICATION OF AN ELECTRONIC CIRCUIT DESIGN - A new and convenient methodology for proving the correctness of multiplier and multiply-accumulate circuit designs in a full custom design flow. Such an approach utilizes a basic description of the implemented algorithm, which is created in early phases of the design flow and requires only little extra work for the designer who spends most of the time in full-custom optimizations. Such an approach also defines arithmetic circuit at the arithmetic bit level and allows for the generation of a gate level netlist. Given a structural similarity between the specification and design under verification, a large amount of structural similarity between the generated netlists is obtained so that a standard equivalence checker can be utilized to verify the design against the specification. | 12-03-2009 |
| 20100146210 | METHOD TO VERIFY AN IMPLEMENTED COHERENCY ALGORITHM OF A MULTI PROCESSOR ENVIRONMENT - A method to verify an implemented coherency algorithm of a multi processor environment on a single processor model is described, comprising the steps of:
| 06-10-2010 |
| 20120059996 | Avoiding Cross-Interrogates in a Streaming Data Optimized L1 Cache - A mechanism is provided for avoiding cross-interrogates for a streaming data optimized level one cache. The mechanism adds a set of dedicated registers, referred to as “copex registers,” to track ownership of the cache lines that the co-processor's L1 cache holds exclusive. The mechanism extends the cache directory of the L2 cache by a bit that identifies exclusive ownership of a cache line in the co-processor cache. The co-processor continuously provides an indication of which copex registers are valid. On any action that requires a directory lookup in the L2 cache, the mechanism compares the valid copex registers against the lookup address in parallel to the directory lookup. The mechanism considers the “exclusive ownership in co-processor” bit in the directory valid only if the cache line is also currently in a valid copex register. | 03-08-2012 |
| 20120210188 | HANDLING CORRUPTED BACKGROUND DATA IN AN OUT OF ORDER EXECUTION ENVIRONMENT - Handling corrupted background data in an out of order processing environment. Modified data is stored on a byte of a word having at least one byte of background data. A byte valid vector and a byte store bit are added to the word. Parity checking is done on the word. If the word does not contain corrupted background date, the word is propagated to the next level of cache. If the word contains corrupted background data, a copy of the word is fetched from a next level of cache that is ECC protected, the byte having the modified data is extracted from the word and swapped for the corresponding byte in the word copy. The word copy is then written into the next level of cache that is ECC protected. | 08-16-2012 |
| 20130246738 | INSTRUCTION TO LOAD DATA UP TO A SPECIFIED MEMORY BOUNDARY INDICATED BY THE INSTRUCTION - A Load to Block Boundary instruction is provided that loads a variable number of bytes of data into a register while ensuring that a specified memory boundary is not crossed. The boundary may be specified a number of ways, including, but not limited to, a variable value in the instruction text, a fixed instruction text value encoded in the opcode, or a register based boundary. | 09-19-2013 |
| 20130246740 | INSTRUCTION TO LOAD DATA UP TO A DYNAMICALLY DETERMINED MEMORY BOUNDARY - A Load to Block Boundary instruction is provided that loads a variable number of bytes of data into a register while ensuring that a specified memory boundary is not crossed. The boundary is dynamically determined based on a specified type of boundary and one or more characteristics of the processor executing the instruction, such as cache line size or page size used by the processor. | 09-19-2013 |
| 20130246767 | INSTRUCTION TO COMPUTE THE DISTANCE TO A SPECIFIED MEMORY BOUNDARY - A Load Count to Block Boundary instruction is provided that provides a distance from a specified memory address to a specified memory boundary. The memory boundary is a boundary that is not to be crossed in loading data. The boundary may be specified a number of ways, including, but not limited to, a variable value in the instruction text, a fixed instruction text value encoded in the opcode, or a register based boundary; or it may be dynamically determined. | 09-19-2013 |
| 20130339325 | CONSTRAINED TRANSACTION EXECUTION - Constrained transactional processing is provided. A constrained transaction is initiated by execution of a Transaction Begin constrained instruction. The constrained transaction has a number of restrictions associated therewith. Absent violation of a restriction, the constrained transaction is to complete. If an abort condition is encountered, the transaction is re-executed starting at the Transaction Begin instruction. Violation of a restriction may cause an interrupt. | 12-19-2013 |
| 20130339326 | TRANSACTION BEGIN/END INSTRUCTIONS - A TRANSACTION BEGIN instruction and a TRANSACTION END instruction are provided. The TRANSACTION BEGIN instruction causes either a constrained or nonconstrained transaction to be initiated, depending on a field of the instruction. A constrained transaction has one or more restrictions associated therewith, while a nonconstrained transaction is not limited in the manner of a constrained transaction. The TRANSACTION END instruction ends the transaction started by the TRANSACTION BEGIN instruction. | 12-19-2013 |
| 20130339327 | FACILITATING TRANSACTION COMPLETION SUBSEQUENT TO REPEATED ABORTS OF THE TRANSACTION - Processing of transactions within a computing environment is facilitated by taking actions to increase the chances of successfully executing a transaction. A counter is maintained that provides a count of how often a transaction has aborted. The counter increments the count each time the transaction is aborted, and it is reset to zero upon successful completion of the transaction or an interruption leading to no more re-executions of the transaction. If the count reaches a threshold value, then an interrupt is presented and transaction execution is unsuccessful. However, before the count reaches the threshold, a number of actions may be taken to increase the chances of successfully executing the transaction. These actions include actions to be performed within the processor executing the transaction, and/or actions to be performed against conflicting processors. | 12-19-2013 |
| 20130339328 | SELECTIVELY CONTROLLING INSTRUCTION EXECUTION IN TRANSACTIONAL PROCESSING - Execution of instructions in a transactional environment is selectively controlled. A TRANSACTION BEGIN instruction initiates a transaction and includes controls that selectively indicate whether certain types of instructions are permitted to execute within the transaction. The controls include one or more of an allow access register modification control and an allow floating point operation control. | 12-19-2013 |
| 20130339329 | TRANSACTIONAL PROCESSING - A transaction is initiated via a transaction begin instruction. During execution of the transaction, the transaction may abort. If the transaction aborts, a determination is made as to the type of transaction. Based on the transaction being a first type of transaction, resuming execution at the transaction begin instruction, and based on the transaction being a second type, resuming execution at an instruction following the transaction begin instruction. Regardless of transaction type, resuming execution includes restoring one or more registers specified in the transaction begin instruction and discarding transactional stores. For one type of transaction, the nonconstrained transaction, the resuming includes storing information in a transaction diagnostic block. | 12-19-2013 |
| 20130339561 | PROGRAM EVENT RECORDING WITHIN A TRANSACTIONAL ENVIRONMENT - A transaction is initiated within a computing environment, and based on detecting a program event recording event, an interrupt is presented for the transaction. Subsequent to the interrupt, one or more controls are set to inhibit presentation of another interrupt based on detecting another PER event. Thereafter, the transaction is re-executed and PER events detected during execution of the transaction are ignored. | 12-19-2013 |
| 20130339615 | MANAGING TRANSACTIONAL AND NON-TRANSACTIONAL STORE OBSERVABILITY - Embodiments relate to controlling observability of transactional and non-transactional stores. An aspect includes receiving one or more store instructions. The one or more store instructions are initiated within an active transaction and include store data. The active transaction effectively delays committing stores to memory until successful completion of the active transaction. The store data is stored in a local storage buffer causing alterations to the local storage buffer from a first state to a second state. A signal is received that the active transaction has terminated. If the active transaction has terminated abnormally then: the local storage buffer is reverted back to the first state if the store data was stored by a transactional store instruction, and is propagated to a shared cache if the store instruction is non-transactional. | 12-19-2013 |
| 20130339616 | MANAGING TRANSACTIONAL AND NON-TRANSACTIONAL STORE OBSERVABILITY - Embodiments relate to controlling observability of transactional and non-transactional stores. An aspect includes receiving one or more store instructions. The one or more store instructions are initiated within an active transaction and include store data. The active transaction effectively delays committing stores to memory until successful completion of the active transaction. The store data is stored in a local storage buffer causing alterations to the local storage buffer from a first state to a second state. A signal is received that the active transaction has terminated. If the active transaction has terminated abnormally then: the local storage buffer is reverted back to the first state if the store data was stored by a transactional store instruction, and is propagated to a shared cache if the store instruction is non-transactional. | 12-19-2013 |
| 20130339618 | AVOIDING ABORTS DUE TO ASSOCIATIVITY CONFLICTS IN A TRANSACTIONAL ENVIRONMENT - Embodiments relate to a transactional read footprint after a cache line eviction. An aspect includes executing one or more read instructions in an active transaction. A cross invalidate (XI) request for a target cache line is received, and it is determined if the target cache line is part of a congruence class in a local cache. It is further determined whether an extension flag associated with the congruence class is set. The extension flag is used to indicate that cache lines of the congruence class associated with the active transaction have been replaced based only on being least recently used and that the target cache line is not in the cache. Execution of the active transaction continues based on determining that the extension flag is not set. Execution of the active transaction is aborted based on determining that the extension flag is set. | 12-19-2013 |
| 20130339627 | MONITORING A VALUE IN STORAGE WITHOUT REPEATED STORAGE ACCESS - A technique is provided for monitoring a value without repeated storage access. A processing circuit processes an instruction of a program that specifies a memory address of a memory location to be monitored. The processing circuit configures a monitor station for monitoring the memory location. The memory location includes a state descriptor for the program. The processing circuit receives a cross-invalidate request from a memory controller. The cross-invalidate request indicates to the monitor station that content of the memory location has been changed by another processing circuit. | 12-19-2013 |
| 20130339628 | DETERMINING THE LOGICAL ADDRESS OF A TRANSACTION ABORT - Embodiments relate to determining the logical address of a transaction abort. In an embodiment, one or more instructions are received are received from an application. The one or more instructions are executed within a first transaction. The first transaction delays committing stores to memory until it has completed. At least one of the one or more instructions includes a first logical memory address. The first logical memory address corresponds to a first memory address in a memory system. It is determined if the first memory address is equal to a second memory address that is stored in a conflict register. Based on determining that they are equal the first logical memory address is saved as a logical address associated with a cross invalidate (XI) signal at a location available to the application. | 12-19-2013 |
| 20130339629 | TRACKING TRANSACTIONAL EXECUTION FOOTPRINT - Embodiments relate to tracking a transactional execution footprint. An aspect includes receiving a store instruction which includes store data. It is determined if the store instruction is executing within a transaction that effectively delays committing stores to a shared cache until the transaction has completed. The store data is stored to a cache line in a local cache. The cache line is marked as dirty if the transaction is active. The stored data that was marked as dirty in the local cache is invalidated if the transaction has terminated abnormally. The stored data is un-marked if it is determined that the transaction has successfully ended. | 12-19-2013 |
| 20130339630 | MONITORING A VALUE IN STORAGE WITHOUT REPEATED STORAGE ACCESS - A technique is provided for monitoring a value without repeated storage access. A processing circuit processes an instruction of a program that specifies a memory address of a memory location to be monitored. The processing circuit configures a monitor station for monitoring the memory location. The memory location includes a state descriptor for the program. The processing circuit receives a cross-invalidate request from a memory controller. The cross-invalidate request indicates to the monitor station that content of the memory location has been changed by another processing circuit. | 12-19-2013 |
| 20130339642 | SAVING/RESTORING SELECTED REGISTERS IN TRANSACTIONAL PROCESSING - A TRANSACTION BEGIN instruction begins execution of a transaction and includes a general register save mask having bits, that when set, indicate registers to be saved in the event the transaction is aborted. At the beginning of the transaction, contents of the registers are saved in memory not accessible to the program, and if the transaction is aborted, the saved contents are copied to the registers. | 12-19-2013 |
| 20130339650 | PREFETCH ADDRESS TRANSLATION USING PREFETCH BUFFER - Embodiments relate to prefetch address translation in a computer processor. An aspect includes issuing, by prefetch logic, a prefetch request comprising a virtual page address. Another aspect includes, based on the prefetch request missing the TLB and the address translation logic of the processor being busy performing a current translation request, comparing a page of the prefetch request to a page of the current translation request. Yet another aspect includes, based on the page of the prefetch request matching the page of the current translation request, storing the prefetch request in a prefetch buffer. | 12-19-2013 |
| 20130339672 | Next Instruction Access Intent Instruction - Executing a Next Instruction Access Intent instruction by a computer. The processor obtains an access intent instruction indicating an access intent. The access intent is associated with an operand of a next sequential instruction. The access intent indicates usage of the operand by one or more instructions subsequent to the next sequential instruction. The computer executes the access intent instruction. The computer obtains the next sequential instruction. The computer executes the next sequential instruction, which comprises based on the access intent, adjusting one or more cache behaviors for the operand of the next sequential instruction. | 12-19-2013 |
| 20130339673 | INTRA-INSTRUCTIONAL TRANSACTION ABORT HANDLING - Embodiments relate to intra-instructional transaction abort handling. An aspect includes using an emulation routine to execute an instruction within a transaction. The instruction includes at least one unit of operation. The transaction effectively delays committing stores to memory until the transaction has completed successfully. After receiving an abort indication, emulation of the instruction is terminated prior to completing the execution of the instruction. The instruction is terminated after the emulation routine completes any previously initiated unit of operation of the instruction. | 12-19-2013 |
| 20130339674 | RESTRICTED INSTRUCTIONS IN TRANSACTIONAL EXECUTION - Restricted instructions are prohibited from execution within a transaction. There are classes of instructions that are restricted regardless of type of transaction: constrained or nonconstrained. There are instructions only restricted in constrained transactions, and there are instructions that are selectively restricted for given transactions based on controls specified on instructions used to initiate the transactions. | 12-19-2013 |
| 20130339675 | RANDOMIZED TESTING WITHIN TRANSACTIONAL EXECUTION - Task specific diagnostic controls are provided to facilitate the debugging of certain types of abort conditions. The diagnostic controls may be set to cause transactions to be selectively aborted, allowing a transaction to drive its abort handler routine for testing purposes. The controls include, for instance, a transaction diagnostic scope and a transaction diagnostic control. The transaction diagnostic scope indicates when the transaction diagnostic control is to be applied, and the transaction diagnostic control indicates whether transactions are to selectively aborted. | 12-19-2013 |
| 20130339676 | TRANSACTION ABORT INSTRUCTION - A TRANSACTION ABORT instruction is used to abort a transaction that is executing in a computing environment. The TRANSACTION ABORT instruction includes at least one field used to specify a user-defined abort code that indicates the specific reason for aborting the transaction. Based on executing the TRANSACTION ABORT instruction, a condition code is provided that indicates whether re-execution of the transaction is recommended. | 12-19-2013 |
| 20130339680 | NONTRANSACTIONAL STORE INSTRUCTION - A NONTRANSACTIONAL STORE instruction, executed in transactional execution mode, performs stores that are retained, even if a transaction associated with the instruction aborts. The stores include user-specified information that may facilitate debugging of an aborted transaction. | 12-19-2013 |
| 20130339684 | RESTRICTING PROCESSING WITHIN A PROCESSOR TO FACILITATE TRANSACTION COMPLETION - Processing of transactions within a computing environment is facilitated by taking actions to increase the chances of successfully executing a transaction. A counter is maintained that provides a count of how often a transaction has aborted. The counter increments the count each time the transaction is aborted, and it is reset to zero upon successful completion of the transaction or an interruption leading to no more re-executions of the transaction. If the count reaches a threshold value, then an interrupt is presented and transaction execution is unsuccessful. However, before the count reaches the threshold, a number of actions may be taken to increase the chances of successfully executing the transaction. These actions include actions to be performed within the processor executing the transaction, and/or actions to be performed against conflicting processors. | 12-19-2013 |
| 20130339685 | RESTRICTED INSTRUCTIONS IN TRANSACTIONAL EXECUTION - Restricted instructions are prohibited from execution within a transaction. There are classes of instructions that are restricted regardless of type of transaction: constrained or nonconstrained. There are instructions only restricted in constrained transactions, and there are instructions that are selectively restricted for given transactions based on controls specified on instructions used to initiate the transactions. | 12-19-2013 |
| 20130339687 | PROCESSOR ASSIST FACILITY - An operation is provided to signal a processor that action is to be taken to facilitate execution of a transaction that has aborted one or more times. The operation is specified within an instruction or is itself an instruction. The instruction is executed based on detecting an abort of the transactions, and includes a field indicating how many times the transaction has aborted. The processor uses this information to determine what action is to be taken. | 12-19-2013 |
| 20130339702 | PROGRAM INTERRUPTION FILTERING IN TRANSACTIONAL EXECUTION - Program exception conditions cause a transaction to abort and typically result in an interruption in which the operating system obtains control. A program interruption filtering control is provided to selectively present the interrupt. That is, the interrupt from the program exception condition may or may not be presented depending at least on the program interruption filtering control and a transaction class associated with the program exception condition. The program interruption filtering control is provided by a TRANSACTION BEGIN instruction. | 12-19-2013 |
| 20130339704 | SAVING/RESTORING SELECTED REGISTERS IN TRANSACTIONAL PROCESSING - A TRANSACTION BEGIN instruction begins execution of a transaction and includes a general register save mask having bits, that when set, indicate registers to be saved in the event the transaction is aborted. At the beginning of the transaction, contents of the registers are saved in memory not accessible to the program, and if the transaction is aborted, the saved contents are copied to the registers. | 12-19-2013 |
| 20130339796 | TRANSACTIONAL EXECUTION BRANCH INDICATIONS - Transactional execution branch indications are placed into one or more transaction diagnostic blocks when a transaction is aborted. Each branch indication specifies whether a branch was taken, as a result of executing a branch instruction within the transaction. As the transaction executes and a branch instruction is encountered, a branch indication is set in a vector indicating whether the branch was taken. Then, if the transaction aborts, the indicators are stored in one or more transaction diagnostic blocks providing a branch history usable in diagnosing the failure. | 12-19-2013 |
| 20130339806 | TRANSACTION DIAGNOSTIC BLOCK - When an abort of a transaction occurs, a determination is made as to whether diagnostic information is to be stored in one or more transaction diagnostic blocks (TDBs). There are different types of transaction diagnostic blocks to accept diagnostic information depending on the type of abort and other considerations. As examples, there are a program-specified TDB in which information is stored if a valid TDB address is provided in a transaction begin instruction; a program interruption TDB, which is stored into when the program is aborted due to an interruption; and a program interception TDB, which is stored into when an abort results in an interception. | 12-19-2013 |
| 20130339963 | TRANSACTION ABORT PROCESSING - A transaction executing within a computing environment ends prior to completion; i.e., execution is aborted. Pursuant to aborting execution, a hardware transactional execution CPU mode is exited, and one or more of the following is performed: restoring selected registers; committing nontransactional stores on abort; branching to a transaction abort program status word specified location; setting a condition code and/or abort code; and/or preserving diagnostic information. | 12-19-2013 |
| 20130339967 | CONSTRAINED TRANSACTION EXECUTION - Constrained transactional processing is provided. A constrained transaction is initiated by execution of a Transaction Begin constrained instruction. The constrained transaction has a number of restrictions associated therewith. Absent violation of a restriction, the constrained transaction is to complete. If an abort condition is encountered, the transaction is re-executed starting at the Transaction Begin instruction. Violation of a restriction may cause an interrupt. | 12-19-2013 |
| 20140082252 | Combined Two-Level Cache Directory - Responsive to receiving a logical address for a cache access, a mechanism looks up a first portion of the logical address in a local cache directory for a local cache. The local cache directory returns a set identifier for each set in the local cache directory. Each set identifier indicates a set within a higher level cache directory. The mechanism looks up a second portion of the logical address in the higher level cache directory and compares each absolute address value received from the higher level cache directory to an absolute address received from a translation look-aside buffer to generate a higher level cache hit signal. The mechanism compares the higher level cache hit signal to each set identifier to generate a local cache hit signal and responsive to the local cache hit signal indicating a local cache hit, accesses the local cache based on the local cache hit signal. | 03-20-2014 |
| 20140082293 | Store Buffer for Transactional Memory - Provided are techniques for handling a store buffer in conjunction with a processor, the store buffer comprising a free list; a merge window; and an evict list; and logic, for, upon receipt of a T_STORE operation, comparing a first address associated with the T_STORE operation with a plurality of addresses associated with previous T_STORE operations, wherein the previous T_STORE operations are part of the same transaction as the T_STORE operation and the entries corresponding to the previous T_STORE operations are stored in the merge window; in response to a match between the first address and a second address, associated with a second T_STORE operation, of the plurality of addresses, merging a first entry corresponding to the first T_STORE operation with a second entry corresponding to the second T_STORE operation; and consolidating results associated with the first T_STORE operation with results associated with the second T_STORE operation. | 03-20-2014 |
| 20140095851 | Delaying Interrupts for a Transactional-Execution Facility - A mechanism is provided for completing of set of instructions while receiving interrupts. The mechanism executes a set of instructions. Responsive to receiving an interrupt and determining that the interrupt requires processing within an implementation time frame, the mechanism delays the interrupt for a predetermined time period. Responsive to completing the set of instructions within the predetermined time period, the mechanism processes the interrupt. | 04-03-2014 |
| 20140223137 | STORING A SYSTEM-ABSOLUTE ADDRESS (SAA) IN A FIRST LEVEL TRANSLATION LOOK-ASIDE BUFFER (TLB) - Embodiments relate to a method, system and computer program product for storing a system-absolute address (SAA) in a first level look-aside buffer (TLB). In one embodiment, the system includes a central processor including the TLB and general purpose registers (GPRS). The TLB is configured for storing the SAA. The central processor is configured for issuing a load system-absolute address (LSAA) instruction. The system includes a translation unit that is in communication with the TLB of the central processor. The system is configured to perform a method including determining, based on the LSAA instruction being issued, whether the SAA is stored in the TLB. The method includes sending a translation request to the translation unit from the central processor based on the SAA not being stored in the TLB. The method includes determining the SAA by the translation unit based on receiving the translation request. | 08-07-2014 |
| 20140281238 | SYSTEMS AND METHODS FOR ACCESSING CACHE MEMORY - Systems and methods for providing data from a cache memory to requestors includes a number of cache memory levels arranged in a hierarchy. The method includes receiving a request for fetching data from the cache memory and determining one or more addresses in a cache memory level which is one level higher than a current cache memory level using one or more prediction algorithms. Further, the method includes pre-fetching the one or more addresses from the high cache memory level and determining if the data is available in the addresses. If data is available in the one or more addresses then data is fetched from the high cache level, else addresses of a next level which is higher than the high cache memory level are determined and pre-fetched. Furthermore, the method includes providing the fetched data to the requestor. | 09-18-2014 |
| 20150039868 | INTRA-INSTRUCTIONAL TRANSACTION ABORT HANDLING - Embodiments relate to intra-instructional transaction abort handling. An aspect includes using an emulation routine to execute an instruction within a transaction. The instruction includes at least one unit of operation. The transaction effectively delays committing stores to memory until the transaction has completed successfully. After receiving an abort indication, emulation of the instruction is terminated prior to completing the execution of the instruction. The instruction is terminated after the emulation routine completes any previously initiated unit of operation of the instruction. | 02-05-2015 |
