Chou, Tainan County
Cheng Wei Chou, Tainan County TW
| Patent application number | Description | Published |
|---|---|---|
| 20110001135 | METHOD FOR MANUFACTURING SELF-ALIGNED THIN-FILM TRANSISTOR AND STRUCTURE THEREOF - A method for manufacturing a self-aligned thin-film transistor (TFT) is described. Firstly, an oxide gate, a dielectric layer, and a photoresist layer are deposited on a first surface of a transparent substrate in sequence. Then, an ultraviolet light is irradiated on a second surface of the substrate opposite to the first surface to expose the photoresist layer, in which a gate manufactured by the oxide gate serves as a mask, and absorbs the ultraviolet light irradiated on the photoresist layer corresponding to the oxide gate. Then, the exposed photoresist layer is removed, and a transparent conductive layer is deposited on the unexposed photoresist layer and the dielectric layer. Then, a patterning process is executed on the transparent conductive layer to form a source and a drain, and an active layer is formed to cover the source, the drain, and the dielectric layer, so as to finish a self-aligned TFT structure. | 01-06-2011 |
| 20110193089 | PIXEL STRUCTURE, METHOD OF FABRICATING THE SAME, AND METHOD OF FABRICATING ELECTRONIC DEVICE - A pixel structure including a substrate, a gate, an insulation layer, a metal oxide semiconductor (MOS) layer, a source and a drain, at least one film layer, and a first electrode layer is provided. The gate is disposed on the substrate. The insulation layer covers the gate. The MOS layer is disposed on the insulation layer above the gate. The source and the drain are disposed on the MOS layer. The film layer covers the MOS layer and includes a transparent photocatalytic material, wherein the transparent photocatalytic material blocks ultraviolet light from reaching the MOS layer. The first electrode layer is electrically connected to the source or the drain. | 08-11-2011 |
Cheng-Zing Chou, Tainan County TW
| Patent application number | Description | Published |
|---|---|---|
| 20090066588 | Case structure of electronic device - A case structure of an electronic device is used for directly integrating an antenna of a signal transceiver circuit and a case of the electronic device, so as to improve a space utilization rate of the electronic device. At least one trench pattern is formed on a specific region of the metal case of the electronic device. When the metal case is electrically coupled to the signal transceiver circuit of the electronic device, the metal case and the trench pattern constitute at least one antenna of the electronic device. | 03-12-2009 |
| 20120011395 | BOOT METHOD UNDER BOOT SECTOR FAILURE IN HARD DISK AND COMPUTER DEVICE USING THE SAME - A boot method under a boot sector failure in a hard disk is provided, which includes the following steps. First, a detection unit is utilized to determine whether a boot sector in the hard disk fails. After determining that the boot sector fails, the detection unit utilizes a second boot file stored in a solid state disk (SSD) for booting. Meanwhile, the detection unit drives a pickup head in the hard disk to skip the failed boot sector and move to a normal sector in the hard disk, so as to boot a computer and enable the hard disk to operate normally. | 01-12-2012 |
Chien-Kang Chou, Tainan County TW
| Patent application number | Description | Published |
|---|---|---|
| 20090065871 | SEMICONDUCTOR CHIP AND PROCESS FOR FORMING THE SAME - A semiconductor chip comprises a first MOS device, a second MOS device, a first metallization structure connected to said first MOS device, a second metallization structure connected to said second MOS device, a passivation layer over said first and second MOS devices and over said first and second metallization structures, and a third metallization structure connecting said first and second metallization structures. | 03-12-2009 |
| 20090104769 | Semiconductor chip with coil element over passivation layer - A method for fabricating a circuitry component includes providing a semiconductor substrate, a first coil over said semiconductor substrate, a passivation layer over said first coil; and depositing a second coil over said passivation layer and over said first coil. Said second coil may be deposited by forming a first metal layer over said passivation layer, forming a pattern defining layer over said first metal layer, a first opening in said pattern defining layer exposing said first metal layer, forming a second metal layer over said first metal layer exposed by said first opening, removing said pattern defining layer, and removing said first metal layer not under said second metal layer. | 04-23-2009 |
| 20090108453 | CHIP STRUCTURE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a metallization structure comprises depositing a first metal layer; depositing a first pattern-defining layer over said first metal layer, a first opening in said first pattern-defining layer exposes said first metal layer; depositing a second metal layer over said first metal layer exposed by said first opening; depositing a second pattern-defining layer over said second metal layer, a second opening in said second pattern-defining layer exposes said second metal layer; depositing a third metal layer over said second metal layer exposed by said second opening; removing said second pattern-defining layer; removing said first pattern-defining layer; and removing said first metal layer not under said second metal layer. | 04-30-2009 |
| 20110204510 | CHIP STRUCTURE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a metallization structure comprises depositing a first metal layer; depositing a first pattern-defining layer over said first metal layer, a first opening in said first pattern-defining layer exposes said first metal layer; depositing a second metal layer over said first metal layer exposed by said first opening; depositing a second pattern-defining layer over said second metal layer, a second opening in said second pattern-defining layer exposes said second metal layer; depositing a third metal layer over said second metal layer exposed by said second opening; removing said second pattern-defining layer; removing said first pattern-defining layer; and removing said first metal layer not under said second metal layer. | 08-25-2011 |
| 20110233776 | SEMICONDUCTOR CHIP WITH COIL ELEMENT OVER PASSIVATION LAYER - A method for fabricating a circuitry component includes providing a semiconductor substrate, a first coil over said semiconductor substrate, a passivation layer over said first coil; and depositing a second coil over said passivation layer and over said first coil. Said second coil may be deposited by forming a first metal layer over said passivation layer, forming a pattern defining layer over said first metal layer, a first opening in said pattern defining layer exposing said first metal layer, forming a second metal layer over said first metal layer exposed by said first opening, removing said pattern defining layer, and removing said first metal layer not under said second metal layer. | 09-29-2011 |
Chun-Hung Chou, Tainan County TW
| Patent application number | Description | Published |
|---|---|---|
| 20100142059 | LIQUID OPTICAL LENS AND LIQUID OPTICAL LENS MODULES - A liquid optical lens, including a transparent container, an elastic membrane, a first liquid and a second liquid, is provided. The transparent container is divided into a first chamber and a second chamber by the elastic membrane. The first liquid fills the first chamber. The second liquid fills the second chamber. The curvature of the elastic membrane is regulated by changing the volume ratio between the first liquid and the second liquid, so as to adjust the focal length of the liquid optical lens. Moreover, a liquid optical lens module including the above liquid optical lens and a volume adjustment mechanism is also provided. The focal length of the liquid optical lens can be precisely adjusted by using the volume adjustment mechanism. | 06-10-2010 |
Chun Sung Chou, Tainan County TW
| Patent application number | Description | Published |
|---|---|---|
| 20090044225 | METHOD OF BUILDING UP GROUP PROFILE FOR CUSTOMIZING EPG VIEWING AND METHOD OF USING THE GROUP PROFILE - The method of building group profiles for customizing EPG viewing includes the steps of: automatically establishing background information of viewers by means of personal profiles of the viewers; and automatically establishing preference information of the viewers by means of personal profiles or browsing records of the viewers. | 02-12-2009 |
| 20090064223 | DTV VIEWING TERMINAL, EPG SERVICE SYSTEM AND METHOD FOR EXHIBITING EPG - The method for accessing an EPG server includes the steps of: sending a web request from a browser-embedded DTV viewing terminal to the EPG server through the Internet; identifying the web requester in the EPG server; providing collected EPG in a webpage mode in the EPG server; and providing DTV presenting parameters from the EPG server to the browser-embedded DTV viewing terminal as soon as a desired program is selected. | 03-05-2009 |
| 20090064226 | USER INTERFACE OF INTERACTIVE PROGRAM GUIDE AND METHOD THEREOF - A user interface of an interactive program guide includes a two-dimensional EPG area and a selected program area. The two-dimensional EPG area includes a list of channels, programs corresponding to the channels and an indicator pointing to a selected program. The selected program area includes an analog clock indicating the current time and display period of the selected program and a status area with text indicating the status of the selected program. | 03-05-2009 |
Chun-Yu Chou, Tainan County TW
| Patent application number | Description | Published |
|---|---|---|
| 20110195553 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device is provided. The method comprises: forming a first layer; forming a P-well on the first layer; forming an isolation region in the P-well; performing an extra implantation on a surface between the P-well and the first layer; and forming a source/drain region. The method of the present invention can solve the punch through problem of the conventional iso-NMOS transistor without increasing cost. | 08-11-2011 |
| 20120080752 | HIGH VOLTAGE METAL-OXIDE-SEMICONDUCTOR TRANSISTOR WITH STABLE THRESHOLD VOLTAGE AND RELATED MANUFACTURING METHOD - A high voltage metal-oxide-semiconductor (HVMOS) transistor includes a gate poly, wherein a channel is formed in an area projected from the gate poly in a thickness direction when the HVMOS is activated; two carrier drain drift regions, adjacent to the area projected from the gate poly, wherein at least one of the carrier drain drift regions has a gradient doping concentration; and two carrier plus regions, respectively locate within the two carrier drain drift regions, wherein the two carrier plus regions and the two carrier drain drift regions are communicating with each other through the channel when the HVMOS is activated. | 04-05-2012 |
En-Jan Chou, Tainan County TW
| Patent application number | Description | Published |
|---|---|---|
| 20120162363 | Systems and Methods for Sharing Conversion Data - A method implemented in a server for sharing video conversion data is described. The method comprises receiving one or more sets of conversion data for one or more two-dimensional (2D) videos, archiving the one or more sets of conversion data, and receiving, from a client, a selection of a 2D video corresponding to one or more of the archived one or more conversion data. The method further comprises transmitting, to the client, conversion data corresponding to the selection received from the client. | 06-28-2012 |
George Chin-Sheng Chou, Tainan County TW
| Patent application number | Description | Published |
|---|---|---|
| 20080293049 | Methods, Kids and Polynucleotides for Simultaneously Diagnosing Viruses - The present invention provides a simultaneous method for diagnosing HBV, HCV and HIV of a suspected patient. The present invention further provides different primer sets and specific probes for HBV, HCV and HIV. The present invention also provides a kit for simultaneous diagnosing of HBV, HCV and HIV. | 11-27-2008 |
| 20090142757 | STRIP AND METHOD FOR DETECTING NUCLEOTIDE AMPLIFICATION PRODUCTS OF MYCOBACTERIUM TUBERCULOSIS AND NON-TUBERCULOUS MYCOBACTERIUM - The present invention provides a test strip and a method for rapid identifying the presence of the amplified DNA product of | 06-04-2009 |
| 20090263793 | NOVEL METHOD FOR DIAGNOSING OF MYCOBACTERIUM Tuberculosis - The present invention relates to a method and a kit for detecting | 10-22-2009 |
Heng-Yi Chou, Tainan County TW
| Patent application number | Description | Published |
|---|---|---|
| 20090316392 | ELECTRIC ENERGY CONTROL CIRCUIT FOR SOLAR POWER ILLUMINATION SYSTEM - The present invention discloses an electric energy control circuit for a solar power illumination system. The solar power illumination system has at least one solar panel coupled to a charging controller, and the solar panel charges at least one battery via the charging controller. An electric energy control circuit according to the present invention controls a driving unit to acquire electric energy from the battery and turn on at least one lamp set. The electric energy control circuit comprises: a power detection loop and an output control loop. The power detection loop is coupled to the solar panel and the battery and detects the power generation of the solar panel and the remaining capacity of the battery. The output control loop is coupled to the power detection loop and determines the power output to the lamp set according to the power generation and the remaining capacity. Thereby, the present invention can modulate the power for the solar power illumination system according to the weather, prolong the power supply time of the battery, and reduce the bad weather-induced attrition of the solar power illumination system. | 12-24-2009 |
Hua-Shan Chou, Tainan County TW
| Patent application number | Description | Published |
|---|---|---|
| 20090075614 | AUTOMATIC GAIN CONTROL METHOD FOR RECEIVER AND APPARATUS THEREOF - A gain control method which includes setting a first initial gain value to a first variable gain amplifier; measuring a first power value corresponding to incoming signals; measuring a second power value corresponding to a target signal; and resetting the first initial gain value according to the first power value and the second power value. Another gain control method is also disclosed, which includes updating a gain value of a first variable gain amplifier by combining an adjustment value with the gain value according to a first tuning direction; obtaining a signal quality indicator; comparing the signal quality indicator with a reference signal quality indicator to generate a comparison result; and referring to the comparison result, further updating the gain value according to the first tuning direction or a second tuning direction opposite to the first tuning direction. | 03-19-2009 |
Mei-Ling Chou, Tainan County TW
| Patent application number | Description | Published |
|---|---|---|
| 20100134031 | DEVICE AND METHOD FOR PERIODIC DIODE ACTUATION - An energy efficient illumination device is provided in which energy consumption is reduced by using a pulse generating circuit which provides power to LEDs in short pulses, and in which the circuit has a lifespan which is comparable to that of an LED. The illumination device includes a pulse generator circuit employing only passive circuit components and which is used to generate a desired pulsed and positively DC biased output waveform. The pulse generator circuit receives alternating current power as an input, alters the power waveform, and supplies the power to LEDs for a very short time (0.2-15 ms) during each cycle of a 50-60 Hz input signal. This paradigm of pulsed light emission provides ambient lighting that is perceived by humans to be steady and continuous, and which also provides substantial energy savings since power is used in only a fraction of the power cycle. | 06-03-2010 |
Shu-Hsien Chou, Tainan County TW
| Patent application number | Description | Published |
|---|---|---|
| 20110176609 | MULTI-FORMAT VIDEO DECODER AND RELATED DECODING METHOD - A multi-format video decoder includes a bitstream buffer, a system controller, a bitstream decoding unit, an intra mode decoding unit and a shared prediction module. The system controller selectively generates a first control signal or a second control signal according to a video bitstream. The bitstream decoding unit generates a decoding information signal according to the video bitstream when receiving the first control signal. The intra mode decoding unit generates an intra mode signal when receiving the second control signal. The shared prediction module performs an AC/DC prediction upon a current block of the video bitstream to generate a current first prediction result according to the decoding information signal and performs an intra prediction upon the current block to generate a current second prediction result according to the intra mode signal. The shared prediction module includes shared components being utilized in the AC/DC prediction and the intra prediction. | 07-21-2011 |
| 20110216835 | EDGE FILTER WITH A SHARING ARCHITECTURE AND RELATED METHOD FOR SHARING THE EDGE FILTER UNDER A PLURALITY OF VIDEO STANDARDS - An edge filter includes an input unit and a shared edge filter module. The input unit receives first original pixels of a first decoded block and second original pixels of a second decoded block. The shared edge filter module includes a shared intermediate value generator and a filtering unit. The shared intermediate value generator generates shared intermediate values by making use of original pixels selected from the first original pixels and the second original pixels according to a coefficient rule of coefficients of the first and second original pixels under a designated video standard. The filtering unit filters the first original pixels and the second original pixels to generate a plurality of first filtered pixels and a plurality of second filtered pixels by reference to the coefficient rule. At least two of the first filtered pixels and the second filtered pixels are derived from the shared intermediate value. | 09-08-2011 |
| 20110280321 | DEBLOCKING FILTER AND METHOD FOR CONTROLLING THE DEBLOCKING FILTER THEREOF - A deblocking filter includes a controller, an edge filter module, a first multiplexer module, a plurality of buffers, and a second multiplexer module. The controller controls the deblocking filter to filter edges between decoded blocks according to a plurality of deblocking strategies in order to obtain an efficiency result under a designated video standard, and determines a target deblocking strategy by reference to the efficiency result. The edge filter module filters a plurality of original pixels to generate a plurality of filtered pixels. The first multiplexer module outputs a plurality of combinations selected from the plurality of filtered pixels according to the target deblocking strategy. The plurality of buffers are used for storing the plurality of combinations, respectively. The second multiplexer module selectively outputs a designated combination of the plurality of combinations as the original pixels to be inputted into the edge filter module according to the target deblocking strategy. | 11-17-2011 |
Ying-Hung Chou, Tainan County TW
| Patent application number | Description | Published |
|---|---|---|
| 20120012938 | METHOD OF MANUFACTURING COMPLEMENTARY METAL OXIDE SEMICONDUCTOR DEVICE - A method of manufacturing a CMOS device includes providing a substrate having a first region and a second region; forming a first gate structure and a second gate structure, each of the gate structures comprising a sacrificial layer and a hard mask layer; forming a patterned first protecting layer covering the first region and a first spacer on sidewalls of the second gate structure; performing an etching process to form first recesses in the substrate; performing a SEG process to form epitaxial silicon layers in each first recess; forming a patterned second protecting layer covering the second region; and performing a dry etching process with the patterned second protecting layer serving as an etching mask to etch back the patterned first protecting layer to form a second spacer on sidewalls of the first gate structure and to thin down the hard mask layer on the first gate structure. | 01-19-2012 |