Patent application number | Description | Published |
20130221536 | ENHANCED FLIP CHIP STRUCTURE USING COPPER COLUMN INTERCONNECT - A flip chip package includes a carrier coupled to a die. The carrier includes: at least a via, for coupling the surface of the carrier to electrical traces in the carrier; and at least a capture pad electrically coupled to the via, wherein the capture pad is plated over the via. The die includes: at least a bond pad formed on the surface of the die; and at least a copper column, formed on the bond pad for coupling the die to the capture pad on the carrier, wherein the copper column is disposed on one side of the capture pad about the via opening only. | 08-29-2013 |
20140042615 | FLIP-CHIP PACKAGE - An exemplary flip-chip package is provided, including: a package structure having a first bonding pad and a second bonding pad formed thereon, wherein the first bond pad has a feature size different from a feature size of the second bond pad; a semiconductor chip facing the package structure, having a first under bump metal (UBM) layer and a second under bump metal (UBM) layer formed thereon, wherein the first UBM layer has a feature size different from a feature size of the second UBM layer; a first conductive element disposed between the first bond pad and the first UBM layer; and a second conductive element disposed between the second bond pad and the second UBM layer. | 02-13-2014 |
20150097277 | FAN-OUT SEMICONDUCTOR PACKAGE WITH COPPER PILLAR BUMPS - A system-in-package includes a package carrier; a first semiconductor die having a die face and a die edge, the first semiconductor die being assembled face-down to a chip side of the package carrier, wherein a plurality of contact pads are situated on the die face; a second semiconductor die mounted on the package carrier and adjacent to the first semiconductor die; a rewiring laminate structure between the first semiconductor die and the package carrier, the rewiring laminate structure comprising a re-routed metal layer, wherein at least a portion of the re-routed metal layer projects beyond the die edge; and a plurality of copper pillar bumps arranged on the rewiring laminate structure for electrically connecting the first semiconductor die with the package carrier. | 04-09-2015 |
20150249060 | ENHANCED FLIP CHIP STRUCTURE USING COPPER COLUMN INTERCONNECT - A flip chip package includes: a carrier coupled to a die. The carrier includes: at least a via, for coupling the surface of the carrier to electrical traces in the carrier; and at least a capture pad electrically coupled to the via, wherein the capture pad is plated over the via. The die includes: at least a bond pad formed on the surface of the die; and at least a copper column, formed on the bond pad for coupling the die to the capture pad on the carrier, wherein part of the copper column overhangs the via opening. | 09-03-2015 |
Patent application number | Description | Published |
20120280348 | BACK SIDE ILLUMINATED IMAGE SENSOR WITH IMPROVED STRESS IMMUNITY - Provided is an image sensor device. The image sensor device includes a substrate having a front side and a back side opposite the first side. The substrate has a pixel region and a periphery region. The image sensor device includes a plurality of radiation-sensing regions disposed in the pixel region of the substrate. Each of the radiation-sensing regions is operable to sense radiation projected toward the radiation-sensing region through the back side. The image sensor device includes a reference pixel disposed in the periphery region. The image sensor device includes an interconnect structure that is coupled to the front side of the substrate. The interconnect structure includes a plurality of interconnect layers. The image sensor device includes a film formed over the back side of the substrate. The film causes the substrate to experience a tensile stress. The image sensor device includes a radiation-blocking device disposed over the film. | 11-08-2012 |
20130299886 | Backside Structure and Methods for BSI Image Sensors - BSI image sensors and methods. In an embodiment, a substrate is provided having a sensor array and a periphery region and having a front side and a back side surface; a bottom anti-reflective coating (BARC) is formed over the back side to a first thickness, over the sensor array region and the periphery region; forming a first dielectric layer over the BARC; a metal shield is formed; selectively removing the metal shield from over the sensor array region; selectively removing the first dielectric layer from over the sensor array region, wherein a portion of the first thickness of the BARC is also removed and a remainder of the first thickness of the BARC remains during the process of selectively removing the first dielectric layer; forming a second dielectric layer over the remainder of the BARC and over the metal shield; and forming a passivation layer over the second dielectric layer. | 11-14-2013 |
20130299931 | Backside Structure for BSI Image Sensor - An embodiment method for forming an image sensor includes forming an anti-reflective coating over a surface of a semiconductor supporting a photodiode, forming an etching stop layer over the anti-reflective coating, forming a buffer oxide over the etching stop layer, and selectively removing a portion of the buffer oxide through etching, the etching stop layer protecting the anti-reflective coating during the etching. An embodiment image sensor includes a semiconductor disposed in an array region and in a periphery region, the semiconductor supporting a photodiode in the array region, an anti-reflective coating disposed over a surface of the semiconductor, an etching stop layer disposed over the anti-reflective coating, a thickness of the etching stop layer over the photodiode in the array region less than a thickness of the etching stop layer in the periphery region, and a buffer oxide disposed over the etching stop layer in the periphery region. | 11-14-2013 |
20140073080 | Back Side Defect Reduction for Back Side Illuminated Image Sensor - Provided is an image sensor device. The image sensor device includes a substrate having a front side and a back side. The image sensor also includes a radiation-detection device that is formed in the substrate. The radiation-detection device is operable to detect a radiation wave that enters the substrate through the back side. The image sensor further includes a recrystallized silicon layer. The recrystallized silicon layer is formed on the back side of the substrate. The recrystallized silicon layer has different photoluminescence intensity than the substrate. | 03-13-2014 |
20140159190 | Backside Structure and Methods for BSI Image Sensors - BSI image sensors and methods. In an embodiment, a substrate is provided having a sensor array and a periphery region and having a front side and a back side surface; a bottom anti-reflective coating (BARC) is formed over the back side to a first thickness, over the sensor array region and the periphery region; forming a first dielectric layer over the BARC; a metal shield is formed; selectively removing the metal shield from over the sensor array region; selectively removing the first dielectric layer from over the sensor array region, wherein a portion of the first thickness of the BARC is also removed and a remainder of the first thickness of the BARC remains during the process of selectively removing the first dielectric layer; forming a second dielectric layer over the remainder of the BARC and over the metal shield; and forming a passivation layer over the second dielectric layer. | 06-12-2014 |
20140252523 | Backside Structure and Methods for BSI Image Sensors - A back side image sensor and method of manufacture are provided. In an embodiment a bottom anti-reflective coating is formed over a substrate, and a metal shield layer is formed over the bottom anti-reflective coating. The metal shield layer is patterned to form a grid pattern over a sensor array region of the substrate, and a first dielectric layer and a second dielectric layer are formed to at least partially fill in openings within the grid pattern. | 09-11-2014 |
20150140722 | Backside Structure and Method for BSI Image Sensors - BSI image sensors and methods. In an embodiment, a substrate is provided having a sensor array and a periphery region and having a front side and a back side surface; a bottom anti-reflective coating (BARC) is formed over the back side to a first thickness, over the sensor array region and the periphery region; forming a first dielectric layer over the BARC; a metal shield is formed; selectively removing the metal shield from over the sensor array region; selectively removing the first dielectric layer from over the sensor array region, wherein a portion of the first thickness of the BARC is also removed and a remainder of the first thickness of the BARC remains during the process of selectively removing the first dielectric layer; forming a second dielectric layer over the remainder of the BARC and over the metal shield; and forming a passivation layer over the second dielectric layer. | 05-21-2015 |
20150187834 | Ridge Structure for Back Side Illuminated Image Sensor - Provided is an image sensor device. The image sensor device includes a substrate having a front side and a back side. The image sensor includes first and second radiation-detection devices that are disposed in the substrate. The first and second radiation-detection devices are operable to detect radiation waves that enter the substrate through the back side. The image sensor also includes an anti-reflective coating (ARC) layer. The ARC layer is disposed over the back side of the substrate. The ARC layer has first and second ridges that are disposed over the first and second radiation-detection devices, respectively. The first and second ridges each have a first refractive index value. The first and second ridges are separated by a substance having a second refractive index value that is less than the first refractive index value. | 07-02-2015 |
Patent application number | Description | Published |
20120133607 | TOUCH-SENSING DISPLAY PANEL, TOUCH PANEL, TOUCH-SENSING DEVICE AND TOUCH-SENSING CIRCUIT - The present application provides a touch-sensing display panel comprising a display panel and a touch-sensing device disposed above the display panel. The touch-sensing device comprises a plurality of select lines, a plurality of readout lines and a plurality of capacitive touch-sensing units arranged in array. Each of the capacitive touch-sensing units comprises a transistor and a touch-sensing pad, each of the transistors comprises a gate electrode electrically connected to one of the select lines, a source electrode electrically connected to a reference voltage, a drain electrode electrically connected to one of the readout lines, and a channel layer electrically coupled to the touch-sensing pad. | 05-31-2012 |
20120287075 | Active touch sensing circuit apparatus - The invention discloses an active matrix touch sensing circuit apparatus used in a touch panel comprises a sensing unit, a resistance, and a thin film transistor. The resistance connects the sensing unit and the first scan line. The control end of the thin film transistor connects the sensing unit, the second scan line connects the input end of the thin film transistor, and the read out line connects the output end of the thin film transistor. When the sensing value of the body touch sensing unit is changed, and then the input wave form of the control end is changed. The output end generates an open current, and the read out line transmits the open current. | 11-15-2012 |
20140192035 | PIXEL CIRCUIT, ACTIVE SENSING ARRAY, SENSING DEVICE AND DRIVING METHOD THEREOF - A pixel circuit, an active sensing array, a sensing device, and a driving method thereof are provided. The pixel circuit includes a sensing transistor, a reset transistor, and a storage capacitor. The sensing transistor is electrically connected to a sensing element and a data line. The reset transistor is electrically connected to a first scan line and the sensing transistor. The storage capacitor is electrically connected to the sensing transistor and a second scan line. During a compensation period, the reset transistor is turned on in response to a first scanning pulse from the first scan line, so that the sensing transistor is connected into a diode configuration, and the storage capacitor charges and discharges to a threshold voltage of the sensing transistor through the sensing transistor having the diode configuration in response to switching of a level of the data line. | 07-10-2014 |
20150077010 | THE PIXEL CIRCUIT FOR ACTIVE MATRIX DISPLAY APPARATUS AND THE DRIVING METHOD THEREOF - Provided is the pixel circuit for active matrix display apparatus and the driving method thereof, which is controlled by digital signal. The pre-charge pixel voltage is controlled and discharged by controlling the resistor and transistors, so that the desired grey scale is generated. The pixel circuit includes: a first switch, a second switch, a third switch, an energy storage device and resistor. By controlling the third switch, the first end of the energy storage device is charged to the voltage of the second source. The first switch and the second switch are controlled to switch on, so that the first end of the energy storage device discharging to the first source. The second switch switches off when the first end of the energy storage device reaches the desired pixel voltage. | 03-19-2015 |
Patent application number | Description | Published |
20120113675 | LAMP DEVICE WITH COLOR-CHANGEABLE FILTER - A lamp device includes a supporting frame, a light emitting diode (LED) array source, a light filter, two end caps and two couples of electrodes. The LED array source is disposed on the supporting frame. The light filter is arc-shaped and combined with the supporting frame as a tubular structure, wherein the arc surface of the light filter is a light emitting surface of the LED array source. The light filter is used for absorbing a ray in a specific wavelength range of the emitting light of the LED array source. The two end caps are disposed at two ends of the tubular structure respectively. The two couples of electrodes are disposed at two ends of the tubular structure and mounted on the two end caps respectively for electrically connecting to the LED array source. | 05-10-2012 |
20120170228 | CIRCUIT MODULE AND ELECTRIC CONNECTOR - A circuit module and an electric connector are provided. The electric connector is used for connecting two circuit boards. The electric connector at least includes two bases and a locking element. The bases are disposed on the periphery of the circuit boards and electrically connected with the circuit boards respectively. The locking element is used for locking the bases, such that the circuit boards are mechanically connected with each other and the electric paths thereof are electrically connected. | 07-05-2012 |
20120243216 | LAMP COVER AND LAMP STRUCTURE - A cover and a lamp structure. The cover whose curvature has a light incident surface and a light outgoing surface, and includes a plurality of 3D micro-structures disposed thereon and arranged in the form of an array. When a light is emitted into the light outgoing surface from the light incident surface, the light emitting angle of the light outgoing surface is increased through the refraction of the 3D micro-structures, so that the occurrence of mura or spots due to uneven distribution of the light is avoid. | 09-27-2012 |
20120243242 | LIGHTING MODULE AND POWER CONNECTING SET - A lighting module and a power connecting set are provided. The lighting module includes two circuit boards, two light emitting elements and a power connecting set. The light emitting elements are disposed on the circuit boards respectively. The power connecting set includes two connecting bases and a flexible circuit board. The connecting bases are disposed on the circuit boards and electronically connected to the circuit boards respectively. Two ends of the flexible circuit board are connected to the connecting bases for electrically connecting a power path of the circuit boards. | 09-27-2012 |
20130083546 | LIGHT SOURCE COOLING DEVICE AND COOLING METHOD THEREOF - A light source cooling device includes a light source module, an inner casing, an outer casing, and a plurality of spacers. The inner casing encloses an accommodation space for accommodating the light source module. The outer casing surrounds the inner casing and has a gap included between an inner wall of the inner casing and the outer casing, wherein the inner casing and the outer casing are made of materials with different thermal conductivity coefficients. The inner wall of the inner casing, an outer wall of the outer casing, and the spacers together form a plurality of heat-dissipating passages. The inner wall absorbs the heat generated by the light source module and generates a temperature gradient between the inner wall and the outer wall, which assists in creating thermal convection to exhaust the heat. | 04-04-2013 |
20130094239 | LIGHT GUIDE COLUMN, LIGHT EMITTING STRUCTURE AND ILLUMINATION DEVICE USING THE SAME - A light guide column is disposed on the top of a light source. The light guide column includes a column body, a cavity, a reflection structure and a micro-structure. The column body has a first end and a second end opposite to the first end. The cavity on the first end is for gathering the light source. The reflection structure is on the second end, when light emitted from the light source, a portion of the light reflected by the reflection structure to emit toward a lateral surface of the column body and others transmitted to the front side direction. The micro-structure is formed on the lateral surface of the column body can facilitate the emitting light from the column body uniformly. | 04-18-2013 |
20130182459 | LIGHTING DEVICE - A lighting device is provided and includes a light guide plate including a plurality of light incident surfaces and two light emitting surfaces, a plurality of edge frames, and at least one light source. Each of the edge frames includes a main body including an accommodating groove and an opening, first and second clamp members, and first and second fixing elements respectively located on first and second ends of the main body. The light emitting surfaces are clamped by the first and second clamp members of each edge frame. Each of the light incident surfaces is inserted in the main body of one of the edge frames through the opening and accommodated in the accommodating groove. The light source is located in the accommodating groove of one of the edge frames and adjacent to the corresponding light incident surface. | 07-18-2013 |
20150354805 | RECESSED LIGHT FIXTURE - A recessed light fixture is provided. The recessed light fixture includes a casing having an inner wall and an outer wall to define a space; a front flange extending outward from the casing and surrounding the space, wherein the front flange has a top surface and a bottom surface; and an intumescent material disposed in a first recess of the outer wall and/or disposed on the top surface of the front flange. | 12-10-2015 |
Patent application number | Description | Published |
20090039925 | SAMPLE-AND-HOLD AMPLIFICATION CIRCUITS - A sample-and-hold amplification circuit comprises an amplifier, a first sample-and-hold unit, and a second sample-and-hold unit. The amplifier has an input terminal and an output terminal. The first sample-and-hold unit is coupled to the input terminal and the output terminal. The second sample-and-hold unit is coupled to the input terminal and the output terminal. When the first sample-and-hold unit is arranged to perform a sampling operation, the second sample-and-hold unit performs a holding operation, and when the first sample-and-hold unit is arranged to perform the holding operation, the second sample-and-hold unit performs the sampling operation. | 02-12-2009 |
20090195315 | SAMPLE-AND-HOLD AMPLIFIERS - A sample-and-hold amplifier is provided. The sample-and-hold amplifier comprises a sample-and-hold circuit and a buffer circuit. The sample-and-hold circuit receives an input signal and transmits the input signal to a first node according to a control signal. The buffer circuit is coupled between a supply voltage source and a ground and controlled by the first node to provide an output signal at an output node. The buffer circuit comprises a native MOS transistor coupled to the output node. | 08-06-2009 |
20100127910 | COMPARATOR AND PIPELINED ADC UTLIZING THE SAME - A comparator includes a plurality of switches, a capacitor, an amplifier, and a latch. The switches provide an input signal during a first period and provide a reference signal during a second period. A first switch among the switches is composed of a first transistor. The capacitor receives the input signal during the first period and receives the reference signal during the second period. The amplifier is coupled to the capacitor for receiving a difference voltage between the input signal and the reference signal and amplifies the difference voltage during the second period to generate an amplified result. The determining circuit provides a digital signal according to the amplified result. | 05-27-2010 |
20100182173 | FLIP-FLOP AND PIPELINED ANALOG-TO-DIGITAL CONVERTER UTILIZING THE SAME - A flip-flop includes a sense amplifier stage and a latch stage. The sense amplifier includes a first P type transistor and generates a first sensed signal and a second sensed signal in a first node and a second node, respectively. When the first P type transistor is turned on, the first node is connected to the second node. The latch stage generates a first output signal and a second output signal according to the first and the second sensed signals. | 07-22-2010 |
20100182179 | PIPELINED ANALOG-TO-DIGITAL CONVERTER - A pipelined analog-to-digital converter includes at least one multiplying digital-to-analog converter and at least one sub-ADC. The multiplying digital-to-analog converter includes at least one first capacitor, at least one second capacitor, an amplifier, and a plurality of switches. The amplifier is coupled to the first and the second capacitors. The switches control a connection between the first and the second capacitors according to a first control signal, a second control signal and a digital signal. In a first period, the first capacitor is connected to the second capacitor in parallel. In a second period, the first capacitor is connected to the second capacitor in series. At least one switch among the switches is composed of a transistor. The sub-ADC provides a digital signal according to the first and second control signals. | 07-22-2010 |
20100328129 | PIPELINE ANALOG-TO-DIGITAL CONVERTER WITH PROGRAMMABLE GAIN FUNCTION - A pipeline analog-to-digital converter (ADC) comprises a plurality of pipeline stages is disclosed. The first pipeline stage has programmable gain function. The first pipeline stage includes a sub-analog-to-digital converter (sub-ADC) and a multiplying digital-to-analog converter (MDAC) implemented by switched capacitor (SC) circuits. Different capacitances in the sub-ADC and MDAC are provided so as to provide different gains by controlling switches in the SC circuits. | 12-30-2010 |
Patent application number | Description | Published |
20100244220 | LAYOUT STRUCTURE AND METHOD OF DIE - A layout structure and layout method are provided. The layout structure includes a first conductive via, a second conductive via, a die and eight pads. The first conductive via and the second conductive via pass through the die. The first conductive via has a first pad and a second pad, and the second conductive via has a third pad and a fourth pad. A fifth pad is conducted to the third pad. A sixth pad is conducted to the second pad. A seventh pad is conducted to the first pad. An eighth pad is conducted to the fourth pad. In a vertical direction of the die, the first pad and the second pad are overlapped, the third pad and the fourth pad are overlapped, the fifth pad and the sixth pad are overlapped, and the eighth pad and the seventh pad are overlapped, partially or totally. | 09-30-2010 |
20100289139 | HARDWIRED SWITCH OF DIE STACK AND OPERATING METHOD OF HARDWIRED SWITCH - A hardwired switch of a die stack including eight landing pads is provided. A first, a second, a third, and a fourth landing pads are disposed on a first surface of a die. The second and the fourth landing pads are electrically connected to the first and the third landing pads respectively. A fifth, a sixth, a seventh, and an eighth landing pads are disposed on a second surface of the die. The seventh and the eighth landing pads are electrically connected to the sixth and the fifth landing pads respectively. In a vertical direction of the die, the first, the second, the third, and the fourth landing pads overlap partially or fully with the fifth, the sixth, the seventh, and the eighth landing pads respectively. In addition, an operating method of a hardwired switch is also provided. | 11-18-2010 |
20100295189 | METHOD FOR REPAIRING CHIP AND STACKED STRUCTURE OF CHIPS - A method for repairing a chip with a stacked structure of chips is provided. First, a first chip is provided, which includes a first circuit block with a first function, a second circuit block with a second function, and a signal path electrically connected to the first and the second circuit blocks. A second chip is provided, which includes a third circuit block with the first function. The functions of the first and the second chips are verified. The first circuit block is disabled if the first circuit block is defective. The third circuit block is electrically connected to the signal path to replace the first circuit block and provide the first function if the second circuit block is functional and the third circuit block is functional. | 11-25-2010 |
20100320565 | WAFER AND METHOD FOR IMPROVING YIELD RATE OF WAFER - A wafer and a method for improving the yield rate of the wafer are provided. The wafer includes a first and a second circuit units, a first and a second through silicon vias (TSVs), and a first spare TSV. The first and the second circuit units are disposed inside the wafer. The first TSV vertically runs through the wafer and is coupled to the first circuit unit through the front metal of the wafer. The second TSV vertically passes through the wafer and is coupled to the second circuit unit through the front metal of the wafer. When the first or the second TSV has failed, the first spare TSV vertically passes through the wafer to replace the failed first or second TSV. | 12-23-2010 |
20110006829 | ISOLATION CIRCUIT - An isolation circuit is provided. The isolation circuit is coupled to an output and an input node and includes a first set, a second switch set, and a body bias voltage generator. The first switch set couples a switch control node to a second voltage when a first voltage is at a first voltage level, and couples the switch control node to the input node when the first voltage is at a second voltage level. The second switch set couples the output node to the input node when the first voltage is at the first voltage level, and isolates the output node from the input node when the first voltage is at the second voltage level. The body bias voltage generator selectively provides a higher one of the first voltage and a voltage on the input node to a body of the second switch set. | 01-13-2011 |
20110080184 | METHOD FOR TESTING THROUGH-SILICON-VIA AND THE CIRCUIT THEREOF - The method and circuit for testing a TSV of the present invention exploit the electronic property of the TSV under test. The TSV under test is first reset to a first state, and is then sensed at only one end to determine whether the TSV under test follows the behavior of a normal TSV, wherein the reset and sense steps are performed at only one end of the TSV under test. If the TSV under test does not follow the behavior of a normal TSV, the TSV under test is determined faulty. | 04-07-2011 |
20110080185 | METHOD FOR TESTING THROUGH-SILICON-VIA AND THE CIRCUIT THEREOF - The method and circuit for testing a TSV of the present invention exploit the electronic property of the TSV under test. The TSV under test is first reset to a first state, and is then sensed at only one end to determine whether the TSV under test follows the behavior of a normal TSV, wherein the reset and sense steps are performed at only one end of the TSV under test. If the TSV under test does not follow the behavior of a normal TSV, the TSV under test is determined faulty. | 04-07-2011 |
20120146207 | STACKED STRUCTURE AND STACKED METHOD FOR THREE-DIMENSIONAL CHIP - A stacked structure and a stacked method for a three-dimensional integrated circuit are provided. The provided stacked method includes separating a logic chip into a function chip and an I/O chip; stacking the function chip above the I/O chip; and stacking at least one memory chip between the function chip and the I/O chip. | 06-14-2012 |
20120193815 | STACKED STRUCTURE OF CHIPS - A stacked structure of chips including a first chip and a second chip is provided. The first chip includes a first and a second circuit blocks, a signal path, a first and a second hardwired switches. The second chip stacks with the first chip stack and includes a third circuit block, a third and a fourth hardwired switches. If the first circuit block is defective and the second and the third circuit blocks are functional, the first hardwired switch and the third hardwired switch are set correspondingly such that a power-supply bonding pad is connected to the third power terminal and disconnected to the first power terminal, and the second hardwired switch and the fourth hardwired switch are set correspondingly such that the third signal terminal is electrically connected to the signal path to make the third circuit block replace the first circuit block and provide the first function. | 08-02-2012 |
20120231563 | OPERATING METHOD OF HARDWIRED SWITCH - An operating method of a hardwired switch is provided. First, a first die is provided. The first die is configured as the first die in the hardwired switch. Next, a function of the first die is inspected to obtain an inspected result. Upon the inspected result, whether a second TSV is selectively disposed between the first landing pad and the fifth landing pad, between the second landing pad and the sixth landing pad, between the third landing pad and the seventh landing pad, or between the fourth landing pad and the eighth landing pad or not is determined. The first die is stacked above a second die, so that the second surface is located between the first die and the second die. | 09-13-2012 |
20130064026 | TECHNOLOGY OF MEMORY REPAIR AFTER STACKING OF THREE-DIMENSIONAL INTEGRATED CIRCUIT - A three-dimensional integrated circuit (3-D IC) includes a controller chip and at least one memory chip, in which, besides an original storage capacity, the memory chip further includes multiple spare memory cells and an address translation circuit with an external activation/enablement function. After the memory chip and the controller chip are stacked, the controller chip may still activate/enable a spare in the memory chip to repair a damaged or deteriorated memory cell in the memory chip through at least one vertical interconnect (for example, through-silicon via (TSV)), regardless of whether the damaged or deteriorated memory cell has been repaired or not before the controller chip and the memory chip are stacked. | 03-14-2013 |
20130161819 | SEMICONDUCTOR DEVICE STACKED STRUCTURE - A semiconductor device stacked structure is disclosed, which includes multiple semiconductor devices and at least one reinforcing structure. The semiconductor devices are stacked on one another. At least one semiconductor device has at least one through silicon via. Each reinforcing structure surrounds a corresponding one of the at least one through silicon via and is electrically insulated from the semiconductor devices. The at least one reinforcing structure includes multiple reinforcing elements and at least one connecting element. Each reinforcing element is disposed between the semiconductor devices. Vertical projections of the reinforcing elements on a plane define a close region, and a projection of the at least one through silicon via on the plane is located within the close region. The connecting element is located in an overlapping region of the vertical projections of the reinforcing elements on the plane, for connecting the reinforcing elements to form the reinforcing structure. | 06-27-2013 |
20130210170 | Apparatus And Method For Repairing An Integrated Circuit - A method for repairing an integrated circuit comprises: fabricating a first circuit, the first circuit including a plurality of regular units and a plurality of redundant units, each of the regular units being identified by an address; performing a first test on the first circuit to determine if a defective regular unit is present; activating, if the defective regular unit is present, at least a first redundant unit to replace the defective regular unit, the first redundant unit being identified by an address of the defective regular unit; performing, if the at least first redundant unit is present, a second test on the first circuit to determine if the first redundant unit is defective; and activating at least a second redundant unit to replace the defective first redundant unit, the second redundant unit being identified by the address of the defective regular unit. | 08-15-2013 |
20130293255 | METHOD FOR TESTING THROUGH-SILICON-VIA - A method for testing a TSV comprises charging a through-silicon-via under test to a first predetermined voltage level charging a capacitance device to a second predetermined voltage level; performing charge-sharing between the through-silicon-via and the capacitance device; and determining that the through-silicon-via under test is not faulty if the voltage level of the through-silicon-via after the charge-sharing step is within a predetermined range. | 11-07-2013 |
20140139259 | TEST METHOD FOR INTERPOSER - A test method for an interposer is provided. The interposer includes a plurality of conductive lines therein and a plurality of connecting contacts thereon, wherein the connecting contacts are electrically connected to the conductive lines. The test method for an interposer provides a passive transponder device. The passive transponder device includes a first circuit including an open/short test circuit and at least a pair of connecting contacts. The test method for an interposer includes contacting the connecting contacts of the first circuit in the passive transponder device with the selected contacts on the interposer to form a checking area and conducting an open-circuit or short-circuit test for the interposer through the checking area. | 05-22-2014 |
20150049569 | MEMORY DEVICE - A memory device including at least one bit-line decoding circuit, at least one word-line decoding circuit, a plurality of memory blocks, and a plurality of switches is provided. The sizes of the plurality of memory blocks include at least one first size and a second size, and the first size is greater than the second size. The plurality of memory blocks with the first size are grouped as at least one first group, and the plurality of memory blocks with the second size are grouped as at least one second group. Compared to the first group, the second group is closer to the bit-line decoding circuit and/or the word-line decoding circuit. The switches are controlled by at least one control signal, so as to enable or disable the first group and/or the second group. | 02-19-2015 |
20150277096 | DISPLAY MAGNIFYING DEVICE - A display magnifying device adapted for an electronic device having one or more external sockets is provided. The display magnifying device includes a magnifying glass, a plug, and a stand. The plug fits the external socket. The stand has a first end connected to the magnifying glass and a second end connected to the plug. The display magnifying device is adapted to be detachably assembled to the electronic device by connecting the plug to the external socket. A display magnifying device including a magnifying glass, a casing and a stand is further provided. The casing at least covers a part of the electronic device. The stand has a first end connected to the magnifying glass and a second end connected to the casing. The display magnifying device is adapted to be detachably assembled to the electronic device by covering the part of the electronic device with the casing. | 10-01-2015 |