Patent application number | Description | Published |
20080312232 | Substituted amide derivatives and methods of use - Selected compounds are effective for prophylaxis and treatment of diseases, such as HGF mediated diseases. The invention encompasses novel compounds, analogs, prodrugs and pharmaceutically acceptable salts thereof, pharmaceutical compositions and methods for prophylaxis and treatment of diseases and other maladies or conditions involving, cancer and the like. The subject invention also relates to processes for making such compounds as well as to intermediates useful in such processes. | 12-18-2008 |
20090124609 | Fused heterocyclic derivatives and methods of use - Selected compounds are effective for prophylaxis and treatment of diseases, such as HGF mediated diseases. The invention encompasses novel compounds, analogs, prodrugs and pharmaceutically acceptable salts thereof, pharmaceutical compositions and methods for prophylaxis and treatment of diseases and other maladies or conditions involving, cancer and the like. The subject invention also relates to processes for making such compounds as well as to intermediates useful in such processes. | 05-14-2009 |
20090124612 | Fused heterocyclic derivatives and methods of use - Selected compounds are effective for prophylaxis and treatment of diseases, such as HGF mediated diseases. The invention encompasses novel compounds, analogs, prodrugs and pharmaceutically acceptable salts thereof, pharmaceutical compositions and methods for prophylaxis and treatment of diseases and other maladies or conditions involving, cancer and the like. The subject invention also relates to processes for making such compounds as well as to intermediates useful in such processes. | 05-14-2009 |
20090176774 | Compounds and methods of use - Selected compounds are effective for prophylaxis and treatment of diseases, such as HGF mediated diseases. The invention encompasses novel compounds, analogs, prodrugs and pharmaceutically acceptable salts thereof, pharmaceutical compositions and methods for prophylaxis and treatment of diseases and other maladies or conditions involving, cancer and the like. The subject invention also relates to processes for making such compounds as well as to intermediates useful in such processes. | 07-09-2009 |
20090318436 | Fused heterocyclic derivatives and methods of use - Selected compounds are effective for prophylaxis and treatment of diseases, such as HGF mediated diseases. The invention encompasses novel compounds, analogs, prodrugs and pharmaceutically acceptable salts thereof, pharmaceutical compositions and methods for prophylaxis and treatment of diseases and other maladies or conditions involving, cancer and the like. The subject invention also relates to processes for making such compounds as well as to intermediates useful in such processes. | 12-24-2009 |
20110118252 | SUBSTITUTED AMIDE DERIVATIVES AND METHODS OF USE - Selected compounds are effective for prophylaxis and treatment of diseases, such as HGF mediated diseases. The invention encompasses novel compounds, analogs, prodrugs and pharmaceutically acceptable salts thereof, pharmaceutical compositions and methods for prophylaxis and treatment of diseases and other maladies or conditions involving, cancer and the like. The subject invention also relates to processes for making such compounds as well as to intermediates useful in such processes. | 05-19-2011 |
20110118285 | HETEROCYCLES AS PROTEIN KINASE INHIBITORS - Selected fused imidazole or triazole derivatives are effective for prophylaxis and treatment of diseases, such as HGF mediated diseases. The invention encompasses novel compounds, analogs, prodrugs and pharmaceutically acceptable salts thereof, pharmaceutical compositions and methods for prophylaxis and treatment of diseases and other maladies or conditions involving, cancer and the like. The subject invention also relates to processes for making such compounds as well as to intermediates useful in such processes. | 05-19-2011 |
20120070413 | METHOD OF TREATING CANCER WITH SUBSTITUTED AMIDE DERIVATIVES - Selected compounds are effective for prophylaxis and treatment of diseases, such as HGF mediated diseases. The invention encompasses novel compounds, analogs, prodrugs and pharmaceutically acceptable salts thereof, pharmaceutical compositions and methods for prophylaxis and treatment of diseases and other maladies or conditions involving, cancer and the like. The subject invention also relates to processes for making such compounds as well as to intermediates useful in such processes. | 03-22-2012 |
20120107275 | FUSED HETEROCYCLIC DERIVATIVES AND METHODS OF USE - Selected compounds are effective for prophylaxis and treatment of diseases, such as HGF mediated diseases. The invention encompasses novel compounds, analogs, prodrugs and pharmaceutically acceptable salts thereof, pharmaceutical compositions and methods for prophylaxis and treatment of diseases and other maladies or conditions involving, cancer and the like. The subject invention also relates to processes for making such compounds as well as to intermediates useful in such processes. | 05-03-2012 |
20120148531 | FUSED HETEROCYCLIC DERIVATIVES AND METHODS OF USE - Selected compounds are effective for prophylaxis and treatment of diseases, such as HGF mediated diseases. The invention encompasses novel compounds, analogs, prodrugs and pharmaceutically acceptable salts thereof, pharmaceutical compositions and methods for prophylaxis and treatment of diseases and other maladies or conditions involving, cancer and the like. The subject invention also relates to processes for making such compounds as well as to intermediates useful in such processes. | 06-14-2012 |
20120190666 | Heteroaryl Compounds as PIKK Inhibitors - The present invention provides compounds that are PIKK inhibitors, more specifically, mTOR and/or PI3Kα kinase inhibitors and are therefore useful for the treatment of diseases treatable by inhibition of kinases, specifically PI3 kinases, more specifically, mTOR and/or PI3Kα, such as cancer. Also provided are pharmaceutical compositions containing such compounds and processes for preparing such compounds. | 07-26-2012 |
20130217668 | BENZIMIDAZOLE AND AZABENZIMIDAZOLE COMPOUNDS THAT INHIBIT ANAPLASTIC LYMPHOMA KINASE - Compounds of Formula (I) are useful inhibitors of anaplastic lymphoma kinase. Compounds of Formula (I) have the following structure: where the definitions of the variables are provided herein. | 08-22-2013 |
20130303529 | FUSED HETEROCYCLIC DERIVATIVES AND METHODS OF USE - Selected compounds are effective for prophylaxis and treatment of diseases, such as HGF mediated diseases. The invention encompasses novel compounds, analogs, prodrugs and pharmaceutically acceptable salts thereof, pharmaceutical compositions and methods for prophylaxis and treatment of diseases and other maladies or conditions involving, cancer and the like. The subject invention also relates to processes for making such compounds as well as to intermediates useful in such processes. | 11-14-2013 |
20140107109 | AMINO-DIHYDROTHIAZINE AND AMINO-DIOXIDO DIHYDROTHIAZINE COMPOUNDS AS BETA-SECRETASE ANTAGONISTS AND METHODS OF USE - The present invention provides a new class of compounds useful for the modulation of beta-secretase enzyme (BACE) activity. The compounds have a general Formula I: | 04-17-2014 |
Patent application number | Description | Published |
20130109299 | SYSTEM AND METHOD FOR GATEWAY RF DIVERSITY USING A CONFIGURABLE SPOT BEAM SATELLITE | 05-02-2013 |
20130286830 | METHOD AND APPARATUS FOR DYNAMIC LOAD BALANCING OF COMMUNICATIONS CHANNELS FOR CONTROLLING TRAFFIC LOAD IN A COMMUNICATIONS SYSTEM - A method and apparatus for dynamically balancing traffic loads in a communications system (such as satellite communications systems), based on a control of collision rates via the real-time control of throughput of channels of the communications system (such as a real time throughput of random access channels in a satellite network). The method and apparatus generates and transmits to remote nodes or terminals an operating probability based on the determined throughput for transmission using the communications channel. Also, the method and apparatus includes receiving by at least one terminal the generated operating probability and determining by the at least one terminal a transmission probability for the communications channel based upon the received operating probability, which can further be adjusted by one or more of a received upper or lower limit of the generated operating probability or a collision rate for the communications channel. | 10-31-2013 |
20130286833 | METHOD AND APPARATUS FOR DYNAMIC ASSOCIATION OF TERMINAL NODES WITH AGGREGATION NODES AND LOAD BALANCING - A system and method for association of remote nodes with respective aggregation nodes in a high capacity shared bandwidth communications network, which meets various requirements and desires associated with efficient, robust, reliable and flexible broadband services, and which is relatively efficient and automated from a network management and load balancing standpoint, is provided. A remote node receives a message transmitted by a gateway over the communications network, wherein the message includes service codes identifying one or more service capabilities of the gateway. The remote node determines, based on the service codes, whether the gateway is an eligible gateway for servicing one or more service requirements of the remote node. The remote node then adds the gateway to a pool of eligible gateways within the communications network. | 10-31-2013 |
20140173134 | METHOD AND SYSTEM FOR OPTIMIZED OPPORTUNISTIC TRANSMISSION OF DOMAIN NAME REFERENCE INFORMATION - A system and method for efficiently and opportunistically delivering DNS reference information to a plurality of DNS proxies. A DNS proxy receives first DNS reference information associated with at least a first target hostname, wherein the first DNS reference information is based, at least in part, on a first DNS query of a further DNS proxy, other than the one DNS proxy. Further, the DNS proxy stores the first DNS reference information at a respective storage device. | 06-19-2014 |
Patent application number | Description | Published |
20120110586 | THREAD GROUP SCHEDULER FOR COMPUTING ON A PARALLEL THREAD PROCESSOR - A parallel thread processor executes thread groups belonging to multiple cooperative thread arrays (CTAs). At each cycle of the parallel thread processor, an instruction scheduler selects a thread group to be issued for execution during a subsequent cycle. The instruction scheduler selects a thread group to issue for execution by (i) identifying a pool of available thread groups, (ii) identifying a CTA that has the greatest seniority value, and (iii) selecting the thread group that has the greatest credit value from within the CTA with the greatest seniority value. | 05-03-2012 |
20130117541 | SPECULATIVE EXECUTION AND ROLLBACK - One embodiment of the present invention sets forth a technique for speculatively issuing instructions to allow a processing pipeline to continue to process some instructions during rollback of other instructions. A scheduler circuit issues instructions for execution assuming that, several cycles later, when the instructions reach multithreaded execution units, that dependencies between the instructions will be resolved, resources will be available, operand data will be available, and other conditions will not prevent execution of the instructions. When a rollback condition exists at the point of execution for an instruction for a particular thread group, the instruction is not dispatched to the multithreaded execution units. However, other instructions issued by the scheduler circuit for execution by different thread groups, and for which a rollback condition does not exist, are executed by the multithreaded execution units. The instruction incurring the rollback condition is reissued after the rollback condition no longer exists. | 05-09-2013 |
20130145102 | MULTI-LEVEL INSTRUCTION CACHE PREFETCHING - One embodiment of the present invention sets forth an improved way to prefetch instructions in a multi-level cache. Fetch unit initiates a prefetch operation to transfer one of a set of multiple cache lines, based on a function of a pseudorandom number generator and the sector corresponding to the current instruction L1 cache line. The fetch unit selects a prefetch target from the set of multiple cache lines according to some probability function. If the current instruction L1 cache | 06-06-2013 |
20130145124 | SYSTEM AND METHOD FOR PERFORMING SHAPED MEMORY ACCESS OPERATIONS - One embodiment of the present invention sets forth a technique that provides an efficient way to retrieve operands from a register file. Specifically, the instruction dispatch unit receives one or more instructions, each of which includes one or more operands. Collectively, the operands are organized into one or more operand groups from which a shaped access may be formed. The operands are retrieved from the register file and stored in a collector. Once all operands are read and collected in the collector, the instruction dispatch unit transmits the instructions and corresponding operands to functional units within the streaming multiprocessor for execution. One advantage of the present invention is that multiple operands are retrieved from the register file in a single register access operation without resource conflict. Performance in retrieving operands from the register file is improved by forming shaped accesses that efficiently retrieve operands exhibiting recognized memory access patterns. | 06-06-2013 |
20130159628 | METHODS AND APPARATUS FOR SOURCE OPERAND COLLECTOR CACHING - Methods and apparatus for source operand collector caching. In one embodiment, a processor includes a register file that may be coupled to storage elements (i.e., an operand collector) that provide inputs to the datapath of the processor core for executing an instruction. In order to reduce bandwidth between the register file and the operand collector, operands may be cached and reused in subsequent instructions. A scheduling unit maintains a cache table for monitoring which register values are currently stored in the operand collector. The scheduling unit may also configure the operand collector to select the particular storage elements that are coupled to the inputs to the datapath for a given instruction. | 06-20-2013 |
20130159684 | BATCHED REPLAYS OF DIVERGENT OPERATIONS - One embodiment of the present invention sets forth an optimized way to execute replay operations for divergent operations in a parallel processing subsystem. Specifically, the streaming multiprocessor (SM) includes a multistage pipeline configured to batch two or more replay operations for processing via replay loop. A logic element within the multistage pipeline detects whether the current pipeline stage is accessing a shared resource, such as loading data from a shared memory. If the threads are accessing data which are distributed across multiple cache lines, then the multistage pipeline batches two or more replay operations, where the replay operations are inserted into the pipeline back-to-back. Advantageously, divergent operations requiring two or more replay operations operate with reduced latency. Where memory access operations require transfer of more than two cache lines to service all threads, the number of clock cycles required to complete all replay operations is reduced. | 06-20-2013 |
20130166877 | SHAPED REGISTER FILE READS - One embodiment of the present invention sets forth a technique for performing a shaped access of a register file that includes a set of N registers, wherein N is greater than or equal to two. The technique involves, for at least one thread included in a group of threads, receiving a request to access a first amount of data from each register in the set of N registers, and configuring a crossbar to allow the at least one thread to access the first amount of data from each register in the set of N registers. | 06-27-2013 |
20130166881 | METHODS AND APPARATUS FOR SCHEDULING INSTRUCTIONS USING PRE-DECODE DATA - Systems and methods for scheduling instructions using pre-decode data corresponding to each instruction. In one embodiment, a multi-core processor includes a scheduling unit in each core for selecting instructions from two or more threads each scheduling cycle for execution on that particular core. As threads are scheduled for execution on the core, instructions from the threads are fetched into a buffer without being decoded. The pre-decode data is determined by a compiler and is extracted by the scheduling unit during runtime and used to control selection of threads for execution. The pre-decode data may specify a number of scheduling cycles to wait before scheduling the instruction. The pre-decode data may also specify a scheduling priority for the instruction. Once the scheduling unit selects an instruction to issue for execution, a decode unit fully decodes the instruction. | 06-27-2013 |
20130166882 | METHODS AND APPARATUS FOR SCHEDULING INSTRUCTIONS WITHOUT INSTRUCTION DECODE - Systems and methods for scheduling instructions without instruction decode. In one embodiment, a multi-core processor includes a scheduling unit in each core for scheduling instructions from two or more threads scheduled for execution on that particular core. As threads are scheduled for execution on the core, instructions from the threads are fetched into a buffer without being decoded. The scheduling unit includes a macro-scheduler unit for performing a priority sort of the two or more threads and a micro-scheduler arbiter for determining the highest order thread that is ready to execute. The macro-scheduler unit and the micro-scheduler arbiter use pre-decode data to implement the scheduling algorithm. The pre-decode data may be generated by decoding only a small portion of the instruction or received along with the instruction. Once the micro-scheduler arbiter has selected an instruction to dispatch to the execution unit, a decode unit fully decodes the instruction. | 06-27-2013 |
20130212364 | PRE-SCHEDULED REPLAYS OF DIVERGENT OPERATIONS - One embodiment of the present disclosure sets forth an optimized way to execute pre-scheduled replay operations for divergent operations in a parallel processing subsystem. Specifically, a streaming multiprocessor (SM) includes a multi-stage pipeline configured to insert pre-scheduled replay operations into a multi-stage pipeline. A pre-scheduled replay unit detects whether the operation associated with the current instruction is accessing a common resource. If the threads are accessing data which are distributed across multiple cache lines, then the pre-scheduled replay unit inserts pre-scheduled replay operations behind the current instruction. The multi-stage pipeline executes the instruction and the associated pre-scheduled replay operations sequentially. If additional threads remain unserviced after execution of the instruction and the pre-scheduled replay operations, then additional replay operations are inserted via the replay loop, until all threads are serviced. One advantage of the disclosed technique is that divergent operations requiring one or more replay operations execute with reduced latency. | 08-15-2013 |
20130262831 | METHODS AND APPARATUS TO AVOID SURGES IN DI/DT BY THROTTLING GPU EXECUTION PERFORMANCE - Systems and methods for throttling GPU execution performance to avoid surges in DI/DT. A processor includes one or more execution units coupled to a scheduling unit configured to select instructions for execution by the one or more execution units. The execution units may be connected to one or more decoupling capacitors that store power for the circuits of the execution units. The scheduling unit is configured to throttle the instruction issue rate of the execution units based on a moving average issue rate over a large number of scheduling periods. The number of instructions issued during the current scheduling period is less than or equal to a throttling rate maintained by the scheduling unit that is greater than or equal to a minimum throttling issue rate. The throttling rate is set equal to the moving average plus an offset value at the end of each scheduling period. | 10-03-2013 |
20140164743 | REORDERING BUFFER FOR MEMORY ACCESS LOCALITY - Systems and methods for scheduling instructions for execution on a multi-core processor reorder the execution of different threads to ensure that instructions specified as having localized memory access behavior are executed over one or more sequential clock cycles to benefit from memory access locality. At compile time, code sequences including memory access instructions that may be localized are delineated into separate batches. A scheduling unit ensures that multiple parallel threads are processed over one or more sequential scheduling cycles to execute the batched instructions. The scheduling unit waits to schedule execution of instructions that are not included in the particular batch until execution of the batched instructions is done so that memory access locality is maintained for the particular batch. In between the separate batches, instructions that are not included in a batch are scheduled so that threads executing non-batched instructions are also processed and not starved. | 06-12-2014 |
20140189698 | APPROACH FOR A CONFIGURABLE PHASE-BASED PRIORITY SCHEDULER - A streaming multiprocessor (SM) in a parallel processing subsystem schedules priority among a plurality of threads. The SM retrieves a priority descriptor associated with a thread group, and determines whether the thread group and a second thread group are both operating in the same phase. If so, then the method determines whether the priority descriptor of the thread group indicates a higher priority than the priority descriptor of the second thread group. If so, the SM skews the thread group relative to the second thread group such that the thread groups operate in different phases, otherwise the SM increases the priority of the thread group. f the thread groups are not operating in the same phase, then the SM increases the priority of the thread group. One advantage of the disclosed techniques is that thread groups execute with increased efficiency, resulting in improved processor performance. | 07-03-2014 |
Patent application number | Description | Published |
20130188777 | NON-LINEAR DATA ACQUISITION - One or more techniques and/or systems described herein implement, among other things, a parabolic curve for a ramp signal in a data acquisition component, where the curve can be effectively calibrated and used to provide a settling period to mitigate noise. That is, a ramp generator can generate a ramp signal that has a parabolic voltage curve with two substantially mirroring halves. A comparator can compare a first portion of the parabolic voltage curve with a voltage signal indicative of a number of photons detected by a detection array. A second portion of the parabolic voltage curve is used as a temporal delay so that circuitry, such as the ramp generator, can settle. | 07-25-2013 |
20130264483 | TILE FOR DETECTOR ARRAY OF IMAGING MODALITY HAVING SELECTIVELY REMOVABLE/REPLACEABLE TILE SUB-ASSEMBLIES - Among other things, one or more tiles for an indirect-conversation radiation detector array are provided herein. Respective tiles comprise a detector sub-assembly and an electronic sub-assembly, which are operably coupled together, yet selectively removable, via a connection interface. When an electronic sub-assembly portion of a tile, which comprises a signal acquisition system (e.g., an integrated circuit, such as an application specific integrated circuit (ASIC)), functions improperly, the electronic sub-assembly portion of the tile may be selectively removed for repair/replacement without removing and/or replacing the detector sub-assembly (e.g., which may be much more costly to replace). Similarly, when the detector sub-assembly portion of a tile functions improperly, the detector sub-assembly portion of the tile may be selectively removed for repair/replacement without removing and/or replacing the electronic sub-assembly portion of the tile (e.g., although some manipulation of the properly functioning sub-assembly may occur). | 10-10-2013 |