Patent application number | Description | Published |
20080276156 | LOW DENSITY PARITY CHECK DECODER FOR REGULAR LDPC CODES - A method and system for decoding low density parity check (“LDPC”) codes. An LDPC decoder includes an R select unit, a Q message first-in first-out (“FIFO”) memory, and a cyclic shifter. The R select unit provides an R message by selecting from a plurality of possible R message values. The Q message memory stores a Q message until an R message is generated by a CNU, the Q message and the R message are combined to provide a P message. The cyclic shifter shifts the P message. | 11-06-2008 |
20080301521 | LOW DENSITY PARITY CHECK DECODER FOR IRREGULAR LDPC CODES - A method and system for decoding low density parity check (“LDPC”) codes. An LDPC decoder includes a control unit that controls decoder processing, the control unit causing the decoder to process the blocks of a low density parity check (“LDPC”) matrix out of order. A decoder embodiment may process the layers of the LDPC matrix out of order and/or perform partial state processing on out of order blocks of the LDPC matrix and/or generate R messages out of order. | 12-04-2008 |
20130097469 | LOW DENSITY PARITY CHECK DECODER FOR REGULAR LDPC CODES - A method and system for decoding low density parity check (“LDPC”) codes. An LDPC decoder includes an R select unit, a Q message first-in first-out (“FIFO”) memory, and a cyclic shifter. The R select unit provides an R message by selecting from a plurality of possible R message values. The Q message memory stores a Q message until an R message is generated by a CNU, the Q message and the R message are combined to provide a P message. The cyclic shifter shifts the P message. | 04-18-2013 |
20130151922 | LOW DENSITY PARITY CHECK DECODER FOR IRREGULAR LDPC CODES - A method and system for decoding low density parity check (“LDPC”) codes. An LDPC decoder includes a control unit that controls decoder processing, the control unit causing the decoder to process the blocks of a low density parity check (“LDPC”) matrix out of order. A decoder embodiment may process the layers of the LDPC matrix out of order and/or perform partial state processing on out of order blocks of the LDPC matrix and/or generate R messages out of order. | 06-13-2013 |
20140181612 | LOW DENSITY PARITY CHECK DECODER - A method and system for decoding low density parity check (“LDPC”) codes. An LDPC decoder includes an R select unit, a Q message first-in first-out (“FIFO”) memory, and a cyclic shifter. The R select unit provides an R message by selecting from a plurality of possible R message values. The Q message memory stores a Q message until an R message is generated by a CNU, the Q message and the R message are combined to provide a P message. The cyclic shifter shifts the P message. | 06-26-2014 |
20150311917 | LOW DENSITY PARITY CHECK DECODER - A method and system for decoding low density parity check (“LDPC”) codes. A method and system for decoding low density parity check (“LDPC”) codes. An LDPC code decoder includes decoding circuitry configured to process blocks of an LDPC matrix. The decoding circuitry includes a control unit that controls processing by the decoding circuitry. The control unit is configured to cause the decoding circuitry to process blocks of a layer of the LDPC matrix out of order | 10-29-2015 |
Patent application number | Description | Published |
20110223138 | Mesenchymal stem cells that express increased amounts of anti-apoptotic proteins - The invention includes a purified population of mesenchymal stromal cells that have been cultured under conditions, such as having been contacted with an apoptotic cell, to express increased levels of at least one anti-apoptotic protein. Such mesenchymal stem cells may be used to treat diseases, disorders, or conditions associated with apoptosis or with unresolved inflammation. | 09-15-2011 |
20150119343 | Production of TSG-6 Protein - A method of producing a protein or polypeptide, such as, for example, TSG-6 protein, or a biologically active fragment, derivative or analogue thereof, by introducing into mammalian cells a polynucleotide encoding the biologically active protein or polypeptide or biologically active fragment, derivative, or analogue thereof. The cells then are suspended in a protein-free medium that includes at least one agent that suppresses production of hyaluronic acid, hyaluronan, or a salt thereof by the cells. The cells are cultured for a time sufficient to express the biologically active protein or polypeptide or biologically active fragment, derivative or analogue thereof. The biologically active protein or polypeptide, or fragment, derivative, or analogue thereof then is recovered from the cells, such as, for example, by recovering the protein or polypeptide secreted by the cells from the cell culture medium. | 04-30-2015 |
20160075750 | Production of TSG-6 Protein - A method of producing a protein or polypeptide, such as, for example, TSG-6 protein, or a biologically active fragment, derivative or analogue thereof, by introducing into mammalian cells a polynucleotide encoding the biologically active protein or polypeptide or biologically active fragment, derivative, or analogue thereof. The cells then are suspended in a protein-free medium that includes at least one agent that suppresses production of hyaluronic acid, hyaluronan, or a salt thereof by the cells. The cells are cultured for a time sufficient to express the biologically active protein or polypeptide or biologically active fragment, derivative or analogue thereof. The biologically active protein or polypeptide, or fragment, derivative, or analogue thereof then is recovered from the cells, such as, for example, by recovering the protein or polypeptide secreted by the cells from the cell culture medium. | 03-17-2016 |
Patent application number | Description | Published |
20080233747 | Semiconductor Device Manufactured Using an Improved Plasma Etch Process for a Fully Silicided Gate Flow Process - In one aspect, there us provided a method of manufacturing a semiconductor device that comprises placing an oxide layer over a gate electrode and sidewall spacers located adjacent thereto, placing a protective layer over the oxide layer, conducting a plasma etch to remove portions of the protective layer and the first oxide layer that are located over the gate electrode and expose a surface of the gate electrode, wherein the plasma etch is selective to polysilicon. A soft etch is conducted subsequent to the plasma etch. The soft etch includes an inorganic-based fluorine containing gas and an inert gas, wherein the plasma etch leaves a film on the gate electrode that inhibits silicidation of the gate electrode and wherein the soft etch removes the film. The gate electrode is silicided with a metal subsequent to conducting the soft etch. | 09-25-2008 |
20080242072 | PLASMA DRY ETCH PROCESS FOR METAL-CONTAINING GATES - A method of manufacturing a semiconductor device. The method comprises forming a gate stack layer. The gate stack has an insulating layer on a substrate, a metal-containing layer on the insulating layer, a metal nitride barrier layer on the metal-containing layer, and a silicon-containing layer on the metal nitride barrier layer. The method also comprises patterning the gate stack layer. Pattering includes a plasma etch of the metal nitride barrier layer. The plasma etch has a chloride-containing feed gas and a physical etch component. The physical etch component includes a high-mass species having a molecular weight of greater than about 71 gm/mol. | 10-02-2008 |
20100167514 | POST METAL GATE VT ADJUST ETCH CLEAN - A method for fabricating a CMOS integrated circuit (IC) includes providing a substrate having a semiconductor surface, wherein the semiconductor surface has PMOS regions for PMOS devices and NMOS regions for NMOS devices. A gate dielectric layer is formed on the semiconductor surface followed by forming at least a first metal including layer on the gate dielectric layer. A polysilicon or amorphous silicon layer is formed on the first metal including layer to form an intermediate gate electrode stack. A masking pattern is formed on the intermediate gate electrode stack. The polysilicon or amorphous silicon layer is dry etched using the masking pattern to define a patterned intermediate gate electrode stack over the NMOS or PMOS regions, wherein the dry etching stops on a portion of the first metal comprising layer. The masking pattern is removed using a first post etch clean for stripping the masking pattern. A multi-step solution cleaning sequence is used after the removing step and includes a first wet clean including sulfuric acid and a fluoride, and a second wet clean after the first wet clean including a fluoride. Fabrication of the IC is then completed. | 07-01-2010 |
20100167519 | POST HIGH-K DIELECTRIC/METAL GATE CLEAN - A method for fabricating a CMOS integrated circuit (IC) includes the step of providing a substrate having a semiconductor surface. A gate stack including a metal gate electrode on a metal including high-k dielectric layer is formed on the semiconductor surface. Dry etching is used to pattern the gate stack to define a patterned gate electrode stack having exposed sidewalls of the metal gate electrode. The dry etching forms post etch residuals some of which are deposited on the substrate. The substrate including the patterned gate electrode stack is exposed to a solution cleaning sequence including a first clean step including a first acid and a fluoride for removing at least a portion of the post etch residuals, wherein the first clean step has a high selectivity to avoid etching the exposed sidewalls of the metal gate electrode. A second clean after the first clean consists essentially of a fluoride which removes residual high-k material on the semiconductor surface. | 07-01-2010 |
20150371889 | METHODS FOR SHALLOW TRENCH ISOLATION FORMATION IN A SILICON GERMANIUM LAYER - Methods for processing a substrate include (a) providing a substrate comprising a silicon germanium layer and a patterned mask layer atop the silicon germanium layer to define a feature in the silicon germanium layer; (b) exposing the substrate to a first plasma formed from a first process gas to etch a feature into the silicon germanium layer; (c) subsequently exposing the substrate to a second plasma formed from a second process gas to form an oxide layer on a sidewall and a bottom of the feature; (d) exposing the substrate to a third plasma formed from a third process gas to etch the oxide layer from the bottom of the feature; and (e) repeating (b)-(d) to form the feature in the first layer to a desired depth, wherein the first process gas, the second process gas and the third process gas are not the same. | 12-24-2015 |
Patent application number | Description | Published |
20080204127 | Method for Ultimate Noise Isolation in High-Speed Digital Systems on Packages and Printed Circuit Boards (PCBS) - Improved noise isolation for high-speed digital systems on packages and printed circuit boards is provided by the use of mixed alternating impedance electromagnetic bandgap (AI-EBG) structures and a power island configured to provide ultimate noise isolation. A power island is surrounded by a plurality of mixed AI-EBG structures to provide a power distribution network. In this structure, the gap around the power island provides excellent isolation from DC to the first cavity resonant frequency which is determined by the size of the structure and dielectric material. One AI-EBG structure provides excellent isolation from the first cavity resonant frequency of around 1.5 GHz to 5 GHz. The other AI-EBG structure provides excellent noise isolation from 5 GHz to 10 GHz. Through use of this novel configuration of AI-EBG structures, a combination effect of the hybrid AI-EBG structure provides excellent isolation far in excess of 10 GHz. The AI-EBG structure is a metallic-dielectric EBG structure that comprises two metal layers separated by a thin dielectric material (similar to power/ground planes in packages and PCBs). However, in the AI-EBG structure, only one of the metal layers has a periodic pattern which is preferably a two-dimensional rectangular lattice with each element consisting of a metal patch with four connecting metal branches. | 08-28-2008 |
20090307636 | SOLUTION EFFICIENCY OF GENETIC ALGORITHM APPLICATIONS - A method of optimizing a very large scale integrated circuit design takes a circuit description which includes interconnected circuit components and characteristic variables assigned to the circuit components such as environmental, operational or process parameters, computes a first solution for the characteristic variables using a statistical analysis, and then computes a second solution for the characteristic variables using an evolutionary analysis seeded by the first solution. In the exemplary implementation the statistical analysis is a central composite design (CCD) and the evolutionary analysis is a genetic algorithm. Best case and worst case CCD solutions may be used to seed separate genetic algorithm runs and derive global best case and global worst case solutions. These solutions may be compared for sensitivity analysis. The method thereby provides significant reduction in time-to-solution with accurate simulation results. | 12-10-2009 |
20100195756 | REDUCED WIRING REQUIREMENTS WITH SIGNAL SLOPE MANIPULATION - An information handling system device includes a plurality of electronic components; an electric circuit including at least one trace for connecting two or more of the plurality of electronic components and transmitting data between the plurality of electronic components via at least one electric signal; and a substrate including an insulating material for serving as a base for the electric circuit and the plurality of electronic components, wherein the at least one electric signal transmitted between the plurality of electronic components is transmitted utilizing slope manipulation to provide a slope directly proportional to a data value. | 08-05-2010 |
20100229131 | SWARM INTELLIGENCE FOR ELECTRICAL DESIGN SPACE MODELING AND OPTIMIZATION - A method, system, and computer program product for exploring and optimizing an electrical design space. A computer receiving a design space assigns a plurality of initial values (random or predetermined) for optimizing the design space. A particle swarm containing a plurality of particles is created and an optimization of the design space is then performed using the assigned initial values. Following completion of optimization, the global best and personal best for each particle are updated. Velocity vectors and position vectors of the design space are then updated before the computer performs the optimization process again. The process loops, continually updating global and personal bests and velocity and position vectors until a termination criteria is reached. Upon reaching the termination criteria, the best fitness of each particle of the swarm is assigned as an optimized design space. In an alternate embodiment, the particle with the worst target fitness may be assigned. | 09-09-2010 |
20100294557 | Transmission Cable with Spirally Wrapped Shielding - Embodiments of the invention are directed to transmission cables, and particularly to twinax cables, for transmitting digital data and other information between components in a data processing environment. One embodiment of the invention is directed to an information transmission cable that comprises first and second signal carrying conductors of specified length, each of the signal carrying conductors being disposed to carry information signals and having a longitudinal axis. The embodiment further includes an insulating structure comprising an amount of specified dielectric insulation material, the insulating structure being positioned to surround the first and second signal carrying conductors along their respective lengths, and acting to maintain the first and second signal conductors in spaced apart parallel relationship with each other. A first drain conductor is positioned proximate to the first signal carrying conductor in spaced apart parallel relationship, and is further positioned in a first prespecified relationship with a reference line that intersects the respective longitudinal axes of the first and second signal carrying conductors, and that lies in a plane orthogonal thereto. In similar manner, a second drain conductor is positioned proximate to the second signal carrying conductor in spaced apart parallel relationship, and is further positioned in a second prespecified relationship with the reference line. Shielding material is spirally wrapped around the first and second signaling conductors, the first and second drain conductors and the insulating structure. | 11-25-2010 |
20110061898 | REDUCING CROSS-TALK IN HIGH SPEED CERAMIC PACKAGES USING SELECTIVELY-WIDENED MESH - One embodiment of the invention provides a multi-layered ceramic package. The ceramic package includes a signal layer having a plurality of signal lines and a mesh reference layer parallel to the signal layer. The mesh reference layer includes a plurality of intersecting reference lines of varying reference-line width in the plane of the mesh layer. The mesh reference lines may be widened in locations of probable signal cross-talk. Other embodiments of the invention include software for optimizing a ceramic package design by selectively widening mesh lines in regions of probable cross-talk, and systems for designing and manufacturing such a ceramic package. | 03-17-2011 |
20110083888 | Noise Coupling Reduction and Impedance Discontinuity Control in High-Speed Ceramic Modules - An improved multi-layered ceramic package comprises: a plurality of signal layers, each having one or more signal lines; a plurality of vias, each providing one of a voltage (Vdd) power connection or a ground (Gnd) connection; at least one reference mesh layer adjacent to one or more signal layers; and a plurality of via-connected coplanar-type shield (VCS) lines, with a first VCS line extending on a first side of a first signal line within the plurality of signal layers and a second VCS line extending on a second opposing side of the first signal line. Each of the plurality of VCS lines interconnect with and extend past one or more vias that are located along the directional path in which the VCS lines runs. The placement of the VCS lines relative to the signal lines reduces coupling noise and controls impedance discontinuity in the ceramic package. | 04-14-2011 |
20110132650 | High-Speed Ceramic Modules with Hybrid Referencing Scheme for Improved Performance and Reduced Cost - A multi-layered ceramic package comprises: a signal layer with identified chip/device area(s)/site(s) that require a supply of power; and a voltage power (Vdd) layer and a ground (Gnd) layer disposed on opposite sides directly above or below (adjacent to) the signal layer and providing a first reference mesh plane and a second reference mesh plane configured utilizing a hybrid mesh scheme. The hybrid mesh scheme comprises different mesh configurations from among: a full dense mesh in a first area directly above or below the identified chip/device area(s); a half dense mesh in a second area that is above or below the edge(s) of the chip/device area; and a wider mesh pitch in all other areas, and the Vdd traces are aligned to run parallel and adjacent to signal lines in those other areas. Wider traces are provided within the mesh areas that run parallel and adjacent to signal lines. | 06-09-2011 |
20110161055 | SPACE SOLUTION SEARCH - A statistical approach can be used to efficiently supply an initial population that provides a good global description of a design space. The SI based simulation can then find a global best design within a reduced number of simulations. The statistical approach can be utilized to determine a plurality of potential best and worst case designs from a design space. The plurality of potential best and worst case designs from the design space seed or prime a SI based simulation. The best case designs are based on design parameters than can be controlled. The worst case designs are based on design parameters than cannot be controlled due. SI based simulations can then be run on the best case designs with respect to the worst case designs to determine probability of failure of the best case design. | 06-30-2011 |
20110222224 | CORELESS MULTI-LAYER CIRCUIT SUBSTRATE WITH MINIMIZED PAD CAPACITANCE - A multi layer interconnecting substrate has at least two spaced apart metal layers with a conductive pad on each one of the metal layers. Two different types of insulating layers are placed between the metal layers. The placement is such that one of the two different types of insulating layers is placed between the conductive pads and the other type of insulating layer is placed between the two spaced apart metal layers. | 09-15-2011 |
20110289463 | ELECTRICAL DESIGN SPACE EXPLORATION - A method for electrical design space exploration includes receiving a template for an electrical design. Design component parameters associated with at least one component in the electrical design are also received. Weighted factors are assigned to design complexity parameters of the electrical design. The parameters of the complexity can include at least one of following: whether the electrical design is known, a number of the design component parameters, a level of interaction among the design component parameters, a time constraint and a memory restriction of a simulation, and whether a statistical analysis or a worst case approach is used to analyze an output of the simulation. A simulation approach for design space exploration of the electrical design is selected based on the weighted factors for the parameters of the complexity of the electrical design. The simulation is performed based on the selected simulation approach. | 11-24-2011 |
20120125677 | CROSSTALK REDUCTION BETWEEN SIGNAL LAYERS IN A MULTILAYERED PACKAGE BY VARIABLE-WIDTH MESH PLANE STRUCTURES - A first selection of mesh line segments of a mesh layer are of a first width and a second selection of mesh line segments of the mesh layer are of a second width, wherein the second width is greater than the first width. The second selection of mesh line segments of the second width are positioned in parallel to a selection of signal lines in a signal layer that are likely to introduce crosstalk, wherein the widening of the mesh line segments shadowing the selection of signal lines increases the likelihood that the return current associated with the signal will flow in the wider mesh line segment, thereby increasing the likelihood of containing the electromagnetic fields associated with the signal such that crosstalk to other signals is reduced or contained. | 05-24-2012 |
20120204141 | Noise Coupling Reduction and Impedance Discontinuity Control in High-Speed Ceramic Modules - A method reduces coupling noise and controls impedance discontinuity in ceramic packages by: providing at least one reference mesh layer; providing a plurality of signal trace layers, with each signal layer having one or more signal lines and the reference mesh layer being adjacent to one or more of the signal layers; disposing a plurality of vias through the at least one reference mesh layer, with each via providing a voltage (Vdd) power connection or a ground (Gnd) connection; selectively placing via-connected coplanar-type shield (VCS) lines relative to the signal lines, with a first VCS line extended along a first side of a first signal line and a second VCS line extended along a second, opposing side of said first signal line. Each of the VCS lines interconnect with and extend past one or more vias located within a directional path along which the VCS lines extends. | 08-09-2012 |
20130003335 | CORELESS MULTI-LAYER CIRCUIT SUBSTRATE WITH MINIMIZED PAD CAPACITANCE - A multi layer interconnecting substrate has at least two spaced apart metal layers with a conductive pad on each one of the metal layers. Two different types of insulating layers are placed between the metal layers. The placement is such that one of the two different types of insulating layers is placed between the conductive pads and the other type of insulating layer is placed between the two spaced apart metal layers. | 01-03-2013 |
20130008696 | CORLES MULTI-LAYER CIRCUIT SUBSTRATE WITH MINIMIZED PAD CAPACITANCE - A multi layer interconnecting substrate has at least two spaced apart metal layers with a conductive pad on each one of the metal layers. Two different types of insulating layers are placed between the metal layers. The placement is such that one of the two different types of insulating layers is placed between the conductive pads and the other type of insulating layer is placed between the two spaced apart metal layers. | 01-10-2013 |
20130010445 | REDUCED WIRING REQUIREMENTS WITH SIGNAL SLOPE MANIPULATION - An information handling system device includes a plurality of electronic components; an electric circuit including at least one trace for connecting two or more of the plurality of electronic components and transmitting data between the plurality of electronic components via at least one electric signal; and a substrate including an insulating material for serving as a base for the electric circuit, wherein each of the at least one electric signal transmitted between the plurality of electronic components is transmitted utilizing slope manipulation by manipulating each of the at least one electric signal to provide a slope substantially proportional to a discrete integer data value of n discrete integer data values, n being a positive integer greater than or equal to 3, said discrete integer data value represented by using one of n distinct slopes transmitted utilizing a particular reference voltage of n predetermined reference voltages. | 01-10-2013 |
20130133937 | MESH PLANES WITH ALTERNATING SPACES FOR MULTI-LAYERED CERAMIC PACKAGES - An improved multi-layered ceramic package includes a plurality of signal planes, each having one or more signal lines; a plurality of vias, each providing one of a voltage (Vdd) power connection or a ground (Gnd) connection; and at least one reference mesh plane adjacent to one or more signal planes. The reference mesh plane includes spaced mesh lines that are separated by spaces that alternate in a narrow-wide or wide-narrow pattern. A multi-layered ceramic package using the mesh plane with alternating spaces generates significantly lower far-end (FE) noise in the ceramic package than a conventional mesh plane with constant spaces. The noise is further reduced by placing shield lines on opposite sides of signal lines in the signal plane. | 05-30-2013 |
20130252379 | METHOD FOR MAKING HIGH-SPEED CERAMIC MODULES WITH HYBRID REFERENCING SCHEME FOR IMPROVED PERFORMANCE AND REDUCED COST - A multi-layered ceramic package comprises: a signal layer with identified chip/device area(s) that require a supply of power; and a voltage power (Vdd) layer and a ground (Gnd) layer disposed on opposite sides directly above or below and adjacent to the signal layer and providing a first reference mesh plane and a second reference mesh plane configured utilizing a hybrid mesh scheme. The hybrid mesh scheme comprises: a full dense mesh in a first area directly above or below the identified chip/device area(s); a half dense mesh in a second area that is above or below the edge(s) of the chip/device area; and a wider mesh pitch in all other areas The Vdd traces are aligned to run parallel and adjacent to signal lines in those other areas. Wider traces are provided within the mesh areas that run parallel and adjacent to signal lines. | 09-26-2013 |
20140282346 | MESH PLANES WITH ALTERNATING SPACES FOR MULTI-LAYERED CERAMIC PACKAGES - An improved multi-layered ceramic package includes a plurality of signal planes, each having one or more signal lines; a plurality of vias, each providing one of a voltage (Vdd) power connection or a ground (Gnd) connection; and at least one reference mesh plane adjacent to one or more signal planes. The reference mesh plane includes spaced mesh lines that are separated by spaces that alternate in a narrow-wide or wide-narrow pattern. A multi-layered ceramic package, using the mesh plane with alternating spaces, generates significantly lower far-end (FE) noise in the ceramic package than a conventional mesh plane with constant spaces. The noise is further reduced by placing shield lines on opposite sides of signal lines in the signal plane. A method, computer system, and program code that generate the design for the multi-layered ceramic package are also disclosed. | 09-18-2014 |
20140331482 | CROSSTALK REDUCTION BETWEEN SIGNAL LAYERS IN A MULTILAYERED PACKAGE BY VARIABLE-WIDTH MESH PLANE STRUCTURES - A computer system receives an initial multilayered ceramic package design. The computer system maintains a first selection of mesh line segments of the mesh line segments at a first width and adjusts a second selection of mesh line segments of the plurality of mesh line segments to a second width. The computer system controls fabrication of the multilayered ceramic package based on the modified multilayered ceramic package design. | 11-13-2014 |
20150144252 | HIGH SPEED DIFFERENTIAL WIRING IN GLASS CERAMIC MCMS - The embodiments of the present invention relate generally to the fabrication of integrated circuits, and more particularly to a structure and method for fabricating differential wiring patterns in multilayer glass-ceramic (MLC) modules. A structure and method of forming a MLC having layers with staggered, or offset, pairs of lines formed directly on one another are disclosed. In addition, a structure and method of forming a MLC having layers with staggered, or offset, pairs of lines that periodically reverse polarity are disclosed. | 05-28-2015 |
20150144382 | HIGH SPEED DIFFERENTIAL WIRING IN GLASS CERAMIC MCMS - The embodiments of the present invention relate generally to the fabrication of integrated circuits, and more particularly to a structure and method for fabricating differential wiring patterns in multilayer glass-ceramic (MLC) modules. A structure and method of forming a MLC having layers with staggered, or offset, pairs of lines formed directly on one another are disclosed. In addition, a structure and method of forming a MLC having layers with staggered, or offset, pairs of lines that periodically reverse polarity are disclosed. | 05-28-2015 |
Patent application number | Description | Published |
20090163219 | COMBINED BASE TRANSCEIVER STATION AND BASE STATION CONTROLLER DATA CALL - A system, method, and computer readable medium for a data call setup comprises receiving an origination message by a radio call control (RCC) and by a main call control (MCC), receiving an assignment request message by the MCC and by the RCC, and receiving a traffic channel assignment message by a channel element control (CEC) and by the MCC. | 06-25-2009 |
20100087201 | COMBINED BASE TRANSCEIVER STATION AND BASE STATION CONTROLLER CALL ORIGINATION AND TERMINATION - A system, method, and computer readable medium for a mobile origination comprises receiving an origination request message by a main call control (MCC) from a radio call control (RCC), receiving an assignment request message by the RCC from the MCC, receiving a traffic channel assign message by a channel element control (CEC) and by the MCC from the RCC, receiving a call setup message by a selector distribution unit (SDU) from the MCC, and receiving a link active message by the CEC from the SDU. | 04-08-2010 |
20110028155 | COMBINED BASE TRANSCEIVER STATION AND BASE STATION CONTROLLER DATA CALL - A system, method, and computer readable medium for a data call setup comprises receiving an origination message by a radio call control (RCC) and by a main call control (MCC), receiving an assignment request message by the MCC and by the RCC, and receiving a traffic channel assignment message by a channel element control (CEC) and by the MCC. | 02-03-2011 |
20110281588 | COMBINED BASE TRANSCEIVER STATION AND BASE STATION CONTROLLER HANDOFF - A system, method, and computer readable medium for a softer handoff comprises receiving a Pilot Strength Measurement Message (PSMM) to request a handoff by a selector distribution unit (SDU), receiving a softer handoff request message by a channel element control (CEC), receiving a softer handoff request message by a radio call control (RCC), receiving a traffic channel assignment message by the CEC, and receiving an indication of an addition of a new sector for the softer handoff by the SDU. | 11-17-2011 |
20120015663 | COMBINED BASE TRANSCEIVER STATION AND BASE STATION CONTROLLER - A combined base station controller ( | 01-19-2012 |
20120196597 | COMBINED BASE TRANSCEIVER STATION AND BASE STATION CONTROLLER OPTIMIZED ASSIGNMENT OF FRAME OFFSETS - A system, method, and computer readable medium for managing an availability of a call agent, comprising acquiring a session identification by a basestation (BS) and a call agent (CA), wherein the BS is coupled to the CA, if the CA's state is changed from an active state to a standby state, requesting a new connection with the BS; and after the new connection is established between the CA and the BS, sending another session identification from the CA to the BS. | 08-02-2012 |
20120220306 | COMBINED BASE TRANSCEIVER STATION AND BASE STATION CONTROLLER - A combined base station controller ( | 08-30-2012 |
20120238282 | COMBINED BASE TRANSCEIVER STATION AND BASE STATION CONTROLLER DATA CALL - A system, method, and computer readable medium for a data call setup comprises receiving an origination message by a radio call control (RCC) and by a main call control (MCC), receiving an assignment request message by the MCC and by the RCC, and receiving a traffic channel assignment message by a channel element control (CEC) and by the MCC. | 09-20-2012 |
20130029678 | COMBINED BASE TRANSCEIVER STATION AND BASE STATION CONTROLLER - A combined base station controller ( | 01-31-2013 |
20130115960 | COMBINED BASE TRANSCEIVER STATION AND BASE STATION CONTROLLER HANDOFF - A system, method, and computer readable medium for a softer handoff comprises receiving a Pilot Strength Measurement Message (PSMM) to request a handoff by a selector distribution unit (SDU), receiving a softer handoff request message by a channel element control (CEC), receiving a softer handoff request message by a radio call control (RCC), receiving a traffic channel assignment message by the CEC, and receiving an indication of an addition of a new sector for the softer handoff by the SDU. | 05-09-2013 |
20130165128 | COMBINED BASE TRANSCEIVER STATION AND BASE STATION CONTROLLER HANDOFF - A system, method, and computer readable medium for a softer handoff comprises receiving a Pilot Strength Measurement Message (PSMM) to request a handoff by a selector distribution unit (SDU), receiving a softer handoff request message by a channel element control (CEC), receiving a softer handoff request message by a radio call control (RCC), receiving a traffic channel assignment message by the CEC, and receiving an indication of an addition of a new sector for the softer handoff by the SDU. | 06-27-2013 |
20130178207 | COMBINED BASE TRANSCEIVER STATION AND BASE STATION CONTROLLER OPTIMIZED ASSIGNMENT OF FRAME OFFSETS - A system, method, and computer readable medium for managing an availability of a call agent, comprising acquiring a session identification by a basestation (BS) and a call agent (CA), wherein the BS is coupled to the CA, if the CA's state is changed from an active state to a standby state, requesting a new connection with the BS; and after the new connection is established between the CA and the BS, sending another session identification from the CA to the BS. | 07-11-2013 |
20130252623 | COMBINED BASE TRANSCEIVER STATION AND BASE STATION CONTROLLER DATA CALL - A system, method, and computer readable medium for a data call setup comprises receiving an origination message by a radio call control (RCC) and by a main call control (MCC), receiving an assignment request message by the MCC and by the RCC, and receiving a traffic channel assignment message by a channel element control (CEC) and by the MCC. | 09-26-2013 |
20130316717 | COMBINED BASE TRANSCEIVER STATION AND BASE STATION CONTROLLER CALL ORIGINATION AND TERMINATION - A system, method, and computer readable medium for a mobile origination comprises receiving an origination request message by a main call control (MCC) from a radio call control (RCC), receiving an assignment request message by the RCC from the MCC, receiving a traffic channel assign message by a channel element control (CEC) and by the MCC from the RCC, receiving a call setup message by a selector distribution unit (SDU) from the MCC, and receiving a link active message by the CEC from the SDU. | 11-28-2013 |
20130337817 | COMBINED BASE TRANSCEIVER STATION AND BASE STATION CONTROLLER HANDOFF - A system, method, and computer readable medium for a softer handoff comprises receiving a Pilot Strength Measurement Message (PSMM) to request a handoff by a selector distribution unit (SDU), receiving a softer handoff request message by a channel element control (CEC), receiving a softer handoff request message by a radio call control (RCC), receiving a traffic channel assignment message by the CEC, and receiving an indication of an addition of a new sector for the softer handoff by the SDU. | 12-19-2013 |
20140038604 | COMBINED BASE TRANSCEIVER STATION AND BASE STATION CONTROLLER OPTIMIZED ASSIGNMENT OF FRAME OFFSETS - A system, method, and computer readable medium for managing an availability of a call agent, comprising acquiring a session identification by a basestation (BS) and a call agent (CA), wherein the BS is coupled to the CA, if the CA's state is changed from an active state to a standby state, requesting a new connection with the BS; and after the new connection is established between the CA and the BS, sending another session identification from the CA to the BS. | 02-06-2014 |
20140302861 | COMBINED BASE TRANSCEIVER STATION AND BASE STATION CONTROLLER - A combined base station controller ( | 10-09-2014 |
Patent application number | Description | Published |
20110307617 | Method And Apparatus For Handling Peers With Dynamic IP Connectivity Status In Peer-To-Peer Networks - Method and apparatus for communication in a peer-to-peer (P2P) network are provided. The method comprises a first peer in the P2P network selecting a primary Internet Protocol (IP) address from a plurality of IP addresses associated with the first peer. The method further comprises the first peer providing the primary IP address to a second peer as an address the second peer is to use in initiating communication with the first peer. The apparatus comprises a user equipment (UE) that includes a processor configured such that the UE selects a primary IP address from plurality of IP addresses associated with the UE and registers the primary IP address in the P2P network. | 12-15-2011 |
20120076121 | Releasing Connections with Local GW When UE Moves Out of Residential/Enterprise Network Coverage - A method, system and device are provided for managing LIPA and/or SIPTO connection releases when UE moves out of residential/enterprise network coverage in case service continuity is not supported for the LIPA/SIPTO PDN connection(s). To address problems caused by not providing service continuity for LIPA/SIPTO PDN connections, the PDN connection/PDP context created in the HeNB/HNB by the MME/SGSN includes context information related to the UE indicating whether such connection is a LIPA PDN connection PDN connection or not. In addition, each UE may be configured to reconnect or not reconnect to the PDN corresponding to a certain APN or service, depending on how the PDN connection was disconnected by the network. | 03-29-2012 |
20120189016 | Network Apparatus and Process to Determine the Connection Context for Connections Used for (Local) Offloading - A method, system and device are provided for managing LIPA and/or SIPTO connection releases by providing predetermined context information in either the context request message or response thereto exchanged between source and target Mobility Management Entity (MME) devices to allow the appropriate MME device to determine if LIPA service continuity is provided or not. | 07-26-2012 |
20120226802 | Controlling Network Device Behavior - A sender device is able to send packets over a network destined to a receiver device, and the sender device receives response information that is responsive to the packets. A behavior of the sender device with respect to data transmission on plural subflows of a connection is controlled based on the response information. | 09-06-2012 |
20120300750 | RESIDENTIAL/ENTERPRISE NETWORK CONNECTION MANAGEMENT AND CSFB SCENARIOS - A method, system and device are provided for managing LIPA and/or SIPTO connection releases when UE moves out of residential/enterprise network coverage in case service continuity is not supported for the LIPA/SIPTO PDN connection(s). To address problems caused by not providing service continuity for LIPA/SIPTO PDN connections, the PDN connection/PDP context created in the HeNB/HNB by the MME/SGSN includes context information related to the UE indicating whether such connection is a LIPA PDN connection PDN connection or not. In addition, each UE may be configured to reconnect or not reconnect to the PDN corresponding to a certain APN or service, depending on how the PDN connection was disconnected by the network. | 11-29-2012 |
20130329583 | METHOD AND APPARATUS FOR MULTI-RAT TRANSMISSION - A method and apparatus for mobility management, load management, sharing management and configuration update and setup in a mobile network having a first radio access technology node and a second radio access technology node, the first radio access technology node and the second radio access technology node communicating over a backhaul interface. In one aspect the method detects, at the first radio access technology node, that a handover for a user equipment to a new node is required; provides, from the first radio access technology node, handover information to the second radio access technology node over the backhaul interface; and performs the handover of the user equipment from the first radio access technology node to the new node. | 12-12-2013 |
20130329694 | METHOD AND APPARATUS FOR MULTI-RAT TRANSMISSION - A method and apparatus for mobility management, load management, sharing management and configuration update and setup in a mobile network having a first radio access technology node and a second radio access technology node, the first radio access technology node and the second radio access technology node communicating over a backhaul interface. In one aspect the method detects, at the first radio access technology node, that a handover for a user equipment to a new node is required; provides, from the first radio access technology node, handover information to the second radio access technology node over the backhaul interface; and performs the handover of the user equipment from the first radio access technology node to the new node. | 12-12-2013 |
20140242962 | COMMUNICATING DATA IN A PREDEFINED TRANSMISSION MODE - Traffic data is communicated between a wireless device and a core network control node in a predefined transmission mode in which traffic data is communicated in a control channel for carrying control messages. | 08-28-2014 |
20140293882 | DEACTIVATING OR MAINTAINING A PACKET DATA NETWORK CONNECTION - A packet data network (PDN) gateway receives a message associated with a user equipment (UE) having a PDN connection. The PDN gateway determines whether the UE is accessing a network node that has a predetermined association with the PDN gateway based on the message. In response to the determination, the PDN connection is maintained or deactivated. | 10-02-2014 |
20150079906 | Temporary Identifiers and Expiration Values for Discoverable User Equipments (UEs) - A temporary identifier is assigned to a discoverable user equipment (UE) in an assignment, an expiration value is assigned to the assignment, and the temporary identifier and the expiration value are associated to a long-term identifier of the discoverable UE. The temporary identifier and an indication of the expiration value are provided to the discoverable UE. The temporary identifier and an indication of the expiration value are provided to a discovering UE responsive to receipt of an inquiry including the long-term identifier of the discoverable UE The discoverable UE broadcasts the temporary identifier. If the broadcast is heard by the discovering UE, the discovering UE may identify that the broadcast is from the discoverable UE, based on the association of the long-term identifier to the temporary identifier. | 03-19-2015 |
20150092665 | RELEASING CONNECTIONS WITH LOCAL GW WHEN UE MOVES OUT OF RESIDENTIAL/ENTERPRISE NETWORK COVERAGE - A method, system and device are provided for managing LIPA and/or SIPTO connection releases when UE moves out of residential/enterprise network coverage in case service continuity is not supported for the LIPA/SIPTO PDN connection(s). To address problems caused by not providing service continuity for LIPA/SIPTO PDN connections, the PDN connection/PDP context created in the HeNB/HNB by the MME/SGSN includes context information related to the UE indicating whether such connection is a LIPA PDN connection PDN connection or not. In addition, each UE may be configured to reconnect or not reconnect to the PDN corresponding to a certain APN or service, depending on how the PDN connection was disconnected by the network. | 04-02-2015 |
20150249979 | METHODS AND DEVICES FOR PERFORMING PROXIMITY DISCOVERY - A method for use in a first user equipment (UE) includes receiving, from a base station, control information and a resource assignment for uplink transmission; and transmitting, based on the control information, a discovery signal on the assigned resource for uplink transmission, the discovery signal including a first temporary UE identifier (ID) assigned to the first UE, wherein the first temporary UE ID is used to identify the first UE for device-to-device communication. | 09-03-2015 |
Patent application number | Description | Published |
20120314739 | Radio Duty Cycle Minimization Techniques for Transmission-Initiated Wireless Multi-Hop Networks - The duration of receiver on-times may be minimized by sensing and reacting to communication channel power levels at intervals. When no energy is detected on the communication channel, then the receiver may be turned off for a channel sampling interval. If energy is detected on the channel, then the receiver may remain on to determine if a received message is associated with the device. Receiver on-time may also be minimized by adjusting the timing of messages used for broadcast messages sent by routing or other protocols. Broadcast messages, such as network routing topology messages, may be controlled in two phases. In a first phase, the broadcast messages are sent with at a high rate to allow nodes to join the network rapidly. In a second phase, the broadcast messages are sent with at a lower rate to minimize interference with data and other messages in the network. | 12-13-2012 |
20130179715 | SYSTEMS AND METHODS FOR REDUCING ENERGY CONSUMPTION IN SENSOR NETWORKS - A system includes a volatile memory and state information management logic. The volatile memory includes a plurality of volatile storage locations. The state information management logic includes memory write tracking circuitry coupled to the volatile memory. The memory write tracking circuitry is configured to identify locations of the memory written subsequent to restoration of state information to the volatile memory on exit of a low-power mode of operation, and to store indicia of the identified locations. | 07-11-2013 |
20130188670 | DYNAMIC IMPROVEMENT OF LINK SYMMETRY IN CO-LOCATED PLC AND RF NETWORKS - An electronic communication device comprises a first transceiver capable of a bi-directional communication session on a first communication medium; a second transceiver capable of a bi-directional communication session on a second communication medium; and a control logic coupled to the first transceiver and the second transceiver, wherein the control logic is configured to receive, from the first transceiver, a first signal, and cause, in response to the first signal, data transmitted by the first transceiver on the first communication medium as part of a communication session to be transmitted instead by the second transceiver on the second communication medium while the first transceiver continues to receive data as part of the communication session. | 07-25-2013 |
20130188673 | DYNAMIC MEDIUM SWITCH IN CO-LOCATED PLC AND RF NETWORKS - An electronic communication device comprises a first transceiver capable of a bi-directional communication session on a first communication medium; a second transceiver capable of a bi-directional communication session on a second communication medium; and a control logic coupled to the first transceiver and the second transceiver and capable of implementing a convergence layer, wherein the control logic is configured to receive, from the first transceiver, a first signal; and cause, in response to the first signal, data received and transmitted by the first transceiver on the first communication medium as part of a communication session to be received and transmitted instead by the second transceiver on the second communication medium. | 07-25-2013 |
20130198540 | Dynamic Power Management in Real Time Systems - Dynamically reducing power consumption by a processor in a computer system by determining a maximum number of times (token count) that the processor can incur a start-up delay after being placed into a low-power mode during a token period of time when executing a task for a token period of time. The processor may be placed into the low-power mode while executing the task in response to an idle indicator only if a current value of the token count assigned to the task is greater than zero. The current value of the token count is decremented each time the processor incurs a start-up delay in response to being awakened from the low-power mode. The current token count is reset to match the assigned token count at the end of each token period. Furthermore, wakeup may be anticipated to allow the processor to be awakened preemptively. | 08-01-2013 |
20130217399 | PARTIAL CHANNEL MAPPING FOR FAST CONNECTION SETUP IN LOW ENERGY WIRELESS NETWORKS - A system comprising a controller, a scanner, and a transceiver. The controller is configured to identify a number of channels in which a beacon signal may be wirelessly transmitted. The number of channels is less than a total number of channels available for receiving transmissions. The scanner is configured to scan each of the number of channels for a first beacon signal. The transceiver is configured to receive the first beacon signal from one of the number of channels. | 08-22-2013 |
20130250928 | SCHEDULING IN A MULTI-HOP WIRELESS NETWORK - Various techniques are disclosed for assigning timeslots in a multihop wireless network. One such method includes, for each node for uplink timeslot assignments, assigning a higher hop count node to a timeslot that is to occur before all time slots assigned to lower hop count nodes. The method further includes, for each node for downlink timeslot assignments, assigning a lower hop count node to a timeslot that is to occur before all time slots assigned to higher hop count nodes. | 09-26-2013 |
20130259016 | COEXISTENCE OF WIRELESS SENSOR NETWORKS WITH OTHER WIRELESS NETWORKS - A wireless device includes a wireless transceiver configured to transmit to and receive from nodes in a wireless sensor network (WSN) and control logic coupled to the first wireless transceiver. The wireless transceiver transmits a wireless packet to a node in the WSN based on the transmission coinciding with a break in transmissions for a second wireless network. Based on the wireless transceiver being configured to transmit the wireless packets utilizing time synchronized channel hopping, slot frames for packet transmissions in the WSN are time offset so as not to coincide with transmissions made on the second wireless network. Based on the wireless transceiver being configured to transmit the packets utilizing coordinated sampled listening, wake up sequence transmissions for the WSN are time offset so as not to coincide with the transmissions made on the second wireless network. | 10-03-2013 |
20130301453 | WIRELESS NETWORK WITH POWER AWARE TRANSMISSION CONTROL - A wireless device that tailors communications based on power parameters of the device. In one embodiment, a wireless device includes an energy source, a power monitor coupled to the energy source, a wireless transceiver, and a traffic controller coupled to the power monitor and the wireless transceiver. The power monitor is configured to measure a parameter of the energy source. The wireless transceiver is configured to wirelessly communicate via a wireless network. The traffic controller is configured to set length of packets to be transmitted based on the measured parameter of the energy source. | 11-14-2013 |
20130326523 | Resource Sharing Aware Task Partitioning for Multiprocessors - A multi processor task allocation method is described that considers task dependencies while performing task allocation in order to avoid blocking of a task's execution while waiting for the resolution of the dependency. While allocating the tasks to the processors the potential blocking time is considered, and the best allocation that will have the least amount of blocking time is found. | 12-05-2013 |
20160028438 | Dynamic Medium Switch in Co-Located PLC and RF Networks - A method for implementing a convergence layer. Data is received on a first communication medium by a first transceiver. Data is transmitted on the first communication medium by the first transceiver. A signal is received. Causing, through the convergence layer, by a control logic in response to the signal, the data received and transmitted on the first communication medium as part of a communication session to be received and transmitted instead by a second transceiver on a second communication medium, wherein the convergence layer is configured to conceal from a routing layer at least one of: information related to the first signal, and information related to the data being received and transmitted on the second communication medium. | 01-28-2016 |
20160044697 | Coexistence of Wireless Sensor Networks with Other Wireless Networks - A method for communicating in a wireless sensor network (WSN) is described. Using control logic, a first wireless transceiver is caused to transmit a wireless packet to a node in a wireless sensor network. The control logic bases its causing on a transmission coinciding with a break in transmission for a second wireless network, such that the transmission from the first wireless transceiver does not coincide with transmissions made on the second wireless network. Time synchronized channel hopping (TSCH) slot frames for wireless packet transmission in the wireless sensor network are caused to be time offset if the first wireless transceiver is utilizing TSCH. Wake up sequence transmissions for the wireless sensor network are caused to be time offset if the first wireless transceiver is utilizing coordinated sampled listening (CSL). | 02-11-2016 |
20160050046 | Wireless Network with Power Aware Transmission Control - A wireless device that tailors communications based on power parameters of the device. In one embodiment, a wireless device includes an energy source, a power monitor coupled to the energy source, a wireless transceiver, and a traffic controller coupled to the power monitor and the wireless transceiver. The power monitor is configured to measure a parameter of the energy source. The wireless transceiver is configured to wirelessly communicate via a wireless network. The traffic controller is configured to dynamically provide traffic management based on a prediction of wireless device capabilities using the present state of the energy source. | 02-18-2016 |
Patent application number | Description | Published |
20130161639 | DRAIN INDUCED BARRIER LOWERING WITH ANTI-PUNCH-THROUGH IMPLANT - An integrated circuit containing an MOS transistor with epitaxial source and drain regions may be formed by implanting a retrograde anti-punch-through layer prior to etching the source drain regions for epitaxial replacement. The anti-punch-through layer is disposed between stressor tips of the epitaxial source and drain regions, and does not substantially extend into the epitaxial source and drain regions. | 06-27-2013 |
20130249011 | INTEGRATED CIRCUIT (IC) HAVING TSVS AND STRESS COMPENSATING LAYER - A through-substrate via (TSV) unit cell includes a substrate having a topside semiconductor surface and a bottomside surface, and a TSV which extends the full thickness of the substrate including an electrically conductive filler material surrounded by a dielectric liner that forms an outer edge for the TSV. A circumscribing region of topside semiconductor surface surrounds the outer edge of the TSV. Dielectric isolation is outside the circumscribing region. A tensile contact etch stop layer (t-CESL) is on the dielectric isolation, and on the circumscribing region. | 09-26-2013 |
20150054084 | SILICIDE FORMATION DUE TO IMPROVED SiGe FACETING - An integrated circuit includes a PMOS gate structure and a gate structure on adjacent field oxide. An epitaxy hard mask is formed over the gate structure on the field oxide so that the epitaxy hard mask overlaps the semiconductor material in PMOS source/drain region. SiGe semiconductor material is epitaxially formed in the source/drain regions, so that that a top edge of the SiGe semiconductor material at the field oxide does not extend more than one third of a depth of the SiGe in the source/drain region abutting the field oxide. Dielectric spacers on lateral surfaces of the gate structure on the field oxide extend onto the SiGe; at least one third of the SiGe is exposed. Metal silicide covers at least one third of a top surface of the SiGe. A contact has at least half of a bottom of the contact directly contacts the metal silicide on the SiGe. | 02-26-2015 |
20150287717 | INTEGRATION OF ANALOG TRANSISTOR - An integrated circuit has two parallel digital transistors and a perpendicular analog transistor. The digital transistor gate lengths are within 10 percent of each other and the analog gate length is at least twice the digital transistor gate length. The first digital transistor and the analog transistor are implanted by a first LDD implant which includes a two sub-implant angled halo implant process with twist angles perpendicular to the first digital transistor gate edge and parallel to the analog transistor gate edge. The second digital transistor and the analog transistor are implanted by a second LDD implant which includes a two sub-implant angled halo implant process with twist angles perpendicular to the second digital transistor gate edge and parallel to the analog transistor gate edge. The first halo dose is at least 20 percent more than the second halo dose. | 10-08-2015 |
20150287801 | SILICIDE FORMATION DUE TO IMPROVED SIGE FACETING - An integrated circuit includes a PMOS gate structure and a gate structure on adjacent field oxide. An epitaxy hard mask is formed over the gate structure on the field oxide so that the epitaxy hard mask overlaps the semiconductor material in PMOS source/drain region. SiGe semiconductor material is epitaxially formed in the source/drain regions, so that that a top edge of the SiGe semiconductor material at the field oxide does not extend more than one third of a depth of the SiGe in the source/drain region abutting the field oxide. Dielectric spacers on lateral surfaces of the gate structure on the field oxide extend onto the SiGe; at least one third of the SiGe is exposed. Metal silicide covers at least one third of a top surface of the SiGe. A contact has at least half of a bottom of the contact directly contacts the metal silicide on the SiGe. | 10-08-2015 |
20160027888 | SILICIDE FORMATION DUE TO IMPROVED SiGe FACETING - An integrated circuit includes a PMOS gate structure and a gate structure on adjacent field oxide. An epitaxy hard mask is formed over the gate structure on the field oxide so that the epitaxy hard mask overlaps the semiconductor material in PMOS source/drain region. SiGe semiconductor material is epitaxially formed in the source/drain regions, so that that a top edge of the SiGe semiconductor material at the field oxide does not extend more than one third of a depth of the SiGe in the source/drain region abutting the field oxide. Dielectric spacers on lateral surfaces of the gate structure on the field oxide extend onto the SiGe; at least one third of the SiGe is exposed. Metal silicide covers at least one third of a top surface of the SiGe. A contact has at least half of a bottom of the contact directly contacts the metal silicide on the SiGe. | 01-28-2016 |
20160043076 | INTEGRATION OF ANALOG TRANSISTOR - An integrated circuit has two parallel digital transistors and a perpendicular analog transistor. The digital transistor gate lengths are within 10 percent of each other and the analog gate length is at least twice the digital transistor gate length. The first digital transistor and the analog transistor are implanted by a first LDD implant which includes a two sub-implant angled halo implant process with twist angles perpendicular to the first digital transistor gate edge and parallel to the analog transistor gate edge. The second digital transistor and the analog transistor are implanted by a second LDD implant which includes a two sub-implant angled halo implant process with twist angles perpendicular to the second digital transistor gate edge and parallel to the analog transistor gate edge. The first halo dose is at least 20 percent more than the second halo dose. | 02-11-2016 |
Patent application number | Description | Published |
20120074973 | ON-DIE PARAMETRIC TEST MODULES FOR IN-LINE MONITORING OF CONTEXT DEPENDENT EFFECTS - An integrated circuit (IC) die has an on-die parametric test module. A semiconductor substrate has die area, and a functional IC formed on an IC portion of the die area including a plurality of circuit elements configured for performing a circuit function. The on-die parametric test module is formed on the semiconductor substrate in a portion of the die area different from the IC portion. The on-die parametric test module includes a reference layout that provides at least one active reference MOS transistor, wherein the active reference MOS transistor has a reference spacing value for each of a plurality of context dependent effect parameters. A plurality of different variant layouts are included on the on-die parametric test module. Each variant layout provides at least one active variant MOS transistor that provides a variation with respect to the reference spacing value for at least one of the context dependent effect parameters. | 03-29-2012 |
20120074980 | SCRIBE LINE TEST MODULES FOR IN-LINE MONITORING OF CONTEXT DEPENDENT EFFECTS FOR ICs INCLUDING MOS DEVICES - An apparatus includes a plurality of die areas having integrated circuit (IC) die each having circuit elements for performing a circuit function, and scribe line areas between the die areas. At least one test module is formed in the scribe line areas. The test module includes a reference layout that includes at least one active reference MOS transistor that has a reference spacing value for each of a plurality of context dependent effect parameters, and a plurality of variant layouts. Each variant layout provides at least one active variant MOS transistor that provides a variation with respect to the reference spacing values for at least one of the plurality of context dependent effect parameters. | 03-29-2012 |
20120119301 | METHOD FOR IMPROVING DEVICE PERFORMANCE USING DUAL STRESS LINER BOUNDARY - An integrated circuit with DSL borders perpendicular to the tranistor gates primarily inside the nwell and with DSL borders parallel to the transistor gates primarily outside the nwell. A method for forming an integrated circuit with DSL borders perpendicular to the tranistor gates primarily inside the nwell and with DSL borders parallel to the transistor gates primarily outside the nwell. | 05-17-2012 |
20130200466 | INTEGRATED CIRCUIT HAVING SILICIDE BLOCK RESISTOR - A method for forming an integrated circuit (IC) including a silicide block poly resistor (SIBLK poly resistor) includes forming a dielectric isolation region in a top semiconductor surface of a substrate. A polysilicon layer is formed including patterned resistor polysilicon on the dielectric isolation region and gate polysilicon on the top semiconductor surface. Implanting is performed using a first shared metal-oxide-semiconductor (MOS)/resistor polysilicon implant level for simultaneously implanting the patterned resistor polysilicon and gate polysilicon of a MOS transistor with at least a first dopant. Implanting is then performed using a second shared MOS/resistor polysilicon implant level for simultaneously implanting the patterned resistor polysilicon, gate polysilicon and source and drain regions of the MOS transistor with at least a second dopant. A metal silicide is formed on a first and second portion of a top surface of the patterned resistor polysilicon to form the SIBLK poly resistor. | 08-08-2013 |
20140054710 | Reduction of Proximity Effects in Field-Effect Transistors with Embedded Silicon-Germanium Source and Drain Regions - An integrated circuit and method of fabricating the same utilizing embedded silicon-germanium (SiGe) source/drain regions, and in which the proximity effect of nearby shallow trench isolation structures is reduced. Embedded SiGe source/drain structures are formed by selective epitaxy into recesses etched into the semiconductor surface, on either side of each gate electrode. The SiGe structures overfill the recesses by at least about 30% of the depth of the recesses, as measured from the interface between the channel region and the overlying gate dielectric at the edge of the gate electrode. This overfill has been observed to reduce proximity effects of nearby shallow trench isolation structures on nearby transistors. Additional reduction in the proximity effect can be obtained by ensuring sufficient spacing between the edge of the gate electrode and a parallel edge of the nearest shallow trench isolation structure. | 02-27-2014 |
20140374836 | METHOD FOR IMPROVING DEVICE PERFORMANCE USING DUAL STRESS LINER BOUNDARY - An integrated circuit with DSL borders perpendicular to the tranistor gates primarily inside the nwell and with DSL borders parallel to the transistor gates primarily outside the nwell. A method for forming an integrated circuit with DSL borders perpendicular to the tranistor gates primarily inside the nwell and with DSL borders parallel to the transistor gates primarily outside the nwell. | 12-25-2014 |