Patent application number | Description | Published |
20110273412 | ARRAY SUBSTRATE FOR IN-PLANE SWITCHING MODE LIQUID CRYSTAL DISPLAY DEVICE - An array substrate for a liquid crystal display device includes: a substrate; a gate line and a data line on the substrate; a common line parallel to and spaced apart from the gate line; a thin film transistor connected to the gate line and the data line; a plurality of pixel electrodes in the pixel region; a plurality of common electrodes alternating with the plurality of pixel electrodes; at least one outermost common electrode at an edge portion of the pixel region; a black matrix corresponding to the thin film transistor, the gate line and the data line, the black matrix including an inorganic material and having an open portion; and a color filter layer in the open portion. | 11-10-2011 |
20110273651 | LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - A liquid crystal display device includes an array substrate including: gate and data lines crossing each other on a first substrate to define a pixel region; a common line in parallel with the gate line; first and second common line patterns extending from the common line, wherein the data line is between the first and second common line patterns; a thin film transistor connected to the gate and data lines; a pixel electrode connected to the thin film transistor and in the pixel region; and an inorganic black matrix below the gate line, the common line, and the first and second common lines, wherein the inorganic black matrix below the first and second common lines shields the data line; an opposing substrate including a common electrode on a second substrate; and a liquid crystal layer between the array substrate and the opposing substrate. | 11-10-2011 |
20140120643 | LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - A liquid crystal display device includes an array substrate including: gate and data lines crossing each other on a first substrate to define a pixel region; a common line in parallel with the gate line; first and second common line patterns extending from the common line, wherein the data line is between the first and second common line patterns; a thin film transistor connected to the gate and data lines; a pixel electrode connected to the thin film transistor and in the pixel region; and an inorganic black matrix below the gate line, the common line, and the first and second common lines, wherein the inorganic black matrix below the first and second common lines shields the data line; an opposing substrate including a common electrode on a second substrate; and a liquid crystal layer between the array substrate and the opposing substrate. | 05-01-2014 |
20140145157 | ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME - An organic light emitting diode display device includes a substrate including a display region, wherein a plurality of pixel regions are defined in the display region; a first electrode over the substrate and in each of the plurality of pixel regions; a first bank on edges of the first electrode and having a first width and a first thickness; a second bank on the first bank and having a second width smaller than the first width; an organic emitting layer on the first electrode and a portion of the first bank; and a second electrode on the organic emitting layer and covering an entire surface of the display region. | 05-29-2014 |
20140145158 | ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME - An organic light emitting diode display device includes a substrate including a display region, wherein a plurality of pixel regions are defined in the display region; a first electrode over the substrate and in each of the plurality of pixel regions; a bank including a lower layer and an upper layer on the first electrode, the lower layer disposed on edges of the first electrode and having a first width and a first thickness, the upper layer disposed on the lower layer and having a second width smaller than the first width; an organic emitting layer on the first electrode and a portion of the lower layer; and a second electrode on the organic emitting layer and covering an entire surface of the display region. | 05-29-2014 |
20140147950 | METHOD OF FABRICATING ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE - A method of fabricating an organic light emitting diode display device includes forming a first electrode over a substrate including a display region, which includes a plurality of pixel regions, the first electrode formed in each of the plurality of pixel regions; forming a first bank and a second bank, the first bank formed on edges of the first electrode and having a first width and a first thickness, and the second bank formed on the first bank and having a second width smaller than the first width; forming an organic emitting layer on the first electrode and a portion of the first bank; and forming a second electrode on the organic emitting layer and covering an entire of the display region. | 05-29-2014 |
20150249117 | ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME - An organic light emitting diode display device includes a substrate including a display region, wherein a plurality of pixel regions are defined in the display region; a first electrode over the substrate and in each of the plurality of pixel regions; a bank including a lower layer and an upper layer on the first electrode, the lower layer disposed on edges of the first electrode and having a first width and a first thickness, the upper layer disposed on the lower layer and having a second width smaller than the first width; an organic emitting layer on the first electrode and a portion of the lower layer; and a second electrode on the organic emitting layer and covering an entire surface of the display region. | 09-03-2015 |
20150333110 | ORGANIC ELECTROLUMINESCENT DEVICE AND METHOD FOR FABRICATING THE SAME - Disclosed an organic electroluminescent device and a method for fabricating the same. The device may include a thin film transistor disposed on a substrate; a first electrode formed for each pixel on the thin film transistor; a first pixel define layer formed to cover an edge portion of the first electrode; a second pixel define layer formed on the first pixel define layer; an organic layer formed on the first electrode; and a second electrode formed on the organic layer. | 11-19-2015 |
20160079323 | ORGANIC LIGHT EMITTING DISPLAY DEVICE - An OLED device is disclosed. The device includes a substrate defined to have a first active area and a dummy area. First electrodes are formed on the substrate, and a first bank pattern is formed to overlap with edges of each first electrode and to expose a part of an upper surface of each first electrode. A second bank pattern is formed on the first bank pattern within the first active area, and a third bank pattern is formed on the first bank pattern within the dummy area in the same layer as the second bank pattern. The second bank pattern is formed to have a larger width than that of the third bank pattern. As such, an organic emission layer can be evenly formed in the active area. | 03-17-2016 |
20160087016 | ORGANIC LIGHT EMITTING DISPLAY DEVICE - An organic light emitting display (OLED) device is disclosed. The OLED device includes a substrate configured to include a sub-pixel defined into an emission region and a driving region. A first bank pattern configured to define the emission region of the sub-pixel is formed on the substrate. A second bank pattern configured to include an opening, which exposes the emission region and a part of the driving region, is formed on a part of an upper surface of the first bank pattern. An organic emission layer is formed in the opening. As such, the occupied area of the organic emission layer becomes wider. Therefore, the thickness deviation of the organic emission layer is prevented or minimized. | 03-24-2016 |
Patent application number | Description | Published |
20130293593 | Stereoscopic image display device and method for driving the same - A stereoscopic image display device according to an exemplary embodiment of the present invention comprises: a display panel comprising data lines, gate lines, and a plurality of pixels; a data modulation unit that outputs modulated 3D image data by modulating kth pixel data of a jth line based on the kth pixel data of the jth line and kth pixel data of a line adjacent to the jth line; a data driving circuit that converts the modulated 3D image data into analog data voltages and outputs the analog data voltages to the data lines; and a gate driving circuit that sequentially outputs gate pulses to the gate lines. | 11-07-2013 |
20140071120 | MEMORY REDUCTION DEVICE OF STEREOSCOPIC IMAGE DISPLAY FOR COMPENSATING CROSSTALK - A memory reduction device of a stereoscopic image display includes a compression unit configured to receive first to fourth input data belonging to Gn and comprised of K1 bit, respectively, align the first to fourth input data in order of a data size to generate first to fourth alignment data, generate first to fourth compression data groups including first and second compression data having K2 bits smaller than K1 bits and third compression data having K3 bits smaller than K2 bits based on the first to fourth alignment data, derive an outlier from the first to fourth input data by using a deviation between the first to fourth alignment data, select any one of the first to fourth compression data groups, as the compressed Gn−1 according to the presence or absence of the outlier and an outlier derivation position. | 03-13-2014 |
20140176671 | APPARATUS FOR DISPLAYING A HOLOGRAM - An apparatus for displaying a hologram comprises: a hologram display panel that represents light having the hologram images to an observer; a detecting camera that decides a position of the observer; a deflector that forms a prism pattern to refract the light corresponding to the detected position of the observer; and a deflector driver that supplies a driving voltage corresponding to a inclined angle for forming the prism pattern, wherein the deflector includes: a plurality of first electrodes running to a first direction and divided into a plurality of electrode groups; a plurality of connection electrodes running to a second direction crossing with the first direction, and connecting same numbered first electrodes of the electrode groups, wherein each end of the connection electrodes forms a pad portion; and a second electrode facing to the plurality of the first electrodes with a liquid crystal cell therebetween. | 06-26-2014 |
20140300839 | HOLOGRAPHY 3D DISPLAY - The present disclosure relates to a holography three dimensional display in which no 3D cross-talk problem is arisen. The present disclosure suggests an apparatus for displaying hologram images comprising: a display panel displaying a hologram image; a back light unit disposed at one side of the display panel for supplying a back light; a first light path deflecting cell disposed at another side of the display panel facing away from the back light unit for forming a first prism pattern along a first direction rotating by a predetermined angle from a horizontal axis of the display panel; and a second light path deflecting cell disposed in front of the first light path deflecting cell for forming a second prism pattern along a second direction perpendicular to the first direction. | 10-09-2014 |
Patent application number | Description | Published |
20150062101 | DISPLAY DEVICE HAVING TOUCH SCREEN - A display device comprises: a pixel array substrate comprising first pads; a touch screen substrate comprising second pads; an adhesive film that attaches the pixel array substrate and the touch screen substrate; and a conductive sealant that electrically connects the first pads and the second pads between the pixel array substrate and the touch screen substrate. The adhesive film comprises: an opening with the conductive sealant applied thereto; and an extension portion that surrounds the opening. | 03-05-2015 |
20150318447 | Display Apparatus and Method of Manufacturing the Same - Provided are a display apparatus and a method of manufacturing the display apparatus. A color filter layer including at least a red color filter, a green color filter, and a blue color filter is disposed on a first substrate. A black matrix is disposed on the color filter layer. A color filter overlapped unit where the red, green and blue color filters are overlapped is disposed in a black matrix area corresponding to the black matrix. The color filter overlapped unit has a lower reflectivity with respect to an external light than the other color filters. The color filter overlapped unit is formed in the black matrix area, and the color filter overlapped unit is formed by overlapping the blue, red and green color filters in order, and, thus, can prevent mixing of colors and reduce reflection with respect to an external light. | 11-05-2015 |
20160035803 | ORGANIC LIGHT EMITTING DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME - An organic light emitting display device according to an embodiment includes a lower substrate; a bank layer disposed on the lower substrate; a connection assistance unit disposed on the bank layer; a cathode disposed on the lower substrate so as to cover the bank layer; an auxiliary electrode disposed on the bank layer and electrically connected with the cathode; and an upper substrate provided to face the lower substrate. | 02-04-2016 |
Patent application number | Description | Published |
20130240916 | LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME - Discussed are a liquid crystal display device and a method of fabricating the same in which a single common line is formed at the center of a substrate, which results in an enhanced aperture ratio and transmittance. The liquid crystal display device includes a single common line located at a center of a substrate; a first group of unit pixels located in a right portion of the substrate on the basis of the common line and a second group of unit pixels located in a left portion of the substrate on the basis of the common line, each unit pixel defined by a plurality of gate lines and data lines orthogonally intersecting each other; and a plurality of thin film transistors formed at a right side of the respective unit pixels of the first group and at a left side of the respective unit pixels of the second group. | 09-19-2013 |
20140132875 | ARRAY SUBSTRATE FOR FRINGE FIELD SWITCHING MODE LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME - An array substrate for a liquid crystal display (LCD) device includes a common line and gate lines. The array substrate includes a first, second, and third passivation layer and thin film transistors (TFTs). The second passivation layer includes first and second holes respectively corresponding to a drain electrode and the common line. A common electrode on the second passivation layer includes a first opening corresponding to the TFTs and a second opening in the second hole. A drain contact hole through the third and first passivation layers exposes the drain electrode. A first common contact hole through the third passivation layer exposes the common electrode in the second hole. A second common contact hole through the third and first passivation layers exposes the common line, and a pixel electrode includes a third opening and a connection pattern connecting the common electrode to the common line on the third passivation layer. | 05-15-2014 |
20150070610 | LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME - Discussed are a liquid crystal display device and a method of fabricating the same in which a single common line is formed at the center of a substrate, which results in an enhanced aperture ratio and transmittance. The liquid crystal display device includes a single common line located at a center of a substrate; a first group of unit pixels located in a right portion of the substrate on the basis of the common line and a second group of unit pixels located in a left portion of the substrate on the basis of the common line, each unit pixel defined by a plurality of gate lines and data lines orthogonally intersecting each other; and a plurality of thin film transistors formed at a right side of the respective unit pixels of the first group and at a left side of the respective unit pixels of the second group. | 03-12-2015 |
Patent application number | Description | Published |
20100149086 | LIQUID CRYSTAL DISPLAY DEVICE - An LCD device of an edge type is disclosed. The LCD device analyzes brightness of an input image in blocks using an algorithm and generates lamp drive signals corresponding to the analyzed block brightnesses. Also, the LCD device applied the lamp drive signals to a plurality of light sources. As such, the LCD device with the edge type backlight unit can be divisionally driven in blocks. | 06-17-2010 |
20110013110 | Backlight unit and liquid crystal display device having the same - A backlight unit that includes a plurality of light source packages configured to each include a metal printed-circuit-board (PCB) and light emitting diodes; a plurality of light guide plates disposed parallel to the light source packages, respectively; at least one fixation member formed on an incident surface of each light guide plate corresponding to one side surface of each light guide plate; and a bottom cover configured to include a plurality of fixation holes which are formed to receive and secure the respective fixation members. | 01-20-2011 |
20110141158 | BACK LIGHT UNIT AND METHOD FOR ASSEMBLING THE SAME - A back light unit is disclosed, of which thinness is easily provided. The back light unit comprises at least one light source substrate having one surface provided with at least one light source and the other surface provided with a connector to which a driving power source for driving the light source is input; a bottom cover receiving the light source substrate therein, wherein the bottom cover includes at least one opening, so that the connector is projected to the outside of the bottom cover, the opening passing through a rear surface of the bottom cover. | 06-16-2011 |
Patent application number | Description | Published |
20140152629 | SHIFT REGISTER AND FLAT PANEL DISPLAY DEVICE INCLUDING THE SAME - Disclosed are a shift register and a flat panel display device. The shift register includes a plurality of stages that supply a gate-on voltage pulse to a plurality of gate lines formed in a display panel. Each of the stages includes a pull-up transistor configured to supply one of a plurality of clock signals to an output node according to a voltage of a first node, a pull-down transistor configured to supply a gate-off voltage to the output node according to a voltage of a second node, a node controller configured to control the voltages of the first and second nodes on the basis of a gate start signal, and a switching unit connected to at least two gate lines adjacent to the output node, and configured to sequentially supply gate-on voltage pulses having different pulse widths to the at least two adjacent gate lines using the clock signal. | 06-05-2014 |
20150364078 | SCAN DRIVER AND DISPLAY DEVICE USING THE SAME - A scan driver and display device using the same are disclosed. The display device includes display panel, a data driver configured to supply a data signal to the display panel, and a scan driver formed in a non-display area of the display panel, including a shift register composed of a plurality of stages and a level shifter formed outside the display panel, and configured to supply a scan signal to the display panel using the shift register and the level shifter. The scan driver comprises: a sensor circuit unit configured to sense internal and external environmental conditions and generate a compensation circuit control signal on the basis of a sensed result; and a compensation circuit unit generating a compensation signal to compensate outputs of the plurality of stages in response to the compensation circuit control signal. | 12-17-2015 |
20160042691 | DISPLAY DEVICE - A display device includes a display panel and a scan driver including transistors formed in a non-display area of the display panel. A compensation voltage is supplied to the scan driver through a compensation gate electrode included in at least one transistor of the scan driver. Namely, the at least one transistor includes a gate electrode, to which a signal or a voltage for activating a channel is supplied, and the compensation gate electrode, to which the compensation voltage for recovering a threshold voltage is supplied. | 02-11-2016 |
Patent application number | Description | Published |
20140092082 | LIQUID CRYSTAL DISPLAY DEVICE - An LCD device according to an embodiment includes a liquid crystal display panel in which n gate lines are formed; a timing controller to generate first to sixth clock signals; a first gate driver to apply a high gate voltage to one ends of the (2k−1)th gate lines in response to the first, third and fifth clock signals; a second gate driver to apply the high gate voltage to one ends of the (2k)th gate lines in response to the second, fourth and sixth clock signals; left discharge circuits each to apply a low gate voltage to the other end of the (2k−1)th gate line according to a voltage level on (2k+1)th gate line; and right discharge circuits each to apply the low gate voltage to the other end of the (2k)th gate line according to the voltage level on (2k+2)th gate line. | 04-03-2014 |
20140118327 | LIQUID CRYSTAL DISPLAY PANEL - An LCD panel being driven in an overlapping drive mode by applying a gate high voltage during n horizontal synchronous intervals is disclosed. The LCD panel includes: a plurality of gate lines; and a gate driver configured to include a plurality of stages connected to the plurality of gate lines. The plurality of stages are grouped in a plurality of stage groups each including n stages. Odd-numbered stage groups each allows the n stages to be arranged in a Z shape with having a display area therebetween. Even-number stage groups each allows the n states to be arranged in an inverse-Z shape with having the display area therebetween. | 05-01-2014 |
20140354523 | Shift Register - Disclosed is a shift register including stages for sequentially outputting output pulses including carry and scan pulses. Odd-numbered stages supply corresponding scan pulses to odd-numbered gate lines in a sequential manner, and even-numbered stages supply corresponding scan pulses to even-numbered gate lines in a sequential manner. Each stage includes a carry output unit for generating a carry pulse, based on a first discharge voltage and a clock pulse having a low-level voltage equal to the first discharge voltage, and supplying the carry pulse to at least one of upstream and downstream stages, and a scan output unit for generating a scan pulse, based on a second discharge voltage having a higher voltage than the first discharge voltage and the clock pulse, and supplying the scan pulse to a corresponding gate line. | 12-04-2014 |
20150340003 | LIQUID CRYSTAL DISPLAY DEVICE FOR IMPROVING THE CHARACTERISTICS OF GATE DRIVE VOLTAGE - An LCD device can include a liquid crystal display panel having a plurality of gate lines; a controller configured to generate at least four clock signals with different phases; a first gate driver configured to apply a high gate voltage to odd-numbered gate lines in response to at least two of the clock signals; a second gate driver configured to apply the high gate voltage to even-numbered gate lines in response to other clock signals; primary discharge circuits each configured to apply a low gate voltage to the respective odd-numbered gate line in response to a carry signal opposite to a voltage level on one of posterior odd-and-even-numbered gate lines; and secondary discharge circuits each configured to apply the low gate voltage to the respective even-numbered gate line in response to the carry signal opposite to the voltage level on the other one of the posterior odd-and-even-numbered gate lines. | 11-26-2015 |
Patent application number | Description | Published |
20080197468 | Package structure and manufacturing method thereof - A package structure and a manufacturing method thereof are provided. The package structure includes a substrate, a first chip, a cap structure, a second chip and a sealant. The first chip is disposed in an opening of the substrate and is electrically connected to the substrate. The cap structure is disposed on the substrate corresponding to the first chip. The second chip is disposed on the cap structure and is electrically connected to the substrate. The sealant encapsulates the first chip, the cap structure and the second chip. | 08-21-2008 |
20080237820 | Package structure and method of manufacturing the same - A package structure including a substrate, a shielding element, a chip, a sealant layer and a semiconductor device is provided. The substrate has a first surface and a second surface opposite to the first surface. The shielding element is disposed on the first surface. The chip is disposed on the shielding element and is electrically connected to the substrate. The sealant layer is disposed on the first surface, and encapsulates the chip and the shielding element. The semiconductor device is disposed on the second surface. | 10-02-2008 |
20080237821 | Package structure and manufacturing method thereof - A package structure and a manufacturing method thereof are provided. The package structure includes a substrate, a shielding plate, a first chip, a first sealant, a second chip and a second sealant. The substrate has a lower surface and an upper surface on which the shielding plate is disposed. The first chip disposed on the shielding plate is electrically connected to the substrate. The first sealant disposed on the upper surface encapsulates the shielding plate and the first chip. The second chip disposed on the lower surface is electrically connected to the substrate. The second sealant disposed on the lower surface encapsulates the second chip. | 10-02-2008 |
Patent application number | Description | Published |
20120269316 | SHIFT REGISTER - A shift register is provided in which leakage of charges from a voltage at a set node is prevented to stabilize an output from a stage. The shift register includes stages for sequentially outputting scan pulses. An nth one of the stages includes a node controller for controlling voltages at nodes, and an output unit for outputting any one of a corresponding one of the scan pulses and a first discharging voltage according to the voltages at the nodes. The nodes include set and reset nodes. The node controller of the nth stage includes a first switching device controlled by a voltage supplied to the reset node for supplying a second discharging voltage to the set node, and an inverter circuit controlled by a voltage supplied to the set node for supplying any one of a charging voltage and a third discharging voltage to the reset node. | 10-25-2012 |
20130243150 | SHIFT REGISTER - A shift register is provided in which leakage of charges from a voltage at a set node is prevented to stabilize an output from a stage. The shift register includes stages for sequentially outputting scan pulses. An nth one of the stages includes a node controller for controlling voltages at nodes, and an output unit for outputting any one of a corresponding one of the scan pulses and a first discharging voltage according to the voltages at the nodes. The nodes include set and reset nodes. The node controller of the nth stage includes a first switching device controlled by a voltage supplied to the reset node for supplying a second discharging voltage to the set node, and an inverter circuit controlled by a voltage supplied to the set node for supplying any one of a charging voltage and a third discharging voltage to the reset node. | 09-19-2013 |
20150116008 | BUILT-IN GATE DRIVER - A built-in gate driver includes a shift register provided in a non-display area of a panel, and configured to include first to gth stages outputting a scan signal, a clock supply line part configured to include m number of clock supply lines connected to the shift register, and a power supply line part configured to include n number of power supply lines connected to the shift register. At least one of the lines of the clock supply lines and the power supply lines are in a first side direction of the shift register, and the other at least one or more lines of the clock supply lines and the power supply lines are in a second side direction of the shift register. | 04-30-2015 |
Patent application number | Description | Published |
20090243696 | HIGH VOLTAGE SEMICONDUCTOR DEVICE HAVING SHIFTERS AND METHOD OF FABRICATING THE SAME - Provided are a high-voltage semiconductor device including a junction termination which electrically isolates a low voltage unit from a high voltage unit, and a method of fabricating the same. The high voltage semiconductor device includes a high voltage unit, a low voltage unit surrounding the high voltage unit, and a junction termination formed between the high voltage unit and the low voltage unit and surrounding the high voltage unit to electrically isolate the high voltage unit from the low voltage unit. The junction termination includes at least one level shifter which level shifts signals from the low voltage unit and supplies the same to the high voltage unit, a first device isolation region surrounding the high voltage unit to electrically isolate the high voltage unit from the level shifter, and a resistor layer electrically connecting neighboring level shifters. | 10-01-2009 |
20100001343 | HIGH VOLTAGE SEMICONDUCTOR DEVICE INCLUDING FIELD SHAPING LAYER AND METHOD OF FABRICATING THE SAME - Provided are a high voltage semiconductor device in which a field shaping layer is formed on the entire surface of a semiconductor substrate and a method of fabricating the same. Specifically, the high voltage semiconductor device includes a first conductivity-type semiconductor substrate. A second conductivity-type semiconductor layer is disposed on a surface of the semiconductor substrate, and a first conductivity-type body region is formed in semiconductor layer. A second conductivity-type source region is formed in the body region. A drain region is formed in the semiconductor layer and is separated from the body region. The field shaping layer is formed on the entire surface of the semiconductor layer facing the semiconductor layer. | 01-07-2010 |
20130196480 | HIGH VOLTAGE SEMICONDUCTOR DEVICE INCLUDING FIELD SHAPING LAYER AND METHOD OF FABRICATING THE SAME - Provided are a high voltage semiconductor device in which a field shaping layer is formed on the entire surface of a semiconductor substrate and a method of fabricating the same. Specifically, the high voltage semiconductor device includes a first conductivity-type semiconductor substrate. A second conductivity-type semiconductor layer is disposed on a surface of the semiconductor substrate, and a first conductivity-type body region is formed in semiconductor layer. A second conductivity-type source region is formed in the body region. A drain region is formed in the semiconductor layer and is separated from the body region. The field shaping layer is formed on the entire surface of the semiconductor layer facing the semiconductor layer. | 08-01-2013 |
20130200427 | TRANSISTORS AND METHODS OF MANUFACTURING THE SAME - A transistor includes a device portion and a collector layer. The device portion is in a first side of a semiconductor substrate, and includes a gate and an emitter. The collector layer is on a second side of the semiconductor substrate, which is opposite to the first side. The collector layer is an impurity-doped epitaxial layer and has a doping profile with a non-normal distribution. | 08-08-2013 |