Patent application number | Description | Published |
20100110922 | Method and Apparatus for Estimating Channel Bandwidth - A bandwidth estimation algorithm detects peaks and/or average per-user bandwidth of data communication networks, such as narrowband and broadband wide-area radio access networks. Estimation can be performed at the TCP/IP layer with no lower layer (PHY, MAC, etc.) information assumed to be available. However, the bandwidth estimation algorithm can be applied to anywhere bandwidth needs to be estimated as well. | 05-06-2010 |
20100302957 | CHANNEL STATE TRANSITION OPTIMIZATION - A system for optimizing communications on a radio network by altering transitions between different link states that includes several modules. The activity, environment, and load module monitor monitors the link layer based on spectral-load metrics and radio-link metrics. The state transition control module determines when user equipment transitions between different states based on the type of user equipment, user equipment battery life, whether the user equipment is connected to an alternating current outlet, a spectral cost, and a backhaul cost. The channel state influencer module uses any of direct messages, ping messages, and keep-alive messages to influence the link state. The policy and preference handler enables or disables transitions based on the bearer technology type, the type of user equipment, the user's subscription plan, and the load level on the network. | 12-02-2010 |
20120106385 | CHANNEL BANDWIDTH ESTIMATION ON HYBRID TECHNOLOGY WIRELESS LINKS - A bandwidth estimation algorithm on shared links detects peaks and/or average per-user bandwidth. Estimating is performed at the transport or IP layer with no assistance from lower layer (PHY, MAC, etc.) and the techniques can be used for any of adjusting the level of video optimization to the available bandwidth; driving QoS decisions at the transmitter based on available bandwidth; improving QoS enforcement during transitions among hybrid technologies on a wireless links; and correcting estimates on devices delivering bursty payload. | 05-03-2012 |
20130107744 | SYSTEMS, STRUCTURES AND ASSOCIATED PROCESSES FOR OPTIMIZATION OF STATE TRANSITIONS WITHIN WIRELESS NETWORKS | 05-02-2013 |
20150092589 | Systems, Structures and Associated Processes for Optimization of State Transitions within Wireless Networks - A system for optimizing communications on a radio network by altering transitions between different link states that includes several modules. The activity, environment, and load module monitor monitors the link layer based on spectral-load metrics and radio-link metrics. The state transition control module determines when user equipment transitions between different states based on the type of user equipment, user equipment battery life, whether the user equipment is connected to an alternating current outlet, a spectral cost, and a backhaul cost. The channel state influencer module uses any of direct messages, ping messages, and keep-alive messages to influence the link state. The policy and preference handler enables or disables transitions based on the bearer technology type, the type of user equipment, the user's subscription plan, and the load level on the network. | 04-02-2015 |
20150124603 | Channel Bandwidth Estimation on Hybrid Technology Wireless Links - A bandwidth estimation algorithm on shared links detects peaks and/or average per-user bandwidth. Estimating is performed at the transport or IP layer with no assistance from lower layer (PHY, MAC, etc.) and the techniques can be used for any of adjusting the level of video optimization to the available bandwidth; driving QoS decisions at the transmitter based on available bandwidth; improving QoS enforcement during transitions among hybrid technologies on a wireless links; and correcting estimates on devices delivering bursty payload. | 05-07-2015 |
Patent application number | Description | Published |
20100289945 | METHOD AND APPARATUS FOR POWER SAVING DURING VIDEO BLANKING PERIODS - Methods and systems are described for enabling display system power saving during the operation of display devices. An integrated circuit package includes input interface circuitry configured to receive an audio-video data stream having a video signal and timing information and timing extraction circuitry that can identify blanking patterns for the video signal. The package includes timing control circuitry configured to implement a power saving process during the blanking periods of the video signal. The invention further includes methods that support the operation of power saving processes. | 11-18-2010 |
20100296562 | DATA SIGNAL IMPROVEMENT USING SIGNAL PEAK DETECTORS IN A RECEIVER - Methods and systems are described for improving a data at a receiver using one or more signal peak detectors. A signal is received having an initial signal level from the transmitter, the signal having a long bit and a short bit. The initial signal voltage of the signal is measured using a signal peak detector. A pre-emphasis value is determined using the signal voltage and is communicated to the transmitter, causing the transmitter to transmit the signal using an adjusted signal level. A second signal voltage of the initial signal is measured using a second signal peak detector, the second signal voltage being used to determine the pre-emphasis value. In another embodiment, a state machine having data relating to appropriate pre-emphasis is used in determining the pre-emphasis value. In another embodiment, one peak detector is used to measure the long bit and another peak detector is used to measure the short bit. In another embodiment, the signal does not have associated link training data. | 11-25-2010 |
20100303187 | AUTOMATICALLY SYNCHRONIZING RING OSCILLATOR FREQUENCY OF A RECEIVER - A ring oscillator in a receiver in a multimedia network is adjusted to compensate for factors that may decrease its accuracy over time using a link training signal from a transmitter device in the network. An incoming signal having a known frequency is received at a receiver or sink device from a transmitter, the signal may be a link training signal used for configuring a link between the two devices. In the receiver, an internally generated clock signal is created, the signal having an internal frequency. The incoming signal and the internally generated clock signal are input into a frequency detector which outputs frequency comparison-based data. The internal frequency is based on the comparison-based data such that it is adjusted to be closer to the known frequency of the incoming signal. | 12-02-2010 |
Patent application number | Description | Published |
20140321439 | Apparatus and Methods for Transmission and Reception of Data in Multi-Antenna Systems - Methods and apparatus adapted to address asymmetric conditions in a multi-antenna system. In one embodiment, the multi-antenna system comprises a wireless (e.g., 3G cellular) multiple-input, multiple-output (MIMO) system, and the methods and apparatus efficiently utilize transmitter and receiver resources based at least in part on a detected asymmetric condition. If an asymmetric condition is detected by the transmitter on any given data stream, the transmitter can decide to utilize only a subset of the available resources for that stream. Accordingly, the signal processing resources for that data stream are adapted to mirror the reduction in resources that are necessary for transmission. The transmitter signals the receiver that it will only be using a subset of the resources available, and the receiver adapts its operation according to the signaling data it receives. The multi-antenna system can therefore reduce power consumption as well as increasing spectral efficiency on the network. | 10-30-2014 |
20150031386 | Methods and Apparatus for Configuration of Femtocells in a Wireless Network - Methods and apparatus that enable and optimize the simultaneous operation of several wireless femtocells having overlapping coverage areas. In one embodiment of the invention, a resource allocation (e.g., time-frequency grid for an OFDM or TDMA based wireless network) governs the simultaneous operation of several femtocells with overlapping coverage areas by specifying uses for resources. A resource allocation unit (RAU) entity is disclosed for managing and modifying resource allocations for femtocells. The community of femtocells can flexibly share resources according to the time-frequency grid, thereby maximizing spectral efficiency without requiring substantial network overhead. | 01-29-2015 |
20150245207 | Network access control methods and apparatus - Methods and apparatus that provide user access control within wireless networks such as those having both fixed and portable nodes. In one embodiment, the network comprises a 3G cellular network or Interworking WLAN (iWLAN), and the portable nodes comprise Home Node B (HNB) base stations. The HNB is configured to authenticate new users, and provide network access while still maintaining user privacy. The portable nodes also may operate in a number of different operating modes which provide different functional control over user access. In one variant, an easy-to-use owner-assigned ID based access control mechanism with a reliable unambiguous user ID is utilized. Methods for providing access control across differing network architectures and protocols, such the aforementioned iWLAN, and business methods, are also described. | 08-27-2015 |
20160057631 | Methods and Apparatus for Configuration of Femtocells in a Wireless Network - Methods and apparatus that enable and optimize the simultaneous operation of several wireless femtocells having overlapping coverage areas. In one embodiment of the invention, a resource allocation (e.g., time-frequency grid for an OFDM or TDMA based wireless network) governs the simultaneous operation of several femtocells with overlapping coverage areas by specifying uses for resources. A resource allocation unit (RAU) entity is disclosed for managing and modifying resource allocations for femtocells. The community of femtocells can flexibly share resources according to the time-frequency grid, thereby maximizing spectral efficiency without requiring substantial network overhead. | 02-25-2016 |
Patent application number | Description | Published |
20150053935 | Organic Light-Emitting Diode Displays With Semiconducting-Oxide and Silicon Thin-Film Transistors - An electronic device may include a display having an array of display pixels on a substrate. The display pixels may be organic light-emitting diode display pixels or display pixels in a liquid crystal display. In an organic light-emitting diode display, hybrid thin-film transistor structures may be formed that include semiconducting oxide thin-film transistors, silicon thin-film transistors, and capacitor structures. The capacitor structures may overlap the semiconducting oxide thin-film transistors. Organic light-emitting diode display pixels may have combinations of oxide and silicon transistors. In a liquid crystal display, display driver circuitry may include silicon thin-film transistor circuitry and display pixels may be based on oxide thin-film transistors. A single layer or two different layers of gate metal may be used in forming silicon transistor gates and oxide transistor gates. A silicon transistor may have a gate that overlaps a floating gate structure. | 02-26-2015 |
20150109276 | Organic Light Emitting Diode Displays with Improved Driver Circuitry - An electronic device may be provided with an organic light-emitting diode display. The display may include row driver circuitry that provides an emission control signal at an output terminal to display pixels. The emission control signals may enable or disable light emission by the pixels. The row driver circuitry may include a bootstrapping capacitor that stores charge for boosting a gate signal at an intermediate node for a pull-up transistor above a power supply voltage. The row driver circuitry may include a pull-down transistor coupled to the intermediate node. The source terminal of the pull-down transistor may be coupled to the output terminal or an additional pull-down transistor may be stacked with the pull-down transistor to reduce leakage current. Charge pump circuitry may be coupled to the intermediate node to ensure that the intermediate node is maintained at a voltage above the power supply voltage. | 04-23-2015 |
20150109279 | Organic Light Emitting Diode Displays with Improved Driver Circuitry - An electronic device may be provided with an organic light-emitting diode display. The display may include row driver circuitry that provides an emission control signal at an output terminal to display pixels. The emission control signals may enable or disable light emission by the pixels. The row driver circuitry may include a bootstrapping capacitor that stores charge for boosting a gate signal at an intermediate node for a pull-up transistor above a power supply voltage. The row driver circuitry may include a pull-down transistor coupled to the intermediate node. The source terminal of the pull-down transistor may be coupled to the output terminal or an additional pull-down transistor may be stacked with the pull-down transistor to reduce leakage current. Charge pump circuitry may be coupled to the intermediate node to ensure that the intermediate node is maintained at a voltage above the power supply voltage. | 04-23-2015 |
20150145849 | Display With Threshold Voltage Compensation Circuitry - A display may have an array of organic light-emitting diode display pixels. Each display pixel may have a light-emitting diode that emits light under control of a drive transistor. Each display pixel may also have control transistors for compensation and programming operations. Each display pixel may have five p-type transistor and two capacitors. One of the five p-type transistors may serve as the drive transistor and may be compensated using the remaining four of the p-type transistors and the two capacitors. A first of the capacitors may be coupled between the gate and source of the drive transistor. A second of the capacitors may have a terminal coupled to the source. Alternatively, each display pixel may have six p-type transistors and a single capacitor. The six p-type transistors may include a drive transistor having a gate coupled to the capacitor. | 05-28-2015 |
20150206931 | Organic Light-Emitting Diode Display with Bottom Shields - A display may have an array of organic light-emitting diode display pixels. Each display pixel may have a light-emitting diode that emits light under control of a drive transistor. Each display pixel may also have control transistors for compensating and programming operations. The array of display pixels may have rows and columns. Row lines may be used to apply row control signals to rows of the display pixels. Column lines (data lines) may be used to apply display data and other signals to respective columns of display pixels. A bottom conductive shielding structure may be formed below each drive transistor. The bottom conductive shielding structure may serve to shield the drive transistor from any electric field generated from the adjacent row and column lines. The bottom conductive shielding structure may be electrically floating or coupled to a power supply line. | 07-23-2015 |
20150268775 | Flexible Displays with Strengthened Pad Area - An electronic device may have a flexible display with portions that can be bent. The display may include an array of display pixels in an active area. Contact pads may be formed in an inactive area of the display. Display circuitry in the active area may exhibit a given stack height, whereas display circuitry in the inactive area may exhibit a stack height that is less than the given stack height. In particular, the contact pads may be formed directly on a multi-buffer layer that sits directly on a flexible display substrate. Passivation material may be selectively formed only at the edges of the contact pad on the multi-buffer layer. The multi-buffer layer may be formed at a distance from the edge of the flexible display substrate to minimize cracking in the multi-buffer layer. | 09-24-2015 |
20150275351 | Evaporation Tool - An evaporation tool is provided that has an elongated evaporation source with elongated edges that run parallel to a longitudinal axis and shorter edges that run perpendicular to the longitudinal axis. The evaporation source has multiple evaporation sources formed by respective source orifices through which material is evaporated. An evaporation control structure is mounted to the evaporation source to enhance the directionality of evaporated material. A shadow mask is provided that has a rectangular frame for supporting a metal mask layer with a pattern of openings. The evaporation control structure ensures that the evaporated material from the source is evaporated towards the shadow mask. Angled walls attached to the elongated edges, a series of vertical walls that extend between the angled walls in the evaporation control structure, and aligned vertical wall extensions on the frame of the shadow mask are used to block evaporated material following angled trajectories. | 10-01-2015 |
20150379938 | Organic Light-Emitting Diode Display With Reduced Lateral Leakage - A display may have an array of pixels. Each pixel may have a light-emitting diode that emits light under control of a drive transistor. The organic light-emitting diodes may have a common cathode layer, a common electron layer, individual red, green, and blue emissive layers, a common hole layer, and individual anodes. The hole layer may have a hole injection layer stacked with a hole transport layer. Pixel circuits for controlling the diodes may be formed from a layer of thin-film transistor circuitry on a substrate. A planarization layer may cover the thin-film transistor layer. Lateral leakage current between adjacent diodes can be blocked by shorting the common hole layer to a metal line such as a bias electrode that is separate from the anodes. The metal line may be laterally interposed between adjacent pixels and may be formed on the planarization layer or embedded within the planarization layer. | 12-31-2015 |
Patent application number | Description | Published |
20110080103 | METHOD AND APPARATUS FOR POWER DRIVING - Aspects of the disclosure provide a power circuit to provide electric energy with control and protection for driving a load, such as a light emitting diode (LED) array, and the like. The power circuit includes a converter, a voltage feedback module, a current feedback module and a controller. The converter is configured to receive electric energy from an energy source and to deliver the electric energy for driving the load. The voltage feedback module is configured to generate a first feedback signal based on a voltage of the delivered electric energy. The current feedback module is configured to generate a second feedback signal based on a current of the delivered electric energy. The controller is configured to receive the first feedback signal and the second feedback signal, and to control the converter to receive and deliver the electric energy based on the first feedback signal and the second feedback signal. | 04-07-2011 |
20110199014 | Dimmer Circuit for Electronic Loads - In one embodiment, a dimmer circuit is coupled to an electronic load and receives an alternating current (AC) signal. A phase control circuit turns the dimmer circuit on for a first portion of the AC signal to turn on the electronic load. The dimmer circuit turns off during a second portion of the AC signal to turn off the electronic load. A switch is coupled to the phase control circuit. The switch is controlled to couple the phase control circuit to ground when the dimmer circuit is off where the switch is part of a power supply supplying power to the electronic load. | 08-18-2011 |
20120002449 | Primary Side Voltage Control in Flyback Converter - In one embodiment, an apparatus includes a sampling component. The sampling component receives a first voltage signal on a primary side of a transformer and monitors the first voltage signal to determine a voltage sampling time. The determined voltage sampling time is when the first voltage signal is used to estimate a second voltage level on a secondary side of the transformer. The first component further samples the first voltage signal at the voltage sampling time to determine a first voltage level. A second component outputs a control signal to control a switch to regulate the second voltage level based on the first voltage level. | 01-05-2012 |
20120081029 | Average Output Current Estimation Using Primary-Side Sensing - In one embodiment, an apparatus includes a transformer comprising a primary side and a secondary side. A switch is coupled to the primary side. A control signal circuit is configured to: sample a first current on the primary side of the transformer; estimate a second current value on the secondary side of the transformer using the sampling of the first current on the primary side and a turn ratio of the transformer; and output a signal to control a turn on time for the switch. | 04-05-2012 |
20120319621 | TRIAC DIMMING SYSTEMS FOR SOLID-STATE LOADS - A system includes a transformer. The transformer includes a first coil and a second coil. The first coil is configured to receive a first voltage based on an output of a switching circuit. The second coil is configured to generate a first current based on the first voltage to power a solid-state load. The system also includes a third coil. The third coil is configured to generate a second voltage based on the first voltage. | 12-20-2012 |
20150015158 | APPARATUSES FOR BLEEDING CURRENT FROM A TRANSFORMER OF A SOLID-STATE LIGHT EMITTING DIODE - A system configured to provide current to power a solid-state light emitting diode in accordance with a dimming level, wherein the dimming level corresponds to an amount of light provided from the solid-state light emitting diode. The system includes a transformer and a switch. The transformer includes a coil. The transformer is configured to receive a first current. The coil is configured to, based on the first current, output a second current to power the solid-state light emitting diode. The switch is configured to, based on a dimming level that corresponds to the amount of light provided from the solid-state light emitting diode of the system, bleed a portion of the second current out of the coil to a ground reference in order to divert the portion of the second current from being supplied to the solid-state light emitting diode. | 01-15-2015 |
Patent application number | Description | Published |
20100224982 | LEAD AND LEAD FRAME FOR POWER PACKAGE - A power device includes a semiconductor chip provided over a substrate, and a patterned lead. The patterned lead includes a raised portion located between a main portion and an end portion. At least part of the raised portion is positioned over the semiconductor chip at a larger height than both the main portion and the end portion. A bonding pad may also be included. The end portion may include a raised portion, bonded portion, and connecting portion. At least part of the bonded portion is bonded to the bonding pad and at least part of the raised portion is positioned over the bonding pad at a larger height than the bonded portion and connecting portion. The end portion may also include a plurality of similarly raised portions. | 09-09-2010 |
20130175704 | DISCRETE POWER TRANSISTOR PACKAGE HAVING SOLDERLESS DBC TO LEADFRAME ATTACH - A packaged power transistor device includes a Direct-Bonded Copper (“DBC”) substrate. Contact pads of a first lead are attached with solderless welds to a metal layer of the DBC substrate. In a first example, the solderless welds are ultrasonic welds. In a second example, the solderless welds are laser welds. A single power transistor realized on a single semiconductor die is attached to the DBC substrate. In one example, a first bond pad of the die is wire bonded to a second lead, and a second bond pad of the die is wire bonded to a third lead. The die, the wire bonds, and the metal layer of the DBC substrate are covered with an amount of plastic encapsulant. Lead trimming is performed to separate the first, second and third leads from the remainder of a leadframe, the result being the packaged power transistor device. | 07-11-2013 |
20130252381 | Electrically Isolated Power Semiconductor Package With Optimized Layout - A packaged power semiconductor device is provided with voltage isolation between a metal backside and terminals of the device. The packaged power semiconductor device is arranged in an encapsulant defining a hole for receiving a structure for physically coupling the device to an object. A direct-bonded copper (“DBC”) substrate is used to provide electrical isolation and improved thermal transfer from the device to a heatsink. At least one power semiconductor die is mounted to a first metal layer of the DBC substrate. The first metal layer spreads heat generated by the semiconductor die. In one embodiment, the packaged power semiconductor device conforms to a TO-247 outline and is capable of receiving a screw for physically coupling the device to a heatsink. | 09-26-2013 |
20140312477 | Lead And Lead Frame For Power Package - A power device includes a semiconductor chip provided over a substrate, and a patterned lead. The patterned lead includes a raised portion located between a main portion and an end portion. At least part of the raised portion is positioned over the semiconductor chip at a larger height than both the main portion and the end portion. A bonding pad may also be included. The end portion may include a raised portion, bonded portion, and connecting portion. At least part of the bonded portion is bonded to the bonding pad and at least part of the raised portion is positioned over the bonding pad at a larger height than the bonded portion and connecting portion. The end portion may also include a plurality of similarly raised portions. | 10-23-2014 |
20150087113 | ELECTRICALLY ISOLATED POWER SEMICONDUCTOR PACKAGE WITH OPTIMIZED LAYOUT - A packaged power semiconductor device is provided with voltage isolation between a metal backside and terminals of the device. The packaged power semiconductor device is arranged in an encapsulant defining a hole for receiving a structure for physically coupling the device to an object. A direct-bonded copper (“DBC”) substrate is used to provide electrical isolation and improved thermal transfer from the device to a heatsink. At least one power semiconductor die is mounted to a first metal layer of the DBC substrate. The first metal layer spreads heat generated by the semiconductor die. In one embodiment, the packaged power semiconductor device conforms to a TO-247 outline and is capable of receiving a screw for physically coupling the device to a heatsink. | 03-26-2015 |
Patent application number | Description | Published |
20160033342 | Force-Sensitive Fingerprint Sensing Input - An object can depress an input device, such as, for example, a function button in an electronic device. A resistive element having a mechanically resistive force can be disposed to resist the depression or movement of the input device. One or more electrodes can be disposed to provide a measure of capacitance based on the depression of the input device. A shield can be disposed to reduce the parasitic capacitance between the one or more electrodes and the object. The electronic device can include a fingerprint sensor operably connected to at least one of the one or more electrodes. | 02-04-2016 |
20160103544 | Force Determination Employing Sheet Sensor and Capacitive Array - A device configured to sense a touch on a surface of the device. The device includes a cover and a force-sensing structure disposed below the cover. The force-sensing structure may be positioned below a display and used in combination with other force-sensing elements to estimate the force of a touch on the cover of a device. | 04-14-2016 |
20160103545 | Temperature Compensating Transparent Force Sensor Having a Complliant Layer - An optically transparent force sensor that may compensate for environmental effects, including, for example, variations in temperature of the device or the surroundings. In some examples, two force-sensitive layers are separated by a compliant layer. The relative electrical response of the two force-sensitive layers may be used to compute an estimate of the force of a touch that reduces the effect of variations in temperature. In some examples, piezoelectric films having anisotropic strain properties are used to reduce the effects of temperature. | 04-14-2016 |
Patent application number | Description | Published |
20130234919 | DEVICES AND METHODS FOR DISCHARGING PIXELS HAVING OXIDE THIN-FILM TRANSISTORS - Methods and devices for discharging a pixel of an electronic display to be turned off are provided. In one example, a method may include supplying an activation signal to the pixel to activate the pixel. The method may also include supplying a data signal of substantially ground to a pixel electrode of the pixel. The method may include controlling a common electrode voltage of the pixel toward substantially ground. The method may also include removing the activation signal from the pixel after the common electrode voltage reaches substantially ground. | 09-12-2013 |
20130235906 | Electronic Device with Dynamic Noise Spectrum Control - An electronic device may contain clock circuits, transmitters, and other circuits that serve as sources of noise signals. The noise signals may be characterized by a noise spectrum. The noise spectrum produced by a noise source can be adjusted by adjusting spread spectrum clock circuitry in a clock circuit, by adjusting data scrambling circuitry in a transmitter circuit, or by making other dynamic adjustments to the circuitry of the electronic device. During operation of the electronic device, sensitive circuitry in the device such as wireless receiver circuitry may be adversely affected by the presence of noise from a noise source in the device. Based on information such as which receiver bands and/or channels are being actively received and target sensitivity levels for the receiver circuitry, control circuitry within the electronic device can determine in real time how to minimize interference between the noise source and the wireless receiver circuitry. | 09-12-2013 |
20140016043 | Touch Screen Display with Transparent Electrical Shielding Layer - A polarizer includes a polarizer component having a top surface and an opposite bottom surface. The bottom surface is configured to couple to a color filter layer for a liquid crystal display. The polarizer also includes a transparent conducting layer disposed over the top surface. The transparent conducting layer being configured to electrically shield the LCD from a touch panel. The polarizer further includes a coating layer disposed over the transparent conducting layer. | 01-16-2014 |
20160097882 | Touch Screen Display with Transparent Electrical Shielding Layer - A polarizer includes a polarizer component having a top surface and an opposite bottom surface. The bottom surface is configured to couple to a color filter layer for a liquid crystal display. The polarizer also includes a transparent conducting layer disposed over the top surface. The transparent conducting layer being configured to electrically shield the LCD from a touch panel. The polarizer further includes a coating layer disposed over the transparent conducting layer. | 04-07-2016 |