Patent application number | Description | Published |
20090147585 | FLEXIBLE WORD LINE BOOSTING ACROSS VCC SUPPLY - Systems and methods for producing a boosted voltage which can be used as a boosted word line voltage for read mode operations of memory cells are disclosed. The system contains a VCC comparator, a look up table, and a boosting circuit including a set of boosting capacitors. The look up table has a list of trim codes that indicates desired boosting ratios. The boosting ratio can vary depending on a level of a supply voltage to provide a sufficient word line voltage, thereby preventing and/or mitigating delay in reading operations. The number of the capacitors in the boosting circuit can be predetermined to be turned on or off according to the trim code. Accordingly, the voltage boost circuit provides a sufficient boosted word line voltage to a core cell gate with flexibility despite fluctuation of the supply voltage level. | 06-11-2009 |
20090180345 | VOLTAGE BOOSTER BY ISOLATION AND DELAYED SEQUENTIAL DISCHARGE - Systems and methods for improving efficiency of a voltage booster for read mode operations of memory cells and discharging a boosted supply voltage safely are disclosed. The system contains a plurality of boosting stages coupled in series including a plurality of boosting capacitors, a plurality of isolators. The isolator can be used to prevent boosting of one capacitor from negatively affecting a charge of the other adjacent capacitor to improve the efficiency of the voltage booster. A voltage booster circuit can accurately boost a supply voltage with a suitable number of boosting stages depending on a level of the supply voltage being provided. Since boosters contain a suitable number of boosting stages, the boosters can discharge a boosted voltage sequentially. With this sequential discharge method, memory cells can not have a hot switching problem. | 07-16-2009 |
20100110819 | Apparatus and Method for Placement of Boosting Cell With Adaptive Booster Scheme - A memory is provided. The memory includes memory arrays and boost converter circuitry. The boost converter circuitry provides at least one boosted voltage to each of the memory arrays when the memory array is being accessed. The boosted voltages may include a word line voltage, and/or a pass gate voltage provided to the gates of pass line transistor in a sector decoders and/or an array decoder for the memory cells being accessed. The boost converter circuitry includes at least two boost converters, and a switch. When one of the memory arrays is accessed, the switch either couples the boost converters together or does not couple the boost converters together based on the distance of the memory array being accessed from the boost converters. | 05-06-2010 |
Patent application number | Description | Published |
20120248688 | DEPINCHING MECHANISM FOR PAPER JAM REMOVAL IN PRINTER - A depinching mechanism including a frame, a star wheel assembly, a limiter arm, a rocker arm and a sensor is provided in present invention. Through the depinching mechanism the star wheel assembly is lifted from the first position to the second position when paper jam occurs, and thus depinched the media the user can clear the paper jam. And after that the star wheel assembly is lowered from the second position to the first position. The star wheel assembly remains in the first position in the normal printing process. Since when paper jam occurs the star wheel assembly is lifted by the depinching mechanism, the user can easily and conveniently remove the jammed paper. And thus, the depinching mechanism can facilitate the user to remove jammed paper when paper jam occurs in printer. Thus, the depinching mechanism can be used in printers to solve the paper jamming problems. | 10-04-2012 |
20120248690 | DEPINCHING MECHANISM FOR PAPER JAM REMOVAL IN PRINTER - A depinching mechanism including a frame, a star wheel assembly, a transmitting device and a sensor is provided in present invention. Through the transmitting device rotating reversely, the star wheel assembly is lifted to the second position when paper jam occurs, thus depinched the media so that user can clear the paper jam. After that the star wheel assembly is lowered to the first position again. The star wheel assembly remains in the first position in normal printing process. Using a one-way clutch and a cam with an outer predetermined profile, the transmitting device rotates forwardly without transmitting any torque during normal printing process, and rotates inversely with transmitting a torque to lift the star wheel assembly up and lower the star wheel assembly down when paper jam occurs. Thus, the depinching mechanism can be used in printers to auto fix the paper jamming problems. | 10-04-2012 |
Patent application number | Description | Published |
20090046511 | REGULATION OF BOOST-STRAP NODE RAMP RATE USING CAPACITANCE TO COUNTER PARASITIC ELEMENTS IN CHANNEL - Systems and/or methods that facilitate accessing data in a memory are presented. The memory can be flash memory that includes a plurality of sectors in an array that can be associated with a decoder component that includes a regulator component, which facilitates performing read operations within a desired period of time. Each sector can be associated with a decoder subcomponent and associated regulator subcomponent. Parasitic resistance and capacitance elements can increase the further in distance a sector and associated decoder component are from a booster component, which is utilized to increase the voltage at a boost-strap node within each decoder subcomponent to facilitate performing read operations. To counter the parasitic elements, each regulator subcomponent can include one or more capacitors, where the number of capacitors and total capacitance value can be determined based on the distance the associated decoder subcomponent is from the booster component. | 02-19-2009 |
20090147585 | FLEXIBLE WORD LINE BOOSTING ACROSS VCC SUPPLY - Systems and methods for producing a boosted voltage which can be used as a boosted word line voltage for read mode operations of memory cells are disclosed. The system contains a VCC comparator, a look up table, and a boosting circuit including a set of boosting capacitors. The look up table has a list of trim codes that indicates desired boosting ratios. The boosting ratio can vary depending on a level of a supply voltage to provide a sufficient word line voltage, thereby preventing and/or mitigating delay in reading operations. The number of the capacitors in the boosting circuit can be predetermined to be turned on or off according to the trim code. Accordingly, the voltage boost circuit provides a sufficient boosted word line voltage to a core cell gate with flexibility despite fluctuation of the supply voltage level. | 06-11-2009 |
20100302846 | CHARGE RETENTION FOR FLASH MEMORY BY MANIPULATING THE PROGRAM DATA METHODOLOGY - A method, system and apparatus for determining whether any un-programmed cell is affected by charge disturb by comparing the voltage threshold of the un-programmed cells against a reference voltage. If the voltage threshold for the un-programmed cell exceeds the reference voltage, the failed or defective un-programmed cell will be then be programmed. This will change the defective un-programmed cell to a new programmed value. To account for the location of the failing memory cell, address syndrome bits are used to identify the location of the defective memory cell. | 12-02-2010 |
20140185393 | DESIGN FOR TEST (DFT) READ SPEED THROUGH TRANSITION DETECTOR IN BUILT-IN SELF-TEST (BIST) SORT - A memory is disclosed that can operate in a normal mode of operation or a testing mode of operation. In the testing mode of operation, the memory can measure various benchmarks of performance, such as read speed. The memory can perform an asynchronous read operation to read a word of electronic data that corresponds to an address or a page read operation in which multiple asynchronous read operations are performed to read multiple words of electronic data, also referred to as a page of electronic data, that correspond to multiple addresses. The memory can measure a time required, referred to as read speed, to read the word of electronic data or the multiple words of electronic data from the memory. In the normal mode of operation, the memory can perform the asynchronous read operation, the page read operation, an asynchronous write operation in which a word of electronic data is stored into the memory that correspond to the address, or a page write operation in which a page electronic data is stored into the memory that correspond to the multiple addresses. | 07-03-2014 |
Patent application number | Description | Published |
20080253550 | Activating Private Access Points For Wireless Networking - A unique identifier is associated with a personal access point. The personal access point is distributed to an end user, who sends a text message including the identifier. Within an automated computer system, the text message is received, a billing account is associated with the personal access point on the basis of the text message, and the personal access point is activated to provide wireless access to a network. | 10-16-2008 |
20080254792 | Controlling Access To Private Access Points For Wireless Networking - An invitation to use a personal access point to access a wireless network is transmitted to an access terminal. An indication that the invitation has been accepted is received and the personal access point is authorized to provide the access terminal with access to the network. | 10-16-2008 |
20090082020 | Selecting embedded cells in wireless networks - An access terminal determines whether a parameter encoded in a signal received from an embedded access point is identified by a list in a memory of the access terminal. Based on the determination, the access terminal initiates communication with a radio area network through the embedded access point. | 03-26-2009 |
20090164547 | PROVIDING ZONE INDICATIONS FOR WIRELESS NETWORKING - Methods and systems for communicating over a wireless network are described. A private access point sends indication information to a mobile station that includes available services provided by the private access point. | 06-25-2009 |
20090170475 | Secure Mobile Base Station Connections - In addition to other aspects disclosed, through a non-secure network, one or more bidirectional secure logical connections are established between a mobile base station and a secure network interface. | 07-02-2009 |
20090172169 | SECURE PROXIES FOR FLAT NETWORKS - A proxy is in communication with an internet protocol network and a mobile operator network. The proxy receives first communications from access points via the internet protocol network, transmits content from the first communications to the mobile operator network, receives second communications from the mobile operator network, and transmits content from the second communications to the access points via the internet protocol network. The proxy may perform operations based on the first and second communications received from either the access points, or from the mobile operator network. The operations performed by the proxy may include modifying the communications, saving certain information regarding the communications, performing authentication, encryption, or decryption of the communications, determining a destination for the communications, or sending the communications to a destination. | 07-02-2009 |
20120178415 | Secure Mobile Base Station Connections - In addition to other aspects disclosed, through a non-secure network, one or more bidirectional secure logical connections are established between a mobile base station and a secure network interface. | 07-12-2012 |
20120302249 | ASSIGNING CODE SPACE TO PORTABLE BASE STATIONS - In addition to other aspects disclosed, a portable base station requests assignment of a portion of a code space from a remotely located control station. The assignment is based upon the location of the portable base station. The portable base station is also capable of transmitting an identification signal using the assigned code space portion to uniquely identify the portable base station to one or more access terminals. | 11-29-2012 |
Patent application number | Description | Published |
20090052289 | SYSTEM AND METHOD OF DEFECT DESCRIPTION OF A DATA STORAGE MEDIUM - The disclosure is directed toward systems and methods of defect description of a data storage medium. In a particular embodiment, a method includes determining a first defect of a data storage medium. The method also includes determining a format of an entry of a defect description table based on the first defect and a location of a second defect of the data storage medium. The format is selected from one of a plurality of formats. The method also includes storing a description of the first defect in the entry of the defect description table in the format. | 02-26-2009 |
20120271994 | METHOD AND DATA STORAGE SYSTEM FOR PROVIDING MULTIPLE PARTITION SUPPORT - An apparatus of the present invention includes partition selection circuitry configured to selectably provide individual access to multiple ones of a plurality of partitions of a data storage component by a host device without multiple partition support. The apparatus can also include the data storage component and/or the host device. The partition selection circuitry uses a logical block addressing (LBA) address generated by the host device, and an operating mode indicator indicative of a particular partition, to allow the partitions of the data storage component to be accessed by the host device without multiple partition support. Methods implemented by the apparatus are also disclosed. | 10-25-2012 |
20120272038 | LOGICAL BLOCK ADDRESS MAPPING - A mapping table is modified to match one or more specified storage conditions of data stored in or expected to be stored in one or more logical block address ranges to physical addresses within a storage drive having performance characteristics that satisfy the specified storage conditions. For example, the performance characteristics may be a reliability of the physical location within the storage drive or a data throughput range of read/write operations. Existing data is moved and/or new data is written to physical addresses on the storage media possessing the performance characteristic(s), according to the mapping table. Further, a standard seeding or a seeding override for the re-mapped logical block addresses can prevent read operations from inadvertently reading incorrect physical addresses corresponding to the re-mapped logical block addresses. | 10-25-2012 |
20150022918 | REQUEST MANAGEMENT FOR ROTATING DATA STORAGE MEDIA - A data storage system and associated method of use may generally be directed to a memory cache that stores a plurality of pending read and write requests. A processor can be configured to prioritize the read requests in the memory cache in response to a sensed acoustic or mechanical vibration in a data storage medium. | 01-22-2015 |