Patent application number | Description | Published |
20120133032 | PACKAGE HAVING ESD AND EMI PREVENTING FUNCTIONS AND FABRICATION METHOD THEREOF - A package having ESD (electrostatic discharge) and EMI (electromagnetic interference) preventing functions includes: a substrate unit having a ground structure and an I/O structure disposed therein; at least a semiconductor component disposed on a surface of the substrate unit and electrically connected to the ground structure and the I/O structure; an encapsulant covering the surface of the substrate unit and the semiconductor component; and a metal layer disposed on exposed surfaces of the encapsulant and side surfaces of the substrate unit and electrically insulated from the ground structure, thereby protecting the semiconductor component against ESD and EMI so as to improve the product yield and reduce the risk of short circuits. | 05-31-2012 |
20120228769 | CARRIER-FREE SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A carrier-free semiconductor package includes a circuit structure having an insulating layer and a circuit layer embedded in the insulating layer and having a plurality of conductive traces and RF (radio frequency) traces, a chip disposed on a first surface of the insulating layer and electrically connected to the conductive traces, an encapsulant covering the chip and the circuit layer, a ground layer formed on a second surface of the insulating layer opposite to the first surface, and a plurality of solder balls disposed on the conductive traces or terminals on the conductive traces, wherein portions of the solder balls electrically connect the ground layer so as to allow the RF traces and the ground layer to form a microstrip line having an RF function, thus obtaining a single-layer carrier-free semiconductor package having low cost and simplified RF design. | 09-13-2012 |
20130093629 | PACKAGING STRUCTURE AND METHOD OF FABRICATING THE SAME - A packaging structure and a method of fabricating the same are provided. The packaging structure includes a substrate, first packaging element disposed on the substrate, a second packaging element disposed on the substrate and spaced apart from the first packaging element, a first antenna disposed on the first packaging element, and a metal layer formed on the second packaging element. The installation of the metal layer and the antenna enhances the electromagnetic shielding effect. | 04-18-2013 |
20140080265 | FABRICATION METHOD OF CARRIER-FREE SEMICONDUCTOR PACKAGE - A carrier-free semiconductor package includes a circuit structure having an insulating layer and a circuit layer embedded in the insulating layer and having a plurality of conductive traces and RF (radio frequency) traces, a chip disposed on a first surface of the insulating layer and electrically connected to the conductive traces, an encapsulant covering the chip and the circuit layer, a ground layer formed on a second surface of the insulating layer opposite to the first surface, and a plurality of solder balls disposed on the conductive traces or terminals on the conductive traces, wherein portions of the solder balls electrically connect the ground layer so as to allow the RF traces and the ground layer to form a microstrip line having an RF function, thus obtaining a single-layer carrier-free semiconductor package having low cost and simplified RF design. | 03-20-2014 |
20140203395 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package and a method of manufacturing the same are provided. The semiconductor package includes: a substrate having a plurality of conductive lands and a plurality of bonding pads surrounding the conductive lands formed on a surface thereof; a plurality of passive devices mounted on the conductive lands; an insulation layer formed on the surface and having a portion of the passive devices embedded therein; a semiconductor chip mounted on a top surface of the insulation layer; a plurality of bonding wires electrically connecting the semiconductor chip and the bonding pads; an encapsulant formed on the surface of the substrate to encapsulate the insulation layer, the bonding wires and the semiconductor chip, wherein a region of the semiconductor chip projected onto the substrate covers a portion of an outermost one of the passive devices. Therefore, the mounting density of the passive devices is improved. | 07-24-2014 |
20140210672 | ELECTRONIC PACKAGE STRUCTURE - An electronic package structure is provided, including a substrate, a package encapsulant disposed on the substrate, and an antenna structure corresponding to a disposing area of the package encapsulant and having a first extension layer, a second extension layer disposed on the substrate, and a connection portion disposed between and electrically connected to the first extension layer and the second extension layer. Through the formation of the antenna structure on the disposing area of the package encapsulant, the substrate is not required to be widen, and, as such, the electronic package structure meets the miniaturization requirement. | 07-31-2014 |
20140210687 | ELECTRONIC PACKAGE AND FABRICATION METHOD THEREOF - An electronic package is provided, which includes: a substrate; at least an electronic element disposed on the substrate; an antenna structure disposed on the substrate; and an encapsulant formed on the substrate for encapsulating the electronic element and the antenna structure. Therein, the antenna structure has an extension portion and a plurality of support portions connected to the extension portion for supporting the extension portion over the substrate so as to save the surface area of the substrate, thereby meeting the miniaturization requirement of the electronic package. | 07-31-2014 |
20150123251 | SEMICONDUCTOR PACKAGE - A semiconductor package is disclosed, which includes: a packaging structure having at least a semiconductor element; and at least three shielding layers sequentially stacked on the packaging structure so as to cover the semiconductor element, wherein a middle layer of the shielding layers is lower in electrical conductivity than adjacent shielding layers on both sides of the middle layer, thereby reducing electromagnetic interferences so as to increase the shielding effectiveness. | 05-07-2015 |
20150145747 | ELECTRONIC PACKAGE AND FABRICATION METHOD THEREOF - An electronic package is disclosed, which includes: a substrate; at least an electronic element disposed on the substrate; an encapsulant formed on the substrate and encapsulating the electronic element; and an antenna body embedded in the encapsulant without contacting with the substrate and exposed from a surface of the encapsulant. Since the antenna body is not disposed on the substrate, the surface area of the substrate can be reduced to meet the miniaturization requirement of the electronic package. | 05-28-2015 |
20150162661 | ELECTRONIC COMPONENT - An electronic component is provided, which includes a substrate having opposite first and second surfaces and an antenna structure combined with the substrate. The antenna structure has at least a first extending portion disposed on the first surface of the substrate, at least a second extending portion disposed on the second surface of the substrate, and a plurality of connecting portions disposed in the substrate for electrically connecting the first extending portion and the second extending portion. Any adjacent ones of the connecting portions are connected through one of the first extending portion and the second extending portion. As such, the antenna structure becomes three-dimensional. The present invention does not need to provide an additional region on the substrate for disposing the antenna structure, thereby reducing the width of the substrate so as to meet the miniaturization requirement of the electronic component. | 06-11-2015 |
Patent application number | Description | Published |
20110175179 | PACKAGE STRUCTURE HAVING MEMS ELEMENT - A package structure having at least an MEMS element is provided, including a chip having electrical connecting pads and the MEMS element; a lid disposed on the chip to cover the MEMS element and having a metal layer provided thereon; first sub-bonding wires electrically connecting to the electrical connecting pads; second sub-bonding wires electrically connecting to the metal layer; an encapsulant disposed on the chip, wherein the top ends of the first and second sub-bonding wires are exposed from the encapsulant; and metallic traces disposed on the encapsulant and electrically connecting to the first sub-bonding wires. The package structure advantageously features reduced size, relatively low costs, diverse bump locations, and an enhanced EMI shielding effect. | 07-21-2011 |
20110177643 | FABRICATION METHOD OF PACKAGE STRUCTURE HAVING MEMS ELEMENT - A fabrication method of a package structure having at least an MEMS element is provided, including: preparing a wafer having electrical connection pads and the at least an MEMS element; disposing lids for covering the at least an MEMS element, the lids having a metal layer formed thereon; electrically connecting the electrical connection pads and the metal layer with bonding wires; forming an encapsulant for covering the lids, bonding wires, electrical connection pads and metal layer; removing portions of the encapsulant to separate the bonding wires each into first and second sub-bonding wires, wherein top ends of the first and second sub-bonding wires are exposed, the first sub-bonding wires electrically connecting to the electrical connection pads, and the second sub-bonding wires electrically connecting to the metal layer; forming metallic traces on the encapsulant for electrically connecting to the first sub-bonding wires; forming bumps on the metallic traces; and performing a singulation process. | 07-21-2011 |
20110227226 | MULTI-CHIP STACK STRUCTURE HAVING THROUGH SILICON VIA - The invention discloses a multi-chip stack structure having through silicon via and a method for fabricating the same. The method includes: providing a wafer having a plurality of first chips; forming a plurality of holes on a first surface of each of the first chips and forming metal posts and solder pads corresponding to the holes so as to form a through silicon via (TSV) structure; forming at least one groove on a second surface of each of the first chips to expose the metal posts of the TSV structure so as to allow at least one second chip to be stacked on the first chip, received in the groove and electrically connected to the metal posts exposed from the groove; filling the groove with an insulating material for encapsulating the second chip; mounting conductive elements on the solder pads of the first surface of each of the first chips and singulating the wafer; and mounting and electrically connecting the stacked first and second chips to a chip carrier via the conductive elements. The wafer, which is not totally thinned but includes a plurality of first chips, severs a carrying purpose during the fabrication process and thereby solves problems, namely a complicated process, high cost, and adhesive layer contamination, facing the prior art that entails repeated use of a carrier board and an adhesive layer for vertically stacking a plurality of chips and mounting the stacked chips on a chip carrier. | 09-22-2011 |
20120168936 | MULTI-CHIP STACK PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF - A multi-chip stack package structure includes: an inner-layer heat sink having a first surface and a second surface opposing one another and having a plurality of conductive vias penetrating the first surface and the second surface; a first chip disposed on the first surface of the inner-layer heat sink; and a second chip disposed on the second surface of the inner-layer heat sink. Thereby, a heat-dissipating path is provided within inner-layers of the multi-chip stack package structure, and the rigidity of the overall structure is enhanced. | 07-05-2012 |
20120224328 | INNER-LAYER HEAT-DISSIPATING BOARD, MULTI-CHIP STACK PACKAGE STRUCTURE HAVING THE INNER LAYER HEAT-DISSIPATING BOARD AND FABRICATION METHOD THEREOF - An inner-layer heat-dissipating board and a multi-chip stack package structure having the inner-layer heat-dissipating board are disclosed. The inner-layer heat-dissipating board includes a metal board body formed with a plurality of penetrating conductive through holes each comprising a plurality of nano wires and an oxidative block having nano apertures filled with the nano wires. The multi-chip stack package structure includes a first chip and an electronic component respectively disposed on the inner-layer heat-dissipating board to thereby facilitate heat dissipation in the multi-chip stack structure as well as increase the overall package rigidity. | 09-06-2012 |
20130020709 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor package and a method of fabricating the same. The semiconductor package includes a carrier having a plurality bonding pads disposed on a surface thereof, a packaging layer formed on the surface of the carrier and having a plurality of openings corresponding to the bonding pads, a conductive material filled in the openings and electrically connected to the bonding pads, and an electronic component installed on the packaging layer and having a plurality of conductive pillars correspondingly received in the openings and electrically connected to the conductive material. The formation of the openings in the packaging layer can control the position and size of the conductive material to enable the overall height of the conductive structure to be level and to keep the electronic component from tilting. | 01-24-2013 |
20130203200 | FABRICATION METHOD OF PACKAGE STRUCTURE HAVING MEMS ELEMENT - A fabrication method of a package structure having at least an MEMS element is provided, including: preparing a wafer having electrical connection pads and the at least an MEMS element; disposing lids for covering the at least an MEMS element, the lids having a metal layer formed thereon; electrically connecting the electrical connection pads and the metal layer with bonding wires; forming an encapsulant for covering the lids, bonding wires, electrical connection pads and metal layer; removing portions of the encapsulant to separate the bonding wires each into first and second sub-bonding wires, wherein top ends of the first and second sub-bonding wires are exposed, the first sub-bonding wires electrically connecting to the electrical connection pads, and the second sub-bonding wires electrically connecting to the metal layer; forming metallic traces on the encapsulant for electrically connecting to the first sub-bonding wires; forming bumps on the metallic traces; and performing a singulation process. | 08-08-2013 |
20130249589 | INTERPOSER AND ELECTRICAL TESTING METHOD THEREOF - An interposer is provided which includes: a substrate having a first surface with a plurality of first conductive pads and a second surface opposite to the first surface, the second surface having a plurality of second conductive pads; a plurality of conductive through holes penetrating the first and second surfaces of the substrate and electrically connecting the first and second conductive pads; and a first removable electrical connection structure formed on the first surface and electrically connecting a portion of the first conductive pads so as to facilitate electrical testing of the interposer. | 09-26-2013 |
20130326873 | METHOD OF FABRICATING MULTI-CHIP STACK PACKAGE STRUCTURE HAVING INNER LAYER HEAT-DISSIPATING BOARD - An inner-layer heat-dissipating board and a multi-chip stack package structure having the inner-layer heat-dissipating board are disclosed. The inner-layer heat-dissipating board includes a metal board body formed with a plurality of penetrating conductive through holes each comprising a plurality of nano wires and an oxidative block having nano apertures filled with the nano wires. The multi-chip stack package structure includes a first chip and an electronic component respectively disposed on the inner-layer heat-dissipating board to thereby facilitate heat dissipation in the multi-chip stack structure as well as increase the overall package rigidity. | 12-12-2013 |
20150035163 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - The present invention provides a semiconductor package and a method of fabricating the same, including: placing a semiconductor element in a groove of a carrier; forming a dielectric layer on the semiconductor element; forming on the dielectric layer a circuit layer electrically connected to the semiconductor element; and removing a first portion of the carrier below the groove to keep a second of the carrier on a sidewall of the groove intact for the second portion to function as a supporting part. The present invention does not require formation of a silicon interposer, therefore the overall cost of the final product is much reduced. | 02-05-2015 |
20150035164 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - The present invention provides a semiconductor package and a method of fabricating the same, including: placing in a groove of a carrier a semiconductor element having opposing active and non-active surfaces, and side surfaces abutting the active surface and the non-active surface; applying an adhesive material in the groove and around a periphery of the side surfaces of the semiconductor element; forming a dielectric layer on the adhesive material and the active surface of the semiconductor element; forming on the dielectric layer a circuit layer electrically connected to the semiconductor element; and removing a first portion of the carrier below the groove to keep a second portion of the carrier on a side wall of the groove intact for the second portion to function as a supporting member. The present invention does not require formation of a silicon interposer, and therefore the overall cost of a final product is much reduced. | 02-05-2015 |
20150041969 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A fabrication method of a semiconductor package is disclosed, which includes the steps of: providing a semiconductor structure having a carrier, a circuit portion formed on the carrier and a plurality of semiconductor elements disposed on the circuit portion; disposing a lamination member on the semiconductor elements; forming an insulating layer on the circuit portion for encapsulating the semiconductor elements; and removing the carrier. The lamination member increases the strength between adjacent semiconductor elements so as to overcome the conventional cracking problem caused by a CTE mismatch between the semiconductor elements and the insulating layer when the carrier is removed. | 02-12-2015 |
20150102433 | PACKAGE STRUCTURE HAVING MEMS ELEMENT - A package structure having at least an MEMS element is provided, including a chip having electrical connecting pads and the MEMS element; a lid disposed on the chip to cover the MEMS element and having a metal layer provided thereon; first sub-bonding wires electrically connecting to the electrical connecting pads; second sub-bonding wires electrically connecting to the metal layer; an encapsulant disposed on the chip, wherein the top ends of the first and second sub-bonding wires are exposed from the encapsulant; and metallic traces disposed on the encapsulant and electrically connecting to the first sub-bonding wires. The package structure advantageously features reduced size, relatively low costs, diverse bump locations, and an enhanced EMI shielding effect. | 04-16-2015 |
Patent application number | Description | Published |
20120308037 | MICROELECTROMECHANICAL MICROPHONE CHIP HAVING STEREOSCOPIC DIAPHRAGM STRUCTURE AND FABRICATION METHOD THEREOF - A microelectromechanical microphone chip having a stereoscopic diaphragm structure includes a base, having a chamber; a diaphragm, disposed on the chamber and having steps with height differences; and a back plate, disposed on the diaphragm, forming a space with the diaphragm in between, and having a plurality of sound-holes communicating with the space. | 12-06-2012 |
20120308066 | COMBINED MICRO-ELECTRO-MECHANICAL SYSTEMS MICROPHONE AND METHOD FOR MANUFACTURING THE SAME - A combined MicroElectroMechanical Systems (MEMS) microphone includes a first substrate, a second substrate, a vibrating diaphragm, a backplate, and an accommodating slot. The first substrate has a first chamber, the vibrating diaphragm is disposed on the first chamber, the second substrate has a second chamber, one side of the backplate is disposed on the second chamber, and the other side of the backplate is disposed on the vibrating diaphragm, so that the second substrate is combined with the first substrate. In addition, the backplate has multiple sound holes, and the accommodating slot is disposed between the first substrate and the second substrate to form a space between the vibrating diaphragm and the backplate. | 12-06-2012 |
20130075835 | MICRO-ELECTRO-MECHANICAL MICROPHONE AND MICRO-ELECTRO-MECHANICAL MICROPHONE CHIP INTEGRATED WITH FILTER - A microelectromechanical microphone comprises a shell body, a microelectromechanical microphone chip and an integrated circuit. The shell body having a cavity and an opening, sound from outside enters into the cavity from the opening. The microelectromechanical microphone chip and the integrated circuit are disposed on a circuit layout inside the cavity. A filter is integrated with the microelectromechanical microphone chip at an appropriate location. Sound entered from the opening into the cavity is received by the microelectromechanical microphone chip, then the sound or audio signals are converted to electrical signals through the filter and the integrated circuit, to be transmitted to external electronic devices. | 03-28-2013 |
20130101143 | MICRO-ELECTRO-MECHANICAL SYSTEM MICROPHONE CHIP WITH AN EXPANDED BACK CHAMBER - A MEMS microphone chip with an expanded chamber comprises a base plate, and the base plate has a main chamber and a secondary chamber. The secondary chamber is formed beside the main chamber, and is connected to the main chamber. A vibration membrane is suspended above the main chamber for receiving external sound waves, and the vibration membrane vibrates in corresponding to the chambers. The MEMS microphone chip has a higher sensitivity because of the expanded chamber, and therefore has a more ideal audio frequency response curve. | 04-25-2013 |
20130322661 | MICRO-ELECTRO-MECHANICAL SYSTEM MICROPHONE CHIP WITH EXPANDED BACK CHAMBER - A MEMS microphone chip with an expanded back chamber includes a first chip unit and a second chip unit. The first chip unit has a first substrate, a vibration membrane layer is formed. above an end of the first substrate, and a space is formed below the vibration membrane layer of the first substrate, so that the vibration membrane layer is suspended above the first substrate to vibrate. The second chip unit has a second substrate to couple with another end of the first substrate, and a groove is formed in the second substrate with. a width larger than that of the space; when the first substrate and the second substrate are coupled together, the groove and the space are connected together to act as the back chamber of the vibration membrane layer. | 12-05-2013 |
Patent application number | Description | Published |
20080230878 | Leadframe based flip chip semiconductor package and lead frame thereof - A flip chip semiconductor package is disclosed according to the present invention, the flip chip semiconductor package comprises a chip that is mounted on and electrically connects to a leadframe via a plurality of solder bumps by means of flip chip, and an encapsulate that encapsulates the chip, the plurality of solder bumps, and the leadframe, wherein, the leadframe further comprises a plurality of leads and a ground plane that is located between the plurality of leads, and also a slit is formed on the ground plane, and then a molding compound that makes up the encapsulant should be capable of filling within the slit, thus to enhance the adhesion between the ground plane and the encapsulant, and then avoid delamination between the ground plane and the encapsulant in subsequent thermal cycle processes, thereby increasing the reliability of fabricated products. | 09-25-2008 |
20120001274 | WAFER LEVEL PACKAGE HAVING A PRESSURE SENSOR AND FABRICATION METHOD THEREOF - A wafer level package having a pressure sensor and a fabrication method thereof are provided. A wafer having the pressure sensor is bonded to a lid, and electrical connecting pads are formed on the wafer. After the lid is cut, wire-bonding and packaging processes are performed. Ends of bonding wires are exposed and serve as an electrical connecting path. A bottom opening is formed on a bottom surface of the wafer, in order to form a pressure sensor path. | 01-05-2012 |
20120018870 | CHIP SCALE PACKAGE AND FABRICATION METHOD THEREOF - A fabrication method of a chip scale package includes: disposing a chip on a carrier board and embedding the chip into a composite board having a hard layer and a soft layer; and removing the carrier board so as to perform a redistribution layer (RDL) process, thereby solving the conventional problems caused by directly attaching the chip on an adhesive film, such as film-softening caused by heat, encapsulant overflow, chip deviation and contamination, etc., all of which may result in poor electrical connection between the wiring layer and the chip electrode pads in the subsequent RDL process and even waste products as a result. | 01-26-2012 |
20120056279 | PACKAGE STRUCTURE HAVING MEMS ELEMENT AND FABRICATION METHOD THEREOF - A package structure having an MEMS element includes: a packaging substrate having first and second wiring layers on two surfaces thereof and a chip embedded therein; a first dielectric layer disposed on the packaging substrate and the chip; a third wiring layer disposed on the first dielectric layer; a second dielectric layer disposed on the first dielectric layer and the third wiring layer and having a recessed portion; a lid disposed in the recessed portion and on the top surface of the second dielectric layer around the periphery of the recessed portion, wherein the portion of the lid on the top surface of the second dielectric layer is formed into a lid frame on which an adhering material is disposed to allow a substrate having an MEMS element to be attached to the packaging substrate with the MEMS element corresponding in position to the recessed portion, thereby providing a package structure of reduced size and costs with better electrical properties. | 03-08-2012 |
20120086117 | PACKAGE WITH EMBEDDED CHIP AND METHOD OF FABRICATING THE SAME - A package embedded with a chip and a method of fabricating the package of embedded chip. The package of embedded chip includes a dielectric layer having a first surface and a second surface opposing the first surface; a plurality of conductive pillars formed in the dielectric layer and exposed from the second surface of the dielectric layer; a chip embedded in the dielectric layer; a circuit layer formed on the first surface of the dielectric layer; a plurality of conductive blind vias formed in the dielectric layer, allowing the circuit layer to be electrically connected via the conductive blind vias to the chip and each of the conductive pillars; and a first solder mask layer formed on the first surface of the dielectric layer and the circuit layer, thereby using conductive pillars to externally connect with other electronic devices as required to form a stacked structure. Therefore, the manufacturing process can be effectively simplified. | 04-12-2012 |
20120104517 | PACKAGE STRUCTURE WITH MICRO-ELECTROMECHANICAL ELEMENT AND MANUFACTURING METHOD THEREOF - A package structure includes a micro-electromechanical element having a plurality of electrical contacts; a package layer enclosing the micro-electromechanical element and the electrical contacts, with a bottom surface of the micro-electromechanical element exposed from a lower surface of the package layer; a plurality of bonding wires embedded in the package layer, each of the bonding wires having one end connected to one of the electrical contacts, and the other end exposed from the lower surface of the package layer; and a build-up layer structure provided on the lower surface of the package layer, the build-up layer including at least one dielectric layer and a plurality of conductive blind vias formed in the dielectric layer and electrically connected to one ends of the bonding wires. The package structure is easier to accurately control the location of an external electrical contact, and the compatibility of the manufacturing procedures is high. | 05-03-2012 |
20120129315 | Method for fabricating semiconductor package - A method for fabricating a semiconductor package includes the steps of: providing an alignment board having a plurality of openings and a plurality of alignment marks corresponding to the openings, respectively; disposing a plurality of chips on the alignment board at positions corresponding to the openings according to the alignment marks; pressing the alignment board with a carrier board having a soft layer disposed on one surface thereof so as to embed the chips in the soft layer of the carrier board; and removing the alignment board. As such, the positions of the chips are accurately positioned according to the alignment marks on the alignment board. | 05-24-2012 |
20120286425 | PACKAGE HAVING MEMS ELEMENT AND FABRICATION METHOD THEREOF - A package structure having an MEMS element is provided, which includes: a protection layer having openings formed therein; conductors formed in the openings, respectively; conductive pads formed on the protection layer and the conductors; a MEMS chip disposed on the conductive pads; and an encapsulant formed on the protection layer for encapsulating the MEMS chip. By disposing the MEMS chip directly on the protection layer to dispense with the need for a carrier, such as a wafer or a circuit board that would undesirably add to the thickness, the present invention reduces the overall thickness of the package to thereby achieve miniaturization. | 11-15-2012 |
20120292722 | PACKAGE STRUCTURE HAVING MEMS ELEMENTS AND FABRICATION METHOD THEREOF - A package structure having MEMS elements includes: a wafer having MEMS elements, electrical contacts and second alignment keys; a plate disposed over the MEMS elements and packaged airtight; transparent bodies disposed over the second alignment keys via an adhesive; an encapsulant disposed on the wafer to encapsulate the plate, the electrical contacts and the transparent bodies; bonding wires embedded in the encapsulant and each having one end connecting a corresponding one of the electrical contacts and the other end exposed from a top surface of the encapsulant; and metal traces disposed on the encapsulant and electrically connected to the electrical contacts via the bonding wires. The present invention eliminates the need to form through holes in a silicon substrate as in the prior art so as to reduce fabrication costs. Further, the present invention accomplishes wiring processes by using a common alignment device to thereby reduce equipment costs. | 11-22-2012 |
20120313243 | CHIP-SCALE PACKAGE - A chip-scale package includes an encapsulating layer, a chip embedded in the encapsulating layer and having an active surface exposed from the encapsulating layer, a buffering dielectric layer formed on the encapsulating layer and the chip, a build-up dielectric layer formed on the buffering dielectric layer, and a circuit layer formed on the build-up dielectric layer and having conductive blind vias penetrating the build-up dielectric layer and being in communication with the openings of the buffering dielectric layer and electrically connected to the chip, wherein the build-up dielectric layer and the buffering dielectric layer are made of different materials. Therefore, delamination does not occur between the buffering dielectric layer and the encapsulating layer, because the buffering dielectric layer is securely bonded to the encapsulating layer and the buffering dielectric layer is evenly distributed on the encapsulating layer. | 12-13-2012 |
20130020709 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor package and a method of fabricating the same. The semiconductor package includes a carrier having a plurality bonding pads disposed on a surface thereof, a packaging layer formed on the surface of the carrier and having a plurality of openings corresponding to the bonding pads, a conductive material filled in the openings and electrically connected to the bonding pads, and an electronic component installed on the packaging layer and having a plurality of conductive pillars correspondingly received in the openings and electrically connected to the conductive material. The formation of the openings in the packaging layer can control the position and size of the conductive material to enable the overall height of the conductive structure to be level and to keep the electronic component from tilting. | 01-24-2013 |
20130187285 | CARRIER, SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A fabrication method of a semiconductor package includes the steps of: providing a carrier having a concave portion and a releasing layer formed on a surface thereof; disposing a chip on the releasing layer in the concave portion; forming an encapsulant on the chip and the releasing layer; removing the releasing layer and the carrier; and forming a circuit structure on the encapsulant and the chip. The design of the concave portion facilitates alignment of the chip to prevent it from displacement, thereby improving the product reliability. A semiconductor package fabricated by the fabrication method is also provided. | 07-25-2013 |
20130228915 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A fabrication method of a semiconductor package includes the steps of: forming a release layer on a carrier having concave portions; disposing chips on the release layer in the concave portions of the carrier; forming an encapsulant on the chips and the release layer; forming a bonding layer on the encapsulant; removing the release layer and the carrier so as to expose the active surfaces of the chips; and forming a circuit structure on the encapsulant and the chips. Since the release layer is only slightly adhesive to the chips and the encapsulant, the present invention avoids warpage of the overall structure during a thermal cycle caused by incompatible CTEs. | 09-05-2013 |
20130249589 | INTERPOSER AND ELECTRICAL TESTING METHOD THEREOF - An interposer is provided which includes: a substrate having a first surface with a plurality of first conductive pads and a second surface opposite to the first surface, the second surface having a plurality of second conductive pads; a plurality of conductive through holes penetrating the first and second surfaces of the substrate and electrically connecting the first and second conductive pads; and a first removable electrical connection structure formed on the first surface and electrically connecting a portion of the first conductive pads so as to facilitate electrical testing of the interposer. | 09-26-2013 |
20130256875 | SEMICONDUCTOR PACKAGE, PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF - A semiconductor package includes: a dielectric layer having opposite first and second surfaces; a semiconductor chip embedded in the dielectric layer and having a plurality of electrode pads; a plurality of first metal posts disposed on the electrode pads of the semiconductor chip, respectively, such that top ends of the first metal posts are exposed from the first surface; at least a second metal post penetrating the dielectric layer such that two opposite ends of the second metal post are exposed from the first and second surfaces, respectively; a first circuit layer formed on the first surface for electrically connecting the first and second metal posts; and a second circuit layer formed on the second surface for electrically connecting the second metal post. The semiconductor package dispenses with conventional laser ablation and electroplating processes for forming conductive posts in a molding compound, thereby saving fabrication time and cost. | 10-03-2013 |
20130341774 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor package is provided, including: an insulating layer; a semiconductor element embedded in the insulating layer; an adhesive body embedded in the insulating layer, wherein a portion of the semiconductor element is embedded in the adhesive body; a patterned metal layer embedded in the adhesive body and electrically connected to the semiconductor element; and a redistribution structure formed on the insulating layer and electrically connected to the patterned metal layer. By embedding the semiconductor element in the adhesive body, the present invention can securely fix the semiconductor element at a predetermined position without any positional deviation, thereby improving the product yield. | 12-26-2013 |
20140015125 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A method of fabricating a semiconductor package is provided, including: providing a carrier having a plurality of chip areas defined thereon, and forming a connection unit on each of the chip areas; disposing a semiconductor element on each of the connection units; forming an insulating layer on the carrier and the semiconductor elements; and forming on the insulating layer a circuit layer electrically connected to the semiconductor elements. Since being formed only on the chip areas instead of on the overall carrier as in the prior art, the connection units are prevented from expanding or contracting during temperature cycle, thereby avoiding positional deviations of the semiconductor elements. | 01-16-2014 |
20140021629 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A method of fabricating a semiconductor package is provided, including: disposing a plurality of semiconductor elements on a carrier through an adhesive layer in a manner that a portion of the carrier is exposed from the adhesive layer; forming an encapsulant to encapsulate the semiconductor elements; removing the adhesive layer and the carrier to expose the semiconductor elements; and forming a build-up structure on the semiconductor elements. Since the adhesive layer is divided into a plurality of separated portions that will not affect each other due to expansion or contraction when temperature changes, the present invention prevents positional deviations of the semiconductor elements during a molding process, thereby increasing the alignment accuracy. | 01-23-2014 |
20140080242 | METHOD FOR MANUFACTURING PACKAGE STRUCTURE WITH MICRO-ELECTROMECHANICAL ELEMENT - A package structure includes a micro-electromechanical element having a plurality of electrical contacts; a package layer enclosing the micro-electromechanical element and the electrical contacts, with a bottom surface of the micro-electromechanical element exposed from a lower surface of the package layer; a plurality of bonding wires embedded in the package layer, each of the bonding wires having one end connected to one of the electrical contacts, and the other end exposed from the lower surface of the package layer; and a build-up layer structure provided on the lower surface of the package layer, the build-up layer including at least one dielectric layer and a plurality of conductive blind vias formed in the dielectric layer and electrically connected to one ends of the bonding wires. The package structure is easier to accurately control the location of an external electrical contact, and the compatibility of the manufacturing procedures is high. | 03-20-2014 |
20140134797 | METHOD FOR FABRICATING SEMICONDUCTOR PACKAGE - A method for fabricating a semiconductor package is disclosed, which includes the steps of: providing a carrier having a release layer and an adhesive layer sequentially formed thereon; disposing a plurality of semiconductor chips on the adhesive layer; forming an encapsulant on the adhesive layer for encapsulating the semiconductor chips; disposing a substrate on the encapsulant; exposing the release layer to light through the carrier so as to remove the release layer and the carrier; and then removing the adhesive layer, thereby effectively preventing the semiconductor chips from being exposed to light so as to avoid any photo damage to the semiconductor chips. | 05-15-2014 |
20140154842 | CARRIER, SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A fabrication method of a semiconductor package includes the steps of: providing a carrier having a concave portion and a releasing layer formed on a surface thereof; disposing a chip on the releasing layer in the concave portion; forming an encapsulant on the chip and the releasing layer; removing the releasing layer and the carrier; and forming a circuit structure on the encapsulant and the chip. The design of the concave portion facilitates alignment of the chip to prevent it from displacement, thereby improving the product reliability. A semiconductor package fabricated by the fabrication method is also provided. | 06-05-2014 |
20140252603 | SEMICONDUCTOR DEVICE HAVING A CONDUCTIVE VIAS - A semiconductor device is provided, including: a substrate having opposing first and second surfaces and a plurality of conductive vias passing through the first and second surfaces; an insulating layer formed on the first surface of the substrate and exposing end portions of the conductive vias therefrom; and a buffer layer formed on the insulating layer at peripheries of the end portions of the conductive vias, thereby increasing product reliability and good yield. | 09-11-2014 |
20140342507 | FABRICATION METHOD OF SEMICONDUCTOR PACKAGE - A semiconductor package includes: a dielectric layer having opposite first and second surfaces; a semiconductor chip embedded in the dielectric layer and having a plurality of electrode pads; a plurality of first metal posts disposed on the electrode pads of the semiconductor chip, respectively, such that top ends of the first metal posts are exposed from the first surface; at least a second metal post penetrating the dielectric layer such that two opposite ends of the second metal post are exposed from the first and second surfaces, respectively; a first circuit layer formed on the first surface for electrically connecting the first and second metal posts; and a second circuit layer formed on the second surface for electrically connecting the second metal post. The semiconductor package dispenses with conventional laser ablation and electroplating processes for forming conductive posts in a molding compound, thereby saving fabrication time and cost. | 11-20-2014 |
20150035163 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - The present invention provides a semiconductor package and a method of fabricating the same, including: placing a semiconductor element in a groove of a carrier; forming a dielectric layer on the semiconductor element; forming on the dielectric layer a circuit layer electrically connected to the semiconductor element; and removing a first portion of the carrier below the groove to keep a second of the carrier on a sidewall of the groove intact for the second portion to function as a supporting part. The present invention does not require formation of a silicon interposer, therefore the overall cost of the final product is much reduced. | 02-05-2015 |
20150035164 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - The present invention provides a semiconductor package and a method of fabricating the same, including: placing in a groove of a carrier a semiconductor element having opposing active and non-active surfaces, and side surfaces abutting the active surface and the non-active surface; applying an adhesive material in the groove and around a periphery of the side surfaces of the semiconductor element; forming a dielectric layer on the adhesive material and the active surface of the semiconductor element; forming on the dielectric layer a circuit layer electrically connected to the semiconductor element; and removing a first portion of the carrier below the groove to keep a second portion of the carrier on a side wall of the groove intact for the second portion to function as a supporting member. The present invention does not require formation of a silicon interposer, and therefore the overall cost of a final product is much reduced. | 02-05-2015 |
20150041969 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A fabrication method of a semiconductor package is disclosed, which includes the steps of: providing a semiconductor structure having a carrier, a circuit portion formed on the carrier and a plurality of semiconductor elements disposed on the circuit portion; disposing a lamination member on the semiconductor elements; forming an insulating layer on the circuit portion for encapsulating the semiconductor elements; and removing the carrier. The lamination member increases the strength between adjacent semiconductor elements so as to overcome the conventional cracking problem caused by a CTE mismatch between the semiconductor elements and the insulating layer when the carrier is removed. | 02-12-2015 |
20150069628 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor package is provided, including a semiconductor substrate having a plurality of conductive vias, a buffer layer formed on the semiconductor substrate, a plurality of conductive pads formed on end surfaces of the conductive vias and covering the buffer layer. During a reflow process, the buffer layer greatly reduces the thermal stress, thereby eliminating the occurance of cracking at the interface of conductive pads. A method of fabricating such a semiconductor package is also provided. | 03-12-2015 |
20150162264 | PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF - A package structure is provided, which includes: a wafer having a surface with a groove, a thin film closing an open end of the groove and electrical contacts; a chip having a surface with a conductive layer and an opposite surface with a concave portion and a seal ring located at a periphery of the concave portion, the chip being disposed on the wafer with the seal ring surrounding the thin film and the electrical contacts located outside the seal ring; an encapsulant formed on the wafer for encapsulating the chip and the electrical contacts; a plurality of sub-conductive wires embedded in the encapsulant with one ends exposed from a top surface of the encapsulant and the other ends in electrical connection with the electrical contacts; and a through hole penetrating the wafer and communicating with the concave portion, thereby reducing the fabrication cost and size of the package structure. | 06-11-2015 |
Patent application number | Description | Published |
20090071278 | Ball screw device having image sensor - A ball screw device includes a number of bearing members received between a ball nut and a screw shaft, and an image device engaged into the bore of the ball nut, and directed toward the screw shaft but spaced from the screw shaft for taking an image of the screw shaft and for viewing a changing of the inner thread of the screw shaft and for allowing the users to change or to replace the worn out ball nut and/or the worn out screw shaft and/or the worn out bearing members right away or at the best time. A processor device may be coupled to the image device for processing the images taken by the image device. A displayer may display the images, and a warning device may generate a warning signal when the screw shaft has been worn out. | 03-19-2009 |
20090090207 | External Circulation Type Ball Screw - An external circulation type ball screw is provided with a helical passage in the outer surface of the nut. The helical passage and the inner helical groove of the nut are opposite in winding direction to each other. The nut is defined with two through holes which are connected to both ends of the inner helical groove and the helical passage, respectively, so that the helical passage and the inner helical groove are connected to each other to form a circulating path for the circulation of the balls. Since the helical passage winds about the outer periphery of the nut, the balls can roll more smoothly. | 04-09-2009 |
20090107273 | Ball screw device having circulating device background of the invention - A ball screw device includes a screw shaft rotatably engaged with a ball nut, and a number of bearing members received between the ball nut and the screw shaft, and a circulating device for circulating the bearing members, the circulating device includes an elongate member having two end blocks for engaging into the ball nut and having a passage for receiving the bearing members, and includes a housing member and a casing member each having a portion of the passage of the elongate member for allowing the passage of the elongate member to be opened and exposed and for allowing the housing member and the casing member to be formed with molding procedures. | 04-30-2009 |
20110023641 | Chain Type Transmission Assembly - A chain type transmission assembly doesn't have the problem that the chain interferes with the transmission assembly, the thickness of the links of the chain of the transmission assembly is precisely calculated by an equation, so that the chain can be prevented from interfering with the outer surface of the screw, thus substantially improving the efficiency and service life of the transmission assembly. | 02-03-2011 |
20110154924 | Ball screw device having cooling structure - A ball screw device includes a ball nut having a bore for receiving a screw shaft, and having a number of longitudinal channels and compartments for forming a zigzag shaped fluid flowing passage in the ball nut, a number of deflecting members engaged with the compartments of the ball nut and each having a recess for communicating adjacent channels with each other, the outer peripheral surfaces of the deflecting members are tilted relative to the ball nut for allowing the deflecting members to be expanded when the deflecting members are expanded, a cooling agent flows through the zigzag shaped fluid flowing passage for cooling the ball nut and for preventing the ball nut from being overheated. | 06-30-2011 |
20130081497 | MOTION TRANSMISSION MODULE WITH A COOLING DEVICE - A motion transmission module with a cooling device is aimed at solving the disadvantage of the conventional motion transmission module that the cooling structure of the conventional motion transmission module would increase the length or outer diameter of the nut. The nut is formed with a flat surface for mounting the cooling device, so that the length of the nut won't be increased. Furthermore, the cooling device also serves as a positioning block to fix the return member, it doesn't increase the outer diameter of the nut. | 04-04-2013 |
20140033847 | MOTION TRANSMISSION MODULE WITH A COOLING DEVICE - A motion transmission module with a cooling device is aimed at solving the disadvantage of the conventional motion transmission module that the cooling structure of the conventional motion transmission module would increase the length or outer diameter of the nut. The nut is formed with a flat surface for mounting the cooling device, so that the length of the nut won't be increased. Furthermore, the cooling device also serves as a positioning block to fix the return member, it doesn't increase the outer diameter of the nut. | 02-06-2014 |