Patent application number | Description | Published |
20130222187 | ANTENNA MODULE - An antenna module capable includes a substrate unit and an antenna unit. The substrate unit includes at least one carrier substrate having a dielectric constant substantially between 7 and 13. The carrier substrate includes a dielectric body and a plurality of nano-scale microparticle structures distributed inside the dielectric body, and each nano-scale microparticle structure includes at least one nano-scale carbon particle and a nano-scale insulating encapsulation layer for totally encapsulating the nano-scale carbon particle. The antenna unit includes at least one antenna track disposed on the carrier substrate. The antenna track has an antenna usage volume that is adjustable within a predetermined volume range according to the VSWR value and the antenna efficiency maintained within a first and a second predetermined ranges, and the antenna track has at least one feeding portion and at least one grounding portion. | 08-29-2013 |
20130241777 | MULTI-BAND ANTENNA STRUCTURE - The instant disclosure relates to a multi-band antenna structure for accepting a feed signal. The antenna structure includes a grounding portion, a radiating portion, and a tuning portion. The radiating portion is spaced apart from the grounding portion and disposed on one side thereof. The radiating portion has a first and a second radiating segments interconnected perpendicularly. The tuning portion is connected between the first radiating segment and the grounding portion. The tuning portion has a hairpin segment and a grounding segment. The hairpin segment is substantially U-shaped and one end thereof is connected to one end of the first radiating segment proximate to the grounding portion. The opposite ends of the grounding segment are connected to the other end of the hairpin segment and the grounding portion. The connecting location between the first radiating segment and the hairpin segment is used for accepting the feed signal. | 09-19-2013 |
20130257665 | ANTENNA STRUCTURE - An antenna structure, used for being fed with a signal, includes a grounding portion, a radiation portion, and a frequency adjusting portion. The radiation portion has a loop segment, a high frequency segment, and a low frequency segment. The loop segment has a feeding sub-segment adjacent to the grounding portion and used for being fed with the signal. The high and low frequency segments are extended from opposite ends of the loop segment away from each other. The frequency adjusting portion is connected to the loop segment and the grounding portion. A high frequency dual-path is formed from a feeding point of the feeding sub-segment and extends along the loop segment in two different directions to the high frequency segment. A low frequency dual-path is formed from the feeding point and extends along the loop segment in two different directions to the low frequency segment. | 10-03-2013 |
20130260675 | MOBILE TERMINAL EXTENSION CASE - A extension case adaptable onto a mobile terminal device to enable extended functions, includes a sheath, an electrical connector, a battery, and a radio frequency identification (RFID) antenna. The sheath is configured to shieldingly receive the mobile terminal device and comprises a covering portion and a buckling portion curvedly extended from an outer edge of the covering portion. The electrical connector is arranged on the buckling portion of the sheath for establishing electrical connection with the mobile terminal device. The battery is disposed on the covering portion and is accessible to the mobile terminal device through the electrical connector. The RFID antenna is electrically connected to the electrical connector and embeddedly disposed in the covering portion adjacent to the battery in a non-overlapping manner. | 10-03-2013 |
20130306739 | RADIO FREQUENCY IDENTIFICATION DEVICE - A radio frequency identification (RFID) device includes a metallic antenna plate, a first metallic tube, and a second metallic tube. The metallic antenna plate has a positioning portion and defines a central axis, a first hole, and a second hole. The positioning portion is formed in the path of the central axis and surrounds the second hole. The first and second metallic tubes are disposed on the metallic antenna plate. The first and second metallic tubes each has one end disposed on the positioning portion. The first and second metallic tubes extend across the first and second holes, respectively and are welded to the metallic antenna plate. The portion of the second metallic tube that extends across the second hole is approximately perpendicular to the portion of the first metallic tube that extends across the first hole. | 11-21-2013 |
20130307739 | TUNABLE ANTENNA INTEGRATED SYSTEM AND MODULE THEREOF - The tunable antenna integrated system may include a tunable antenna module, a bias module, a direct current control module, and a RF module. The tunable antenna module may include a tunable capacitor and an antenna. The tunable capacitor may have the capacitance thereof adjusted according to an adjusting voltage. A resonant frequency of the antenna is controlled by the tunable capacitor. The bias module has a digital/analog converter for receiving a control voltage to generate the adjusting voltage, and the adjusting voltage may be outputted to the tunable capacitor with the value thereof larger than that of the control voltage. The direct current control module is connected to the bias module for outputting the control voltage to the digital/analog converter. The RF module is connected to the bias module, and a RF signal is transmitted between the tunable antenna module and the RF module through the bias module. | 11-21-2013 |
20140061314 | RFID DEVICE FOR NEAR-FIELD COMMUNICATION - This instant disclosure illustrates a RFID device for near-field communication, comprising a substrate, a winding and a RFID circuit. The substrate includes a first surface and a second surface. The windings are spirally reeled and mounted on the first surface and the second surface. A plurality of winding distances are between the windings, and the winding distances are not larger than the first winding distance. The RFID circuit is mounted on the first surface or the second surface of the substrate, and electrically connected to both of winding ends. | 03-06-2014 |
20140078000 | MULTIBAND ANTENNA STRUCTURE - A multiband antenna structure comprises a substrate, a first radiating unit and a second radiating unit. The first radiating unit is disposed on the substrate, having a feed-in end, a first radiating path and a first terminal. The first radiating unit is operated at a first operating frequency. The second radiating unit is disposed on the substrate and has a grounding end, a second radiating path and a second terminal. The second radiating unit is operated at a second operating frequency. The first terminal of the first radiating unit is adjacent to the second radiating path or the second terminal of the second radiating unit is adjacent to the first radiating path for the first radiating unit or the second unit to excite a third operating frequency. The third operating frequency is lower than the lower frequency among the first operating frequency and the second operating frequency. | 03-20-2014 |
20150109168 | MULTI-FREQUENCY ANTENNA AND MOBILE COMMUNICATION DEVICE HAVING THE MULTI-FREQUENCY ANTENNA - The present disclosure provides a multi-frequency antenna for connecting to a circuit board of a mobile communication device. The circuit board has a grounding plane. The mobile communication device has a metal frame coupled to the grounding plane and surrounding the circuit board. The multi-frequency antenna comprises a first radiator and a second radiator. The first radiator is disposed adjacent to a lateral side of the grounding plane. The first radiator has a feeding end and a grounding end. The first radiator surrounds the metal frame adjacent to the lateral side of the grounding plane to forms a loop. The first radiator forms a first current path to provide a first operating mode. The second radiator connected to the first radiator forms a second current path to provide a second operating mode. The frequency of the second operating mode is higher than the frequency of the first operating mode. | 04-23-2015 |
20150372735 | Proximity Activated Antenna Switch System and Method Therefor - A state of a detection signal received from a proximity detector is determined. The first proximity detector is incorporated with a primary antenna at an information handling system. The proximity detector can assert the detection signal in response to detecting that an object external to the information handling system is located close to the proximity detector. A second antenna is coupled to a wireless communication circuit at the information handling system if the detection signal is asserted. | 12-24-2015 |
Patent application number | Description | Published |
20130256492 | THIN-TYPE COLLAPSIBLE FOOT STAND - A thin-type collapsible foot stand includes a base unit, a first rotatable unit and a second rotatable unit. The base unit includes a base body having a first pivot portion, a first connection portion and a first extending portion. The first rotatable unit includes a rotatable platform having a second pivot portion corresponding to the first extending portion, a second connection portion corresponding to the first connection portion, and a second extending portion corresponding to the first pivot portion. The second rotatable unit includes two rotatable support frames. Each rotatable support frame includes a support body disposed between the base body and the rotatable platform, a first pivot structure connected between one end portion of the support body and the first pivot portion, and a second pivot structure connected between the other end portion of the support body and the second pivot portion. | 10-03-2013 |
20130279028 | SLIDING MECHANISM AND ELECTRONIC DEVICE USING THE SAME - The instant disclosure relates to a lens structure, which includes a mounting seat, a sliding carriage, a lens cover, and at least one elastic member, wherein the mounting seat has a first through-hole formed thereon and defines two operating positions, the sliding carriage slidably coupled to the mounting seat and having a second through-hole formed thereon, wherein the second through-hole corresponds to the first through-hole in one operating position, the lens cover arranged on the sliding carriage and having a plurality of heat-dissipating holes formed thereon in correspondence with the second through-hole, one end of the elastic member fixed to the mounting seat, and the other end of the elastic member fixed to the sliding carriage, wherein the sliding carriage is urged to move a predetermined distance form one operating position, the elastic member provides resilient force to drive the sliding carriage to another operating position. | 10-24-2013 |
20150053849 | SENSOR PACKAGE STRUCTURE AND PRODUCTION APPARATUS FOR MANUFACTURING THE SAME - A sensor package structure includes a sensing die, a light-filtering sheet, and an annular pressure-sensitive adhesive sheet. An active surface of the sensing die has a sensing region and a connecting region around the sensing region. The periphery contour of sensing die is greater than or equal to the periphery contour of light-filtering sheet. The pressure-sensitive adhesive sheet has two opposite adhesive surfaces and defines an opening. The adhesive surfaces respectively adhere to the connecting region of the sensing die and the inner surface of the light-filtering sheet, and the sensing region faces the inner surface of the light-filtering sheet via the opening. The sensing region is sealed by the pressure-sensitive adhesive sheet and the light-filtering sheet. Thus, the instant disclosure provides the sensor package structure with low cost, high capacity, and high yield. Moreover, the instant disclosure provides a production apparatus for manufacturing the sensor package structure. | 02-26-2015 |
Patent application number | Description | Published |
20080237750 | Silicided metal gate for multi-threshold voltage configuration - A PMOS (p-channel metal oxide semiconductor) device having at low voltage threshold MOSFET (MOS field effect transistor) with an improved work function and favorable DIBL (drain-induced barrier lowering) and SCE (short channel effect) characteristics, and a method for making such a device. The PMOS device includes a gate structure that is disposed on a substrate and includes a silicided gate electrode. The silicide is preferably nickel-rich and includes a peak platinum concentration at or near the interface between the gate electrode and a dielectric layer that separates the gate electrode from the substrate. The platinum peak region is produced by a multi-step rapid thermal annealing or similar process. The PMOS device may also include two such MOSFETs, one of which is boron-doped and one of which is not. | 10-02-2008 |
20090090935 | High Performance CMOS Device Design - A semiconductor device includes a gate, which comprises a gate electrode and a gate dielectric underlying the gate electrode, a spacer formed on a sidewall of the gate electrode and the gate dielectric, a buffer layer having a first portion underlying the gate dielectric and the spacer and a second portion adjacent the spacer wherein the top surface of the second portion of the buffer layer is recessed below the top surface of the first portion of the buffer layer, and a source/drain region substantially aligned with the spacer. The buffer layer preferably has a greater lattice constant than an underlying semiconductor substrate. The semiconductor device may further include a semiconductor-capping layer between the buffer layer and the gate dielectric, wherein the semiconductor-capping layer has a smaller lattice constant then the buffer layer. | 04-09-2009 |
20130323899 | High Performance CMOS Device Design - A semiconductor device includes a gate, which comprises a gate electrode and a gate dielectric underlying the gate electrode, a spacer formed on a sidewall of the gate electrode and the gate dielectric, a buffer layer having a first portion underlying the gate dielectric and the spacer and a second portion adjacent the spacer wherein the top surface of the second portion of the buffer layer is recessed below the top surface of the first portion of the buffer layer, and a source/drain region substantially aligned with the spacer. The buffer layer preferably has a greater lattice constant than an underlying semiconductor substrate. The semiconductor device may further include a semiconductor-capping layer between the buffer layer and the gate dielectric, wherein the semiconductor-capping layer has a smaller lattice constant then the buffer layer. | 12-05-2013 |
20140264493 | Semiconductor Device and Fabricating the Same - A semiconductor device includes a substrate, a gate stack having at least one gate vertex directed to an area in the substrate below the gate stack. The semiconductor device also includes a source structure having at least one vertex directed toward the area in the substrate and a drain structure having at least one vertex directed toward the area in the substrate. | 09-18-2014 |
20140273366 | Semiconductor Devices and Methods of Manufacture Thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes providing a workpiece including an n-type field effect transistor (N-FET) region, a p-type FET (P-FET) region, and an insulating material disposed over the N-FET region and the P-FET region. The method includes patterning the insulating material to expose a portion of the N-FET region and a portion of the P-FET region, and forming an oxide layer over the exposed portion of the N-FET region and the exposed portion of the P-FET region. The oxide layer over the P-FET region is altered, and a metal layer is formed over a portion of the N-FET region and the P-FET region. The workpiece is annealed to form a metal-insulator-semiconductor (MIS) tunnel diode over the N-FET region and a silicide or germinide material over the P-FET region. | 09-18-2014 |
20150048453 | FinFETs and Methods for Forming the Same - Embodiments of the present disclosure include a semiconductor device, a FinFET device, and methods for forming the same. An embodiment is a semiconductor device including a first semiconductor fin extending above a substrate, the first semiconductor fin having a first lattice constant, an isolation region surrounding the first semiconductor fin, and a first source/drain region in the first semiconductor fin, the first source/drain having a second lattice constant different from the first lattice constant. The semiconductor device further includes a first oxide region along a bottom surface of the first source/drain region, the first oxide region extending into the isolation region. | 02-19-2015 |
20150108430 | TRANSISTOR CHANNEL - A transistor device includes a substrate having a first region and a second region, a first semiconductor layer of a first semiconductor material having a first portion over the first region and a second portion over the second region, the first portion being separated from the second portion, a second semiconductor layer of a second semiconductor material over the second portion of the first semiconductor layer, a first transistor of a first conductivity type, the first transistor disposed within the first region and having a first set of source/drain regions formed in the first semiconductor layer, and a second transistor of a second conductivity type, the second transistor disposed within the second region and having a second set of source/drain regions formed in the second semiconductor layer. The second conductivity type is different than the second conductivity type, and the second semiconductor material is different from the first semiconductor material. | 04-23-2015 |
20160087059 | Semiconductor Device and Method - A vertical gate all around (VGAA) is provided. In embodiments, the VGAA has a nanowire with a first contact pad and a second contact pad. A gate electrode is utilized to help define a channel region within the nanowire. In additional embodiments multiple nanowires, multiple bottom contacts, multiple top contacts, and multiple gate contacts are utilized. | 03-24-2016 |
20160120998 | Cell-Penetrating Drug Carrier and the Application Thereof - This invention is about a cell-penetrating drug carrier and the application thereof. The mentioned cell-penetrating drug carrier can approach the target cell through using a proper recognizable sequence, so that the cell-penetrating drug carrier can be used to specifically delivery wanted drug to target cell. Through carrying wanted drug into the cytoplasm of the target cell by cell-penetrating peptide, the drug accumulation volume in the target cell can be efficiently increased. Preferably, through using proper bioinert polymer, the cell-penetrating peptide and the recognizable sequence can be kept from been digested before approaching the target cell. | 05-05-2016 |
Patent application number | Description | Published |
20140312432 | SEMICONDUCTOR ARRANGEMENT WITH SUBSTRATE ISOLATION - One or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided. A semiconductor arrangement comprises a channel, such as an un-doped channel, over a substrate. The semiconductor arrangement comprises a gate, such as a gate-all-around structure gate, around the channel. The semiconductor arrangement comprises an isolation structure, such as a silicon germanium oxide structure, between the gate and the substrate. The isolation structure blocks current leakage into the substrate. Because the semiconductor arrangement comprises the isolation structure, the channel can be left un-doped, which improves electron mobility and decreases gate capacitance. | 10-23-2014 |
20150380548 | VERTICAL DEVICE ARCHITECTURE - The present disclosure relates to a vertical transistor device having rectangular vertical channel bars extending between a source region and a drain region, and an associated method of formation. In some embodiments, the vertical transistor device has a source region disposed over a semiconductor substrate. A channel region with one or more vertical channel bars is disposed over the source region. The one or more vertical channel bars have a bottom surface abutting the source region that has a rectangular shape (i.e., a shape with four sides, with adjacent sides of different length, and four right angles). A gate region is located over the source region at a position abutting the vertical channel bars, and a drain region is disposed over the gate region and the vertical channel bars. The rectangular shape of the vertical channel bars provides for a vertical device having good performance and cell area density. | 12-31-2015 |
20160079239 | SERIES-CONNECTED TRANSISTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A series-connected transistor structure includes a first source, a first channel-drain structure, a second channel-drain structure, a gate dielectric layer, a gate, a first drain pad and a second drain pad. The first source is over a substrate. The first channel-drain structure is over the first source and includes a first channel and a first drain thereover. The second channel-drain structure is over the first source and substantially parallel to the first channel-drain structure and includes a second channel and a second drain thereover. The gate dielectric layer surrounds the first channel and the second channel. The gate surrounds the gate dielectric layer. The first drain pad is over and in contact with the first drain. The second drain pad is over and in contact with the second drain, in which the first drain pad and the second drain pad are separated from each other. | 03-17-2016 |
Patent application number | Description | Published |
20140112578 | IMAGE RECOGNITION METHOD AND IMAGE RECOGNITION SYSTEM - An image recognition method and an image recognition system can be applied to fetal ultrasound images. The image recognition method includes: (a) adjusting the image with a filter operator to decrease noise and to homogenize an image expression level of the pixel units within an individual object structure; (b) analyzing the image by a statistic information function, determining a foreground object pixel unit and a background pixel unit according to a max information entropy state of the statistic information function; and (c) searching by a profile setting value and recognizing a target object image among the foreground object pixel unit. The image recognition method can not only increase the efficiency of identifying the object of interests within the image and measuring the object of interests, but also improve the precision of measurements of the object of interests. | 04-24-2014 |
20140126841 | REAL-TIME CLOUD IMAGE SYSTEM AND MANAGING METHOD THEREOF - A real-time cloud imaging system includes at least a frontend device and a backend system. The frontend device generates an instruction message and a ROI (Region of Interest) message, and the backend system is coupled to the frontend device. The backend system has at least a raw image, wherein the raw image has a plurality of images of different resolutions. Each of the images and the raw image are composed of a plurality of tiles. The ROI message corresponds to a region of interest respectively within each of the images and the raw image. The backend system, according to the instruction message and the ROI message, selectively provides a grouping of the tiles within the region of interest of the raw image or one of the images to the frontend device. | 05-08-2014 |
20150093001 | IMAGE SEGMENTATION SYSTEM AND OPERATING METHOD THEREOF - An image segmentation system for performing image segmentation on an image data includes an image preprocessing module, a motion analyzing module, a detection module, a classification module, and a multi-dimensional detection module. The image data has a plurality of image stacks ordered chronologically that respectively have a plurality of images sequentially ordered according to spatial levels, wherein one spatial level is designated as a first stack. The image preprocessing module transforms the images into binary images while the motion analyzing module finds a repeating pattern in the binary images in the first stack and accordingly generates a repeating motion result. The classification module generates a classification result based on a spatial and an anatomical assumption to classify objects. The multi-dimensional detection module generates segmentation results for stacks above and below the first stack using spatial and temporal consistency of geometric layouts of object structures. | 04-02-2015 |
20150154755 | IMAGE REGISTRATION METHOD - An image registration method for registering images into a coordinate system includes the following steps: (a) performing image normalization on a source image and generating a normalized image; (b) retrieving at least one color-deconvoluted image from color-deconvoluting the source image; (c) determining at least one image feature from the at least one color-deconvoluted image; (d) comparing the at least one image feature of the at least one color-deconvoluted image with a target image, and generating a relative matching structural feature result; and (e) transforming the normalized image into a registered image according to the matching structural feature result. | 06-04-2015 |
Patent application number | Description | Published |
20100259999 | KEEPERS, INTEGRATED CIRCUITS, AND SYSTEMS THEREOF - A keeper of an integrated circuit includes a first transistor having a first gate being coupled with an output end of an inverter. A second transistor is coupled with the first transistor in series. The second transistor has a second gate being coupled with an input end of the inverter. | 10-14-2010 |
20100271898 | ACCESS TO MULTI-PORT DEVICES - Mechanisms for improving static noise margin and/or reducing misread current in multi-port devices are disclosed. In some embodiments related to dual port SRAM a suppress device (e.g., transistor) is provided at each word line port. When both ports are activated, both suppress devices are on and lower the voltage level of these ports, which in turn lower the voltage level at the node storing the data for the memory. As the voltage level at the data node is lowered, noise margin is improved and read disturb can be avoided. | 10-28-2010 |
20110019458 | MEMORY CIRCUITS, SYSTEMS, AND METHODS FOR ROUTING THE MEMORY CIRCUITS - A memory circuit includes a first memory array. The first memory array includes at least one first memory cell for storing a first datum. The at least one first memory cell is coupled with a first word line and a second word line. A second memory array is coupled with the first memory array. The second memory array includes at least one second memory cell for storing a second datum. The at least one second memory cell is coupled with a third word line and a fourth word line. The first word line is coupled with the third word line. The first word line is misaligned from the third word line in a routing direction of the first word line in the first memory array. | 01-27-2011 |
20110019460 | MEMORY CIRCUITS, SYSTEMS, AND FABRICATION METHODS THEREOF - A memory circuit includes a plurality of bit lines. A first memory cell and a second memory cell are coupled in series. Each of the first memory cell and the second memory cell is capable of storing a first type datum. The first memory cell and the second memory cell share a first common source/drain (S/D) region. The first common S/D region is electrically isolated from all of the bit lines. | 01-27-2011 |
20110242904 | Read Only Memory and Operating Method Thereof - A read only memory (ROM) and an operating method thereof are provided. The read only memory includes: a control circuit, powered by a first power source for outputting a control signal within a first voltage range; a voltage shifter, for expanding the amplitude of the control signal to a second voltage range; a word line driver, powered by a second power source with a voltage which is higher than that of the first power source, for driving one of a plurality of word lines of a read only memory cell array according to the control signal which is expanded to be within the second voltage range; and an input/output circuit, for connecting the plurality of bit lines to read out messages. | 10-06-2011 |
20120014158 | MEMORY DEVICES - A memory device includes an array of transistors, a plurality of bit lines, and a plurality of source lines. The transistors include gate, drain and source terminals. The gate terminals are electrically coupled to word lines. The plurality of bit lines connect a power source to the drain terminals of the array of transistors and the plurality of source lines connect the power source to the source terminals of the array of transistors. The connections are made active during a standby mode, thereby limiting leakage current without entailing drawbacks associated with degraded memory access/cycle time. | 01-19-2012 |
20120213010 | Asymmetric Sense Amplifier Design - A circuit includes a first inverter including a first PMOS transistor and a first NMOS transistor, and a second inverter including a second PMOS transistor and a second NMOS transistor. A first node is connected to gates of the first PMOS transistor and the first NMOS transistor and drains of the second PMOS transistor and the second NMOS transistor. A second node is connected to gates of the second PMOS transistor and the second NMOS transistor and drains of the first PMOS transistor and the first NMOS transistor. The circuit further includes a first capacitor having a first capacitance connected to the first node; and a second capacitor having a second capacitance connected to the second node. The second capacitance is greater than the first capacitance. | 08-23-2012 |
20130188417 | MEMORY CIRCUIT AND METHOD FOR ROUTING THE MEMORY CIRCUIT - A memory circuit includes a first row of memory cells, a first word line and a second word line over and electrically coupled to the first row of memory cells, a second row of memory cells aligned with the first row of memory cells along a predetermined direction, and a third word line and a fourth word line over and electrically coupled to the second row of memory cells. The first word line is aligned with the third word line, and the second word line is aligned with the fourth word line. One of the first word line or the second word line is electrically coupled with one of the third word line or the fourth word line. The other one of the first word line or the second word line is electrically decoupled from the other one of the third word line or fourth word line. | 07-25-2013 |
20130235687 | Asymmetric Sense Amplifier Design - A circuit includes a first inverter including a first PMOS transistor and a first NMOS transistor, and a second inverter including a second PMOS transistor and a second NMOS transistor. A first node is connected to gates of the first PMOS transistor and the first NMOS transistor and drains of the second PMOS transistor and the second NMOS transistor. A second node is connected to gates of the second PMOS transistor and the second NMOS transistor and drains of the first PMOS transistor and the first NMOS transistor. The circuit further includes a first capacitor having a first capacitance connected to the first node; and a second capacitor having a second capacitance connected to the second node. The second capacitance is greater than the first capacitance. | 09-12-2013 |
20140133253 | System and Method for Memory Testing - An embodiment method of testing a memory includes writing a first logic state to a first cell in a first clock cycle and reading the first logic state in the first cell in a second clock cycle in a first phase, and reading the first logic state in the first cell and writing a second logic state to the first cell in the first clock cycle and reading the second logic state in the first cell in the second clock cycle in a second phase. As such, a concurrent read/write operation is performed at the same time and for the same memory bit (i.e., the first cell). | 05-15-2014 |
20140153349 | Simultaneous Two/Dual Port Access on 6T SRAM - A method includes generating a first and a second internal clock signal from a clock signal, wherein a first internal clock signal edge of the first internal clock signal and a second internal clock signal edge of the second internal clock signal are generated from a same edge of the clock signal. A first one of the first and the second internal clock edges is used to trigger a first operation on a six-transistor (6T) Static Random Access Memory (SRAM) cell of a SRAM array. A second one of the first and the second internal clock edges is used to trigger a second operation on the 6T SRAM cell. The first and the second operations are performed on different ports of the 6T SRAM. The first and the second operations are performed within a same clock cycle of the clock signal. | 06-05-2014 |
20140269021 | TIMING LOGIC FOR MEMORY ARRAY - Among other things, techniques and systems are provided for devising a schedule for performing read/write operations on a memory cell. A control signal is provided to timing logic. Using one or more properties of the control signal, such as a voltage property, the timing logic is configured to adjust a time window during which at least one of a read operation or a write operation is performed within a cycle. In this way, the timing logic affects a dynamic switch between an early-read operation, a late-read operation, an early-write operation, a late-write operation, a read-then-write operation, and a write-then-read operation between cycles. In some embodiments, the memory cell for which the schedule is devised is an SRAM cell, such as a six-transistor SRAM cell. | 09-18-2014 |
20150076575 | METHOD AND APPARATUS FOR FORMING AN INTEGRATED CIRCUIT WITH A METALIZED COUPLING CAPACITOR - An integrated circuit includes a plurality of metal layers of bit cells of a memory cell array disposed in a first metal layer and extending in a first direction, a plurality of word lines of the memory cell array disposed in a second metal layer and extending in a second direction that is different from the first direction, and at least two conductive traces disposed in a third metal layer substantially adjacent to each other and extending at least partially across the memory cell array, a first one of the at least two conductive traces coupled to a driving source node of a write assist circuit, and a second conductive trace of the at least two conductive traces coupled to an enable input of the write-assist circuit, where the at least two conductive traces form at least one embedded capacitor having a capacitive coupling to the bit line. | 03-19-2015 |
20150162273 | DEVICE HAVING MULTIPLE-LAYER PINS IN MEMORY MUX1 LAYOUT - An integrated circuit (IC) memory device that includes a first conductive layer, a second conductive layer electrically coupled to the first conductive layer, the second conductive layer formed over the first conductive layer, a third conductive layer separated from the second conductive layer, the third conductive layer formed over the second conductive layer, a fourth conductive layer electrically coupled to the third conductive layer, the fourth conductive layer formed over the third conductive layer, a 2P2E pin box formed in and electrically coupled to the first conductive layer or the second conductive layer and a 1P1E pin box formed in and electrically coupled to the third conductive layer or the fourth conductive layer. | 06-11-2015 |
20150194206 | METHOD OF WRITING TO AND READING DATA FROM A THREE-DIMENSIONAL TWO PORT REGISTER FILE - A method comprises selecting a memory cell included in a memory cell array in which data is to be stored. The memory cell array is connected with a logic gate array. The memory cells of the memory cell array are individually coupled with a corresponding logic gate of the logic gate array by a separate word line output. The method also comprises communicating a write row output signal to the logic gate array. The write row output signal is communicated from a write address row decoder to the logic gate array. The write address row decoder has a plurality of write row outputs coupled with the logic gate array. The method further comprises communicating a write column output signal to the logic gate array. The write column output signal is communicated from a write address column decoder to the logic gate array. | 07-09-2015 |
20150310924 | READ-ONLY MEMORY - A configuration for a bit-1 read-only memory (ROM) cell is provided. The bit-1 ROM cell comprises a first circuit connected to a second circuit. The first circuit comprises a first transistor and the second circuit comprises a second transistor. The second circuit is configured to receive a YMUX signal. The second circuit is connected to a word-line bar. The second circuit is configured to maintain a disconnection or connection between the first transistor and the word-line bar based upon the YMUX signal. The first circuit is located on a different physical layer than the second circuit. | 10-29-2015 |
20150364412 | DEVICE HAVING MULTIPLE-LAYER PINS IN MEMORY MUX1 LAYOUT - An integrated circuit (IC) memory device includes a first conductive layer. The IC memory device also includes a second conductive layer over the first conductive layer. The IC memory device further includes a first-type pin box electrically coupled with the first conductive layer. The IC memory device additionally includes a second-type pin box, different from the first-type pin box, electrically coupled with the second conductive layer. | 12-17-2015 |
20150380077 | STATIC RANDOM ACCESS MEMORY AND METHOD OF CONTROLLING THE SAME - A static random access memory (SRAM) including at least a memory cell array, a first data line connected to the memory cell array, and a read assist unit connected to the first data line. The read assist unit is configured to suppress a voltage level of the first data line during a read operation of the memory cell array. | 12-31-2015 |