Patent application number | Description | Published |
20130328017 | SIDE-GATE DEFINED TUNABLE NANOCONSTRICTION IN DOUBLE-GATED GRAPHENE MULTILAYERS - A graphene-based electrically tunable nanoconstriction device and a non-transitory tangible computer readable medium encoded with a program for fabricating the device that includes a back-gate dielectric layer over a conductive substrate are described. The back-gate dielectric layer may be hexagonal boron nitride, mica, SiOx, SiNx, BNx, HfOx or AlOx. A graphene layer is an AB-stacked bi-layer graphene layer, an ABC-stacked tri-layer graphene layer or a stacked few-layer graphene layer. Contacts formed over a portion of the graphene layer include at least one source contact, at least one drain contact and at least one set of side-gate contacts. A graphene channel with graphene side gates is formed in the graphene layer between at least one source contact, at least one the drain contact and at least one set of side-gate contacts. A top-gate dielectric layer is formed over the graphene layer. A top-gate electrode is formed on the top-gate dielectric layer. | 12-12-2013 |
20130330885 | SIDE-GATE DEFINED TUNABLE NANOCONSTRICTION IN DOUBLE-GATED GRAPHENE MULTILAYERS - A method to fabricate a novel graphene based, electrically tunable, nanoconstriction device is described. The device includes a back-gate dielectric layer formed over a conductive substrate. The back-gate dielectric layer is, in one example, hexagonal boron nitride, mica, SiOx, SiNx, BNx, HfOx or AlOx. A graphene layer is an AB-stacked bi-layer graphene layer, an ABC-stacked tri-layer graphene layer or a stacked few-layer graphene layer. Contacts are formed over a portion of the graphene layer including at least one source contact, at least one drain contact and at least one set of side-gate contacts. A graphene channel with graphene side gates is formed in the graphene layer between the at least one source contact, the at least one the drain contact and the at least one set of side-gate contacts. A top-gate dielectric layer is formed over the graphene layer. A top-gate electrode is formed on the top-gate dielectric layer. | 12-12-2013 |
20140151770 | THIN FILM DEPOSITION AND LOGIC DEVICE - A method for depositing a material on a graphene layer includes arranging a graphene layer having an exposed substantially planar surface proximate to a magnetron assembly that is operative to emit a plasma plume substantially along a first line, wherein the exposed planar surface of the graphene layer is arranged at an angle that is non-orthogonal to the first line where the first line intersects the exposed planar surface; and emitting the plasma plume from the magnetron assembly such that a layer of deposition material is disposed on the graphene layer without appreciably damaging the graphene layer. | 06-05-2014 |
20140151771 | THIN FILM DEPOSITION AND LOGIC DEVICE - A method for depositing a material on a graphene layer includes arranging a graphene layer having an exposed substantially planar surface proximate to a magnetron assembly that is operative to emit a plasma plume substantially along a first line, wherein the exposed planar surface of the graphene layer is arranged at an angle that is non-orthogonal to the first line where the first line intersects the exposed planar surface; and emitting the plasma plume from the magnetron assembly such that a layer of deposition material is disposed on the graphene layer without appreciably damaging the graphene layer. | 06-05-2014 |