Patent application number | Description | Published |
20100065944 | SEMICONDUCTOR DEVICE WITH DECOUPLING CAPACITOR DESIGN - An integrated circuit includes a circuit module having a plurality of active components coupled between a pair of supply nodes, and a capacitive decoupling module coupled to the circuit module. The capacitive decoupling module includes a plurality of metal-insulator-metal (MiM) capacitors coupled in series between the pair of supply nodes, wherein a voltage between the supply nodes is divided across the plurality of MiM capacitors, thereby reducing voltage stress on the capacitors. | 03-18-2010 |
20100213572 | Dual-Dielectric MIM Capacitors for System-on-Chip Applications - An integrated circuit structure includes a chip having a first region and a second region. A first metal-insulator-metal (MIM) capacitor is formed in the first region. The first MIM capacitor has a first bottom electrode; a first top electrode over the first bottom electrode; and a first capacitor insulator between and adjoining the first bottom electrode and the first top electrode. A second MIM capacitor is in the second region and is substantially level with the first MIM capacitor. The second MIM capacitor includes a second bottom electrode; a second top electrode over the second bottom electrode; and a second capacitor insulator between and adjoining the second bottom electrode and the second top electrode. The second capacitor insulator is different from the first capacitor insulator. The first top electrode and the first bottom electrode may be formed simultaneously with the second top electrode and the second bottom electrode, respectively. | 08-26-2010 |
20100224925 | METAL-INSULATOR-METAL STRUCTURE FOR SYSTEM-ON-CHIP TECHNOLOGY - The present disclosure provides a semiconductor device that includes a semiconductor substrate, an isolation structure formed in the semiconductor substrate, a conductive layer formed over the isolation structure, and a metal-insulator-metal (MIM) capacitor formed over the isolation structure. The MIM capacitor has a crown shape that includes a top electrode, a first bottom electrode, and a dielectric disposed between the top electrode and the first bottom electrode, the first bottom electrode extending at least to a top surface of the conductive layer. | 09-09-2010 |
20120289021 | METAL-INSULATOR-METAL STRUCTURE FOR SYSTEM-ON-CHIP TECHNOLOGY - The present disclosure provides a semiconductor device that includes a semiconductor substrate, an isolation structure formed in the semiconductor substrate, a conductive layer formed over the isolation structure, and a metal-insulator-metal (MIM) capacitor formed over the isolation structure. The MIM capacitor has a crown shape that includes a top electrode, a first bottom electrode, and a dielectric disposed between the top electrode and the first bottom electrode, the first bottom electrode extending at least to a top surface of the conductive layer. | 11-15-2012 |
20130307021 | CMOS Device and Method of Forming the Same - A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a first region and a second region. The semiconductor device further includes a first buffer layer formed over the substrate and between first and second isolation regions in the first region and a second buffer layer formed over the substrate and between first and second isolation regions in the second region. The semiconductor device further includes a first fin structure formed over the first buffer layer and between the first and second isolation regions in the first region and a second fin structure formed over the second buffer layer and between the first and second isolation regions in the second region. The first buffer layer includes a top surface different from a top surface of the second buffer layer. | 11-21-2013 |
20140113432 | Semiconductor Fins with Reduced Widths and Methods for Forming the Same - A method includes forming Shallow Trench Isolation (STI) regions extending from a top surface of a semiconductor substrate into the semiconductor substrate, and after the forming the STI regions, oxidizing an upper portion of a semiconductor strip between the STI regions. A width of the upper portion of the semiconductor strip is reduced by the oxidizing. The STI regions are recessed, until a portion of the upper portion of the semiconductor strip is higher than a top surface of remaining portions of the STI regions to form a semiconductor fin. | 04-24-2014 |
20140131776 | Fin Recess Last Process for FinFET Fabrication - A method includes forming isolation regions extending from a top surface of a semiconductor substrate into the semiconductor substrate, and forming a hard mask strip over the isolation regions and a semiconductor strip, wherein the semiconductor strip is between two neighboring ones of the isolation regions. A dummy gate strip is formed over the hard mask strip, wherein a lengthwise direction of the dummy gate strip is perpendicular to a lengthwise direction of the semiconductor strip, and wherein a portion of the dummy gate strip is aligned to a portion of the semiconductor strip. The method further includes removing the dummy gate strip, removing the hard mask strip, and recessing first portions of the isolation regions that are overlapped by the removed hard mask strip. A portion of the semiconductor strip between and contacting the removed first portions of the isolation regions forms a semiconductor fin. | 05-15-2014 |
20140141582 | CMOS DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a first region and a second region. The semiconductor device further includes a first buffer layer formed over the substrate and between first and second isolation regions in the first region and a second buffer layer formed over the substrate and between first and second isolation regions in the second region. The semiconductor device further includes a first fin structure formed over the first buffer layer and between the first and second isolation regions in the first region and a second fin structure formed over the second buffer layer and between the first and second isolation regions in the second region. The first buffer layer includes a top surface different from a top surface of the second buffer layer. | 05-22-2014 |
20140175561 | Method of Fabricating a Gate all Around Device - The device includes a wafer substrate including an isolation feature, a fin base embedded in the isolation feature, at least one channel disposed above the fin base, and a gate stack disposed around the channel, wherein the gate stack includes a top portion and a bottom portion of the gate stack formed by filling a cavity around the channel such that the top portion and bottom portion are aligned each other. The device further includes at least one source and one drain disposed over the fin base, wherein the channel connects the source and the drain. The device further includes the source and the drain disposed over a fin insulator disposed over the fin base. | 06-26-2014 |
20140183633 | Semiconductor Devices and Methods of Manufacture Thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes partially manufacturing a fin field effect transistor (FinFET) including a semiconductor fin comprising a first semiconductive material and a second semiconductive material disposed over the first semiconductive material. A top portion of the second semiconductive material of the semiconductor fin is removed, and a top portion of the first semiconductive material is exposed. A top portion first semiconductive material is removed from beneath the second semiconductive material. The first semiconductive material and the second semiconductive material are oxidized, forming a first oxide comprising a first thickness on the first semiconductive material and a second oxide comprising a second thickness on the second semiconductive material, the first thickness being greater than the second thickness. The second oxide is removed from the second semiconductive material, and manufacturing of the FinFET is completed. | 07-03-2014 |
20140183643 | Transistors with Wrapped-Around Gates and Methods for Forming the Same - A device includes a substrate, a semiconductor strip over the substrate, a gate dielectric wrapping around the semiconductor strip, and a gate electrode wrapping around the gate dielectric. A dielectric region is overlapped by the semiconductor strip. The semiconductor strip and the dielectric region are spaced apart from each other by a bottom portion of the gate dielectric and a bottom portion of the gate electrode. | 07-03-2014 |
20140197456 | Semiconductor Device and Fabricating the Same - The present disclosure provides a semiconductor device. The semiconductor device includes a substrate having a gate region, source and drain (S/D) regions separated by the gate region and a first fin structure in a gate region in the N-FET region. The first fin structure is formed by a first semiconductor material layer as a lower portion, a semiconductor oxide layer as a middle portion and a second semiconductor material layer as an upper portion. The semiconductor device also includes a second fin structure in S/D regions in the N-FET region. The second fin structure is formed by the first semiconductor material layer as a lower portion and the semiconductor oxide layer as a first middle portion, the first semiconductor material layer as a second middle portion beside the first middle and the second semiconductor material layer as an upper portion. | 07-17-2014 |
20140197457 | FinFET Device and Method of Fabricating Same - The present disclosure provides a semiconductor device. The semiconductor device includes a substrate having isolation regions, a gate region, source and drain regions separated by the gate region, a first fin structure in a gate region. The first fin structure includes a first semiconductor material layer as a lower portion of the first fin structure, a semiconductor oxide layer as an outer portion of a middle portion of the first fin structure, the first semiconductor material layer as a center portion of the middle portion of the first fin structure and a second semiconductor material layer as an upper portion of the first fin structure. The semiconductor device also includes a source/drain feature over the substrate in the source/drain region between two adjacent isolation regions and a high-k (HK)/metal gate (MG) stack in the gate region, wrapping over a portion of the first fin structure. | 07-17-2014 |
20140197458 | FinFET Device and Method of Fabricating Same - An integrated circuit structure includes a semiconductor substrate, and isolation regions extending into the semiconductor substrate, wherein the isolation regions have opposite sidewalls facing each other. A fin structure includes a silicon fin higher than top surfaces of the isolation regions, a germanium-containing semiconductor region overlapped by the silicon fin, silicon oxide regions on opposite sides of the germanium-containing semiconductor region, and a germanium-containing semiconductor layer between and in contact with the silicon fin and one of the silicon oxide regions. | 07-17-2014 |
20140203334 | METHOD FOR FABRICATING A FINFET DEVICE INCLUDING A STEM REGION OF A FIN ELEMENT - A method includes providing a substrate having a fin extending from a first (e.g., top) surface of the substrate. The fin has first region (a stem region) and a second region (an active region) each having a different composition. The first region of the fin is modified to decrease a width of semiconductor material for example by etching and/or oxidizing the first region of the fin. The method then continues to provide a gate structure on the second region of the fin. FinFET devices having stem regions with decreased widths of semiconductor material are also provided. | 07-24-2014 |
20140231872 | METHOD FOR INDUCING STRAIN IN FINFET CHANNELS - FinFETs in which a swelled material within the fin, typically an oxide of the fin semiconductor, causes strain that significantly increases charge carrier mobility within the FinFET channel. The concept can be applied to either p-type or n-type FinFETs. For p-type FinFETs the swelled material is positioned underneath the source and drain regions. For n-type FinFETs the swelled material is positioned underneath the channel region. The swelled material can be used with or without strain-inducing epitaxy on the source and drain areas and can provide greater strain than is achievable by strain-inducing epitaxy alone. | 08-21-2014 |
20140273366 | Semiconductor Devices and Methods of Manufacture Thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes providing a workpiece including an n-type field effect transistor (N-FET) region, a p-type FET (P-FET) region, and an insulating material disposed over the N-FET region and the P-FET region. The method includes patterning the insulating material to expose a portion of the N-FET region and a portion of the P-FET region, and forming an oxide layer over the exposed portion of the N-FET region and the exposed portion of the P-FET region. The oxide layer over the P-FET region is altered, and a metal layer is formed over a portion of the N-FET region and the P-FET region. The workpiece is annealed to form a metal-insulator-semiconductor (MIS) tunnel diode over the N-FET region and a silicide or germinide material over the P-FET region. | 09-18-2014 |
20140306297 | RECESSING STI TO INCREASE FIN HEIGHT IN FIN-FIRST PROCESS - A method includes forming a semiconductor fin over top surfaces of insulation regions, and forming a gate stack on a top surface and sidewalls of a middle portion of the semiconductor fin. The insulation regions include first portions overlapped by the gate stack, and second portions misaligned from the gate stack. An end portion of the semiconductor fin is etched to form a recess located between the second portions of the insulation regions. An epitaxy is performed to grow a source/drain region from the recess. After the epitaxy, a recessing is performed to recess the second portions of the insulation regions, with the second portions of the insulation regions having first top surfaces after the first recessing. A dielectric mask layer is formed on the first top surfaces of the second portions of the insulation regions. The dielectric mask layer further extends on a sidewall of the gate stack. | 10-16-2014 |
20140312398 | RECESSING STI TO INCREASE FIN HEIGHT IN FIN-FIRST PROCESS - A method includes forming a gate stack over top surfaces of a semiconductor strip and insulation regions on opposite sides of the semiconductor strip. The insulation regions include first portions overlapped by the gate stack, and second portions misaligned from the gate stack. An end portion of the semiconductor strip is etched to form a recess, wherein the recess is located between the second portions of the insulation regions. An epitaxy is performed to grow a source/drain region from the recess. After the epitaxy, a recessing is performed to recess the second portions of the insulation regions, with the second portions of the insulation regions having first top surfaces after the first recessing. After the recessing, a dielectric mask layer is formed on the first top surfaces of the second portions of the insulation regions, wherein the dielectric mask layer further extends on a sidewall of the gate stack. | 10-23-2014 |
20140312432 | SEMICONDUCTOR ARRANGEMENT WITH SUBSTRATE ISOLATION - One or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided. A semiconductor arrangement comprises a channel, such as an un-doped channel, over a substrate. The semiconductor arrangement comprises a gate, such as a gate-all-around structure gate, around the channel. The semiconductor arrangement comprises an isolation structure, such as a silicon germanium oxide structure, between the gate and the substrate. The isolation structure blocks current leakage into the substrate. Because the semiconductor arrangement comprises the isolation structure, the channel can be left un-doped, which improves electron mobility and decreases gate capacitance. | 10-23-2014 |
20140332859 | Self-Aligned Wrapped-Around Structure - An embodiment vertical wrapped-around structure and method of making. An embodiment method of making a self-aligned vertical structure-all-around device including forming a spacer around an exposed portion of a semiconductor column projecting from a structure layer, forming a photoresist over a protected portion of the structure layer and a first portion of the spacer, etching away an unprotected portion of the structure layer disposed outside a periphery collectively defined by the spacer and the photoresist to form a structure having a footer portion and a non-footer portion, the non-footer portion and the footer portion collectively encircling the semiconductor column, and removing the photoresist and the spacer. | 11-13-2014 |
20140346607 | Tuning Tensile Strain on FinFET - A fin field effect transistor (FinFET) having a tunable tensile strain and an embodiment method of tuning tensile strain in an integrated circuit are provided. The method includes forming a source/drain region on opposing sides of a gate region in a fin, forming spacers over the fin, the spacers adjacent to the source/drain regions, depositing a dielectric between the spacers; and performing an annealing process to contract the dielectric, the dielectric contraction deforming the spacers, the spacer deformation enlarging the gate region in the fin. | 11-27-2014 |
20140353731 | Tuning Strain in Semiconductor Devices - A Fin Field-Effect Transistor (FinFET) includes a semiconductor layer over a substrate, wherein the semiconductor layer forms a channel of the FinFET. A first silicon germanium oxide layer is over the substrate, wherein the first silicon germanium oxide layer has a first germanium percentage. A second silicon germanium oxide layer is over the first silicon germanium oxide layer. The second silicon germanium oxide layer has a second germanium percentage greater than the first germanium percentage. A gate dielectric is on sidewalls and a top surface of the semiconductor layer. A gate electrode is over the gate dielectric. | 12-04-2014 |
20150021697 | Thermally Tuning Strain in Semiconductor Devices - A method includes performing a first epitaxy to grow a silicon germanium layer over a semiconductor substrate, performing a second epitaxy to grow a silicon layer over the silicon germanium layer, and performing a first oxidation to oxidize the silicon germanium layer, wherein first silicon germanium oxide regions are generated. A strain releasing operation is performed to release a strain caused by the first silicon germanium oxide regions. A gate dielectric is formed on a top surface and a sidewall of the silicon layer. A gate electrode is formed over the gate dielectric. | 01-22-2015 |
20150028389 | SEMICONDUCTOR DEVICES COMPRISING A FIN - A semiconductor device may include a fin disposed over a workpiece. The fin may include: a first semiconductive material disposed over the workpiece; an oxide of the first semiconductive material disposed over the first semiconductive material; a second conductive material disposed over and spaced apart from the oxide of the first semiconductive material; a first insulating material disposed around and lining the second semiconductive material; a conductive material disposed around the first insulating material; and a second insulating material disposed between the oxide of the first semiconductive material and a portion of the conductive material facing the workpiece, the second insulating material further lining sidewalls of the conductive material. | 01-29-2015 |
20150028426 | BURIED SIGE OXIDE FINFET SCHEME FOR DEVICE ENHANCEMENT - The present disclosure relates to a Fin field effect transistor (FinFET) device having a buried silicon germanium oxide structure configured to enhance performance of the FinFET device. In some embodiments, the FinFET device has a three-dimensional fin of semiconductor material protruding from a substrate at a position located between first and second isolation regions. A gate structure overlies the three-dimensional fin of semiconductor material. The gate structure controls the flow of charge carriers within the three-dimensional fin of semiconductor material. A buried silicon-germanium-oxide (SiGeOx) structure is disposed within the three-dimensional fin of semiconductor material at a position extending between the first and second isolation regions. | 01-29-2015 |
20150034899 | Semiconductor Device and Fabricating the Same - The present disclosure provides a method for fabricating an integrated circuit (IC) device. The method includes providing a precursor including a substrate having first and second metal-oxide-semiconductor (MOS) regions. The first and second MOS regions include first and second gate regions, semiconductor layer stacks, source/drain regions and isolation regions. The method includes exposing and oxidizing the first semiconductor layer stack to form a first outer oxide layer and a first inner nanowire, and removing the first outer oxide layer to expose the first inner nanowire in the first gate region. A first high-k/metal gate (HK/MG) stack wraps around the first inner nanowire. The method includes exposing and oxidizing the second semiconductor layer stack to form second outer oxide layer and inner nanowire, and removing the second outer oxide layer to expose the second inner nanowire in the second gate region. A second HK/MG stack wraps around the second inner nanowire. | 02-05-2015 |
20150035071 | Semiconductor Device and Fabricating the Same - The present disclosure provides a method for fabricating an integrated circuit device. The method includes providing a precursor including a substrate having first and second metal-oxide-semiconductor (MOS) regions. The first and second MOS regions include first and second gate regions, semiconductor layer stacks, and source/drain regions respectively. The method further includes laterally exposing and oxidizing the semiconductor layer stack in the first gate region to form first outer oxide layer and inner nanowire set, and exposing the first inner nanowire set. A first high-k/metal gate (HK/MG) stack wraps around the first inner nanowire set. The method further includes laterally exposing and oxidizing the semiconductor layer stack in the second gate region to form second outer oxide layer and inner nanowire set, and exposing the second inner nanowire set. A second HK/MG stack wraps around the second inner nanowire set. | 02-05-2015 |
20150048441 | SEMICONDUCTOR ARRANGEMENT WITH ONE OR MORE SEMICONDUCTOR COLUMNS - A semiconductor arrangement comprises a substrate region and a first semiconductor column projecting from the substrate region. The semiconductor arrangement comprises a second semiconductor column projecting from the substrate region. The second semiconductor column is separated a first distance from the first semiconductor column. The first distance is between about 10 nm to about 30 nm. | 02-19-2015 |
20150048453 | FinFETs and Methods for Forming the Same - Embodiments of the present disclosure include a semiconductor device, a FinFET device, and methods for forming the same. An embodiment is a semiconductor device including a first semiconductor fin extending above a substrate, the first semiconductor fin having a first lattice constant, an isolation region surrounding the first semiconductor fin, and a first source/drain region in the first semiconductor fin, the first source/drain having a second lattice constant different from the first lattice constant. The semiconductor device further includes a first oxide region along a bottom surface of the first source/drain region, the first oxide region extending into the isolation region. | 02-19-2015 |
20150048454 | METHOD FOR FABRICATING A GATE ALL AROUND DEVICE - The device includes a wafer substrate including an isolation feature, a fin base embedded in the isolation feature, at least one channel disposed above the fin base, and a gate stack disposed around the channel, wherein the gate stack includes a top portion and a bottom portion of the gate stack formed by filling a cavity around the channel such that the top portion and bottom portion are aligned each other. The device further includes at least one source and one drain disposed over the fin base, wherein the channel connects the source and the drain. The device further includes the source and the drain disposed over a fin insulator disposed over the fin base. | 02-19-2015 |
20150053928 | SILICON AND SILICON GERMANIUM NANOWIRE FORMATION - Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. For example, one or more silicon and silicon germanium stacks are utilized to form PMOS transistors comprising germanium nanowire channels and NMOS transistors comprising silicon nanowire channels. In an example, a first silicon and silicon germanium stack is oxidized to transform silicon to silicon oxide regions, which are removed to form germanium nanowire channels for PMOS transistors. In another example, silicon and germanium layers within a second silicon and silicon germanium stack are removed to form silicon nanowire channels for NMOS transistors. PMOS transistors having germanium nanowire channels and NMOS transistors having silicon nanowire channels are formed as part of a single fabrication process. | 02-26-2015 |
20150054039 | FinFet Device with Channel Epitaxial Region - The present disclosure relates to a Fin field effect transistor (FinFET) device having epitaxial enhancement structures, and an associated method of fabrication. In some embodiments, the FinFET device has a semiconductor substrate having a plurality of isolation regions overlying the semiconductor substrate. A plurality of three-dimensional fins protrude from a top surface of the semiconductor substrate at locations between the plurality of isolation regions. Respective three-dimensional fins have an epitaxial enhancement structure that introduces a strain into the three-dimensional fin. The epitaxial enhancement structures are disposed over a semiconductor material within the three-dimensional fin at a position that is more than 10 nanometers above a bottom of an adjacent isolation region. Forming the epitaxial enhancement structure at such a position provides for sufficient structural support to avoid isolation region collapse. | 02-26-2015 |
20150060996 | SEMICONDUCTOR DEVICE WITH SILICIDE - A semiconductor device includes a first type region including a first conductivity type. The semiconductor device includes a second type region including a second conductivity type. The semiconductor device includes a channel region extending between the first type region and the second type region. The semiconductor device includes a first silicide region on a first type surface region of the first type region. The first silicide region is separated at least one of a first distance from a first type diffusion region of the first type region or a second distance from the channel region. | 03-05-2015 |
20150069474 | Isolation Structure of Fin Field Effect Transistor - The disclosure relates to a fin field effect transistor (FinFET). An exemplary FinFET comprises a substrate comprising a major surface; a fin structure protruding from the major surface comprising a lower portion comprising a first semiconductor material having a first lattice constant; an upper portion comprising the first semiconductor material, wherein a bottom portion of the upper portion comprises a dopant with a first peak concentration; a middle portion between the lower portion and upper portion, wherein the middle portion comprises a second semiconductor material having a second lattice constant different from the first lattice constant; and an isolation structure surrounding the fin structure, wherein a portion of the isolation structure adjacent to the bottom portion of the upper portion comprises the dopant with a second peak concentration equal to or greater than the first peak concentration. | 03-12-2015 |
20150069475 | SEMICONDUCTOR DEVICE WITH REDUCED ELECTRICAL RESISTANCE AND CAPACITANCE - A semiconductor device includes a first type region including a first conductivity type. The semiconductor device includes a second type region including a second conductivity type. The semiconductor device includes a channel region extending between the first type region and the second type region. The channel region is separated a first distance from a first portion of the first type region. The semiconductor device includes a gate region surrounding the channel region. A first portion of the gate region is separated a second distance from the first portion of the first type region. The second distance is greater than the first distance. | 03-12-2015 |
20150091099 | FinFETs with Gradient Germanium-Containing Channels - A method includes forming a semiconductor fin, forming a dummy gate on a top surface and sidewalls of the semiconductor fin, and removing the dummy gate to form a recess. The semiconductor fin is exposed to the recess. After the dummy gate is removed, an oxidation is performed on the semiconductor fin to form a condensed germanium-containing fin in the recess, and a silicon oxide layer on a top surface and sidewalls of the condensed germanium-containing fin. The method further includes forming a gate dielectric over the condensed germanium-containing fin, and forming a gate electrode over the gate dielectric. | 04-02-2015 |
20150097227 | SEMICONDUCTOR DEVICE WITH REDUCED GATE LENGTH - A semiconductor device includes a first type region including a first conductivity type. The semiconductor device includes a second type region including a second conductivity type. The semiconductor device includes a channel region extending between the first type region and the second type region. The semiconductor device includes a gate region surrounding the channel region. The gate region includes a gate electrode. A gate electrode length of the gate electrode is less than about 10 nm. A method of forming a semiconductor device is provided. | 04-09-2015 |
20150102411 | FinFET with Buried Insulator Layer and Method for Forming - A fin structure suitable for a FinFET and having a buried insulator layer is disclosed. In an exemplary embodiment, a semiconductor device comprises a substrate with a first semiconductor material and having a fin structure formed thereupon. The fin structure includes a lower region proximate to the substrate, a second semiconductor material disposed on the lower region, a third semiconductor material disposed on the second semiconductor material, and an insulating material selectively disposed on the second semiconductor material such that the insulating material electrically isolates a channel region of the fin structure and further such that the insulating material exerts a strain on the channel region. The semiconductor device further comprises an isolation feature disposed adjacent to the fin structure. | 04-16-2015 |
20150108544 | Fin Spacer Protected Source and Drain Regions in FinFETs - An integrated circuit device includes a semiconductor substrate, insulation regions extending into the semiconductor substrate, and a semiconductor fin protruding above the insulation regions. The insulation regions include a first portion and a second portion, with the first portion and second portion on opposite sides of the semiconductor fin. The integrated circuit device further includes a gate stack on a top surface and sidewalls of the semiconductor fin, and a semiconductor region connected to an end of the semiconductor fin. The semiconductor region includes a first semiconductor region formed of a first semiconductor material, wherein the first semiconductor region comprise faceted top surfaces, and a second semiconductor region underlying the first semiconductor region. The second semiconductor region has a higher germanium concentration than the first semiconductor region. A fin spacer is on a sidewall of the second semiconductor region, wherein the fin spacer overlaps a portion of the insulation regions. | 04-23-2015 |
20150132901 | Semiconductor Device and Fabricating the Same - The present disclosure provides a semiconductor device. The semiconductor device includes a substrate having a gate region, source and drain (S/D) regions separated by the gate region and a first fin structure in a gate region in the N-FET region. The first fin structure is formed by a first semiconductor material layer as a lower portion, a semiconductor oxide layer as a middle portion and a second semiconductor material layer as an upper portion. The semiconductor device also includes a second fin structure in S/D regions in the N-FET region. The second fin structure is formed by the first semiconductor material layer as a lower portion and the semiconductor oxide layer as a first middle portion, the first semiconductor material layer as a second middle portion beside the first middle and the second semiconductor material layer as an upper portion. | 05-14-2015 |
20150144998 | Fin Structure of Semiconductor Device - A fin structure of a semiconductor device, such as a fin field effect transistor (FinFET), and a method of manufacture, is provided. In an embodiment, trenches are formed in a substrate, and a liner is formed along sidewalls of the trenches, wherein a region between adjacent trenches define a fin. A dielectric material is formed in the trenches. Portions of the semiconductor material of the fin are replaced with a second semiconductor material and a third semiconductor material, the second semiconductor material having a different lattice constant than the substrate and the third semiconductor material having a different lattice constant than the second semiconductor material. Portions of the second semiconductor material are oxidized. | 05-28-2015 |
20150144999 | Structure and Method For FinFET Device With Buried Sige Oxide - The present disclosure provides a semiconductor device that includes a substrate of a first semiconductor material; a fin feature having a first portion, a second portion and a third portion stacked on the substrate; an isolation feature formed on the substrate and disposed on sides of the fin feature; semiconductor oxide features including a second semiconductor material, disposed on recessed sidewalls of the second portion, defining dented voids overlying the semiconductor oxide features and underlying the third portion; and a gate stack disposed on the fin feature and the isolation feature. The gate stack includes a gate dielectric layer extended into and filling in the dented voids. The first and third portions include the first semiconductor material having a first lattice constant. The second portion includes the second semiconductor material having a second lattice constant different from the first lattice constant. | 05-28-2015 |
20150187944 | Semiconductor Liner of Semiconductor Device - The disclosure relates to a fin field effect transistor (FinFET). An exemplary FinFET comprises a substrate comprising a major surface; a fin structure protruding from the major surface comprising a lower portion, an upper portion, and a middle portion between the lower portion and upper portion, wherein the fin structure comprises a first semiconductor material having a first lattice constant; a pair of notches extending into opposite sides of the middle portion; and a semiconductor liner adjoining the lower portion comprising a second semiconductor material having a second lattice constant greater than the first lattice constant. | 07-02-2015 |
20150194503 | Fin Structure of Semiconductor Device - Semiconductor devices and methods of manufacturing the same are disclosed. In some embodiments, a method of manufacturing a semiconductor device comprises forming a fin structure over a substrate. The fin structure may comprise a lower portion protruding from a major surface of the substrate, an upper portion, and a middle portion between the lower portion and the upper portion, wherein the lower portion and the middle portion differ in composition. The method may further include forming an isolation structure surrounding the fin structure and oxidizing the fin structure. The oxidizing may form a pair of notches extending from sidewalls of the fin structure into the middle portion of the fin structure. | 07-09-2015 |
20150200252 | Fin Structure of Semiconductor Device - A semiconductor device and method of formation are provided herein. A semiconductor device includes a fin having a first wall extending along a first plane, the fin including a doped region defining a first furrow on a first side of the first plane. A dielectric is disposed within the first furrow, such that the dielectric is in contact with the first furrow between a first end of the dielectric and a second end of the dielectric. The first end is separated a first distance from the first plane. The dielectric disposed within the furrow increases the isolation of a channel portion of adjacent fins, and thus decreases current leakage of a FinFET, as compared to a FinFET including fins that do not include a dielectric disposed within a furrow. | 07-16-2015 |
20150200267 | SEMICONDUCTOR DEVICE AND FORMATION THEREOF - A semiconductor device and method of formation are provided herein. A semiconductor device includes a fin having a doped region, in some embodiments. The semiconductor device includes a gate over a channel portion of the fin. The gate including a gate electrode over a gate dielectric between a first sidewall spacer and a second sidewall spacer. The first sidewall spacer includes an initial first sidewall spacer over a first portion of a dielectric material. The second sidewall spacer includes an initial second sidewall spacer over a second portion of the dielectric material. | 07-16-2015 |
20150200300 | SEMICONDUCTOR DEVICE AND FORMATION THEREOF - A semiconductor device and method of formation are provided herein. A semiconductor device includes a fin having a first wall extending along a first plane, the fin including a doped region defining a first furrow on a first side of the first plane. A dielectric is disposed within the first furrow, such that the dielectric is in contact with the first furrow between a first end of the dielectric and a second end of the dielectric. The first end is separated a first distance from the first plane. The dielectric disposed within the furrow increases the isolation of a channel portion of adjacent fins, and thus decreases current leakage of a FinFet, as compared to a FinFet including fins that do not include a dielectric disposed within a furrow. | 07-16-2015 |
20150214333 | Tuning Strain in Semiconductor Devices - A Fin Field-Effect Transistor (FinFET) includes a semiconductor layer over a substrate, wherein the semiconductor layer forms a channel of the FinFET. A first silicon germanium oxide layer is over the substrate, wherein the first silicon germanium oxide layer has a first germanium percentage. A second silicon germanium oxide layer is over the first silicon germanium oxide layer. The second silicon germanium oxide layer has a second germanium percentage greater than the first germanium percentage. A gate dielectric is on sidewalls and a top surface of the semiconductor layer. A gate electrode is over the gate dielectric. | 07-30-2015 |
20150236114 | SEMICONDUCTOR DEVICE AND FORMATION THEREOF - A semiconductor device and method of formation are provided herein. A semiconductor device includes a barrier including carbon over a fin, the fin including a doped region. The semiconductor device includes an epitaxial (Epi) cap over the barrier, the Epi cap including phosphorus. The barrier inhibits phosphorus diffusion from the Epi cap into the fin as compared to a device that lacks such a barrier. The inhibition of the phosphorus diffusion reduces a short channel effect, thus improving the semiconductor device function. | 08-20-2015 |
20150263159 | FINFET Structure and Method for Fabricating the Same - A device comprises a substrate comprising silicon, a fin structure comprising a lower portion formed of silicon and enclosed by an isolation region, a middle portion formed of silicon-germanium-carbon, wherein the middle portion is enclosed by an oxide layer, an upper portion formed of silicon, wherein the upper portion comprises a channel and a silicon-carbon layer formed between the middle portion and the upper portion, a first source/drain region comprising a first silicon-phosphorus region and a first silicon-carbon layer formed underlying the first silicon-phosphorus region and a second source/drain region comprising a second silicon-phosphorus region and a second silicon-carbon layer formed underlying the second silicon-phosphorus region. | 09-17-2015 |
20150357443 | Semiconductor Liner of Semiconductor Device - The disclosure relates to a fin field effect transistor (FinFET) formed in and on a substrate having a major surface. The FinFET includes a fin structure protruding from the major surface, which fin includes a lower portion, an upper portion, and a middle portion between the lower portion and upper portion, wherein the fin structure includes a first semiconductor material having a first lattice constant; a pair of notches extending into opposite sides of the middle portion; and a semiconductor liner adjoining the lower portion. The semiconductor liner is a second semiconductor material having a second lattice constant greater than the first lattice constant. | 12-10-2015 |
20150372120 | Fin Structure of Semiconductor Device - A fin structure of a semiconductor device, such as a fin field effect transistor (FinFET), and a method of manufacture, is provided. In an embodiment, trenches are formed in a substrate, and a liner is formed along sidewalls of the trenches, wherein a region between adjacent trenches define a fin. A dielectric material is formed in the trenches. Portions of the semiconductor material of the fin are replaced with a second semiconductor material and a third semiconductor material, the second semiconductor material having a different lattice constant than the substrate and the third semiconductor material having a different lattice constant than the second semiconductor material. Portions of the second semiconductor material are oxidized. | 12-24-2015 |
20150380556 | Channel Strain Control for Nonplanar Compound Semiconductor Devices - A circuit device having differently-strained NMOS and PMOS FinFETs is provided. In an exemplary embodiment, a semiconductor device includes a substrate with a first fin structure and a second fin structure formed thereup. The first fin structure includes opposing source/drain regions disposed above a surface of the substrate; a channel region disposed between the opposing source/drain regions and disposed above the surface of the substrate; and a first buried layer disposed between the channel region and the substrate. The first buried layer includes a compound semiconductor oxide. The second fin structure includes a second buried layer disposed between the substrate and a channel region of the second fin structure, such that the second buried layer is different in composition from the first. For example, the second fin structure may be free of the compound semiconductor oxide. | 12-31-2015 |
20160005656 | Fin Spacer Protected Source and Drain Regions in FinFETs - A method includes forming Shallow Trench Isolation (STI) regions in a semiconductor substrate and a semiconductor strip between the STI regions. The method also include replacing a top portion of the semiconductor strip with a first semiconductor layer and a second semiconductor layer over the first semiconductor layer. The first semiconductor layer has a first germanium percentage higher than a second germanium percentage of the second semiconductor layer. The method also includes recessing the STI regions to form semiconductor fins, forming a gate stack over a middle portion of the semiconductor fin, and forming gate spacers on sidewalls of the gate stack. The method further includes forming fin spacers on sidewalls of an end portion of the semiconductor fin, recessing the end portion of the semiconductor fin, and growing an epitaxial region over the end portion of the semiconductor fin. | 01-07-2016 |
20160035827 | Fin Structure of Semiconductor Device - A semiconductor device and method of formation are provided herein. A semiconductor device includes a fin having a first wall extending along a first plane, the fin including a doped region defining a first furrow on a first side of the first plane. A dielectric is disposed within the first furrow, such that the dielectric is in contact with the first furrow between a first end of the dielectric and a second end of the dielectric. The first end is separated a first distance from the first plane. The dielectric disposed within the furrow increases the isolation of a channel portion of adjacent fins, and thus decreases current leakage of a FinFET, as compared to a FinFET including fins that do not include a dielectric disposed within a furrow. | 02-04-2016 |
20160035849 | Strained Channel of Gate-All-Around Transistor - The disclosure relates to a semiconductor device. An exemplary structure for a nanowire structure comprises a first semiconductor material having a first lattice constant and a first linear thermal expansion constant; and a second semiconductor material having a second lattice constant and a second linear thermal expansion constant surrounding the first semiconductor material, wherein a ratio of the first lattice constant to the second lattice constant is from 0.98 to 1.02, wherein a ratio of the first linear thermal expansion constant to the second linear thermal expansion constant is greater than 1.2 or less than 0.8. | 02-04-2016 |
20160043085 | Semiconductor Device And Fabricating The Same - The present disclosure provides a method for fabricating an integrated circuit device. The method includes providing a precursor including a substrate having first and second metal-oxide-semiconductor (MOS) regions. The first and second MOS regions include first and second gate regions, semiconductor layer stacks, and source/drain regions respectively. The method further includes laterally exposing and oxidizing the semiconductor layer stack in the first gate region to form first outer oxide layer and inner nanowire set, and exposing the first inner nanowire set. A first high-k/metal gate (HK/MG) stack wraps around the first inner nanowire set. The method further includes laterally exposing and oxidizing the semiconductor layer stack in the second gate region to form second outer oxide layer and inner nanowire set, and exposing the second inner nanowire set. A second HK/MG stack wraps around the second inner nanowire set. | 02-11-2016 |
20160056157 | Tuning Tensile Strain on FinFET - A fin field effect transistor (FinFET) having a tunable tensile strain and an embodiment method of tuning tensile strain in an integrated circuit are provided. The method includes forming a source/drain region on opposing sides of a gate region in a fin, forming spacers over the fin, the spacers adjacent to the source/drain regions, depositing a dielectric between the spacers; and performing an annealing process to contract the dielectric, the dielectric contraction deforming the spacers, the spacer deformation enlarging the gate region in the fin. | 02-25-2016 |
20160056236 | SILICON AND SILICON GERMANIUM NANOWIRE FORMATION - Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. For example, one or more silicon and silicon germanium stacks are utilized to form PMOS transistors comprising germanium nanowire channels and NMOS transistors comprising silicon nanowire channels. In an example, a first silicon and silicon germanium stack is oxidized to transform silicon to silicon oxide regions, which are removed to form germanium nanowire channels for PMOS transistors. In another example, silicon and germanium layers within a second silicon and silicon germanium stack are removed to form silicon nanowire channels for NMOS transistors. PMOS transistors having germanium nanowire channels and NMOS transistors having silicon nanowire channels are formed as part of a single fabrication process. | 02-25-2016 |
20160079361 | Silicide Region of Gate-All-Around Transistor - The disclosure relates to a semiconductor device. An exemplary structure for a semiconductor device comprises a substrate; a nanowire structure protruding from the substrate comprising a channel region between a source region and a drain region; a pair of silicide regions extending into opposite sides of the source region, wherein each of the pair of silicide regions comprising a vertical portion adjacent to the source region and a horizontal portion adjacent to the substrate; and a metal gate surrounding a portion the channel region. | 03-17-2016 |
20160087054 | Self-Aligned Wrapped-Around Structure - An vertical gate-all-around transistor and method of making is provided. The vertical gate-all-around transistor includes a first semiconductor structure extending above a substrate, and a gate structure extending completely around the first semiconductor structure in a plan view. An outermost perimeter of the gate structure comprises a first protruding arcuate section interposed between linear sections, the first protruding arcuate section aligned with the first semiconductor structure. | 03-24-2016 |
20160087103 | FinFET with Buried Insulator Layer and Method for Forming - A fin structure suitable for a FinFET and having a buried insulator layer is disclosed. In an exemplary embodiment, a semiconductor device comprises a substrate with a first semiconductor material and having a fin structure formed thereupon. The fin structure includes a lower region proximate to the substrate, a second semiconductor material disposed on the lower region, a third semiconductor material disposed on the second semiconductor material, and an insulating material selectively disposed on the second semiconductor material such that the insulating material electrically isolates a channel region of the fin structure and further such that the insulating material exerts a strain on the channel region. The semiconductor device further comprises an isolation feature disposed adjacent to the fin structure. | 03-24-2016 |
20160104776 | High Mobility Devices with Anti-Punch Through Layer and Methods of Forming Same - An embodiment semiconductor device includes a fin extending upwards from a semiconductor substrate. The fin includes an anti-punch through (APT) layer having APT dopants and a channel region over the APT layer. The channel region is substantially free of APT dopants. The semiconductor device further includes a conductive gate stack on a sidewall and a top surface of the channel region. | 04-14-2016 |
Patent application number | Description | Published |
20150053912 | Integrate Circuit With Nanowires - The present disclosure provides an integrated circuit (IC). The IC includes a substrate having a metal-oxide-semiconductor (MOS) region. The IC further includes first gate, source and drain regions, having a first length, and second gate, source and drain regions, having a second length. A first nanowire set is disposed in the first gate region, the first nanowire set including a nanowire having a first diameter and connecting to a feature in the first source region and a feature in the first drain region. A second nanowire set is disposed in the second gate region, the second nanowire set including a nanowire having a second diameter and connecting to a feature in the second source region and a feature in the second drain region. The diameters are such that if the first length is greater than the second length, the first diameter is less than the second diameter, and vice versa. | 02-26-2015 |
20150137067 | NANOWIRE MOSFET WITH DIFFERENT SILICIDES ON SOURCE AND DRAIN - A nanowire field effect transistor (FET) device and method for forming a nanowire FET device are provided. A nanowire FET including a source region and a drain region is formed. The nanowire FET further includes a nanowire that connects the source region and the drain region. A source silicide is formed on the source region, and a drain silicide is formed on the drain region. The source silicide is comprised of a first material that is different from a second material comprising the drain silicide. | 05-21-2015 |
20150214318 | ALIGNED GATE-ALL-AROUND STRUCTURE - A semiconductor device includes a gate disposed over a substrate. The gate has a first gate portion of the gate including a gate dielectric and a gate electrode disposed above a first channel region and a second gate portion including a gate dielectric and a gate electrode disposed between the substrate and the first channel region and aligned with the first gate portion. A source and a drain region are disposed adjacent the gate. A dielectric layer is disposed on the substrate and has a first portion underlying at least some of the source, a second portion underlying at least some of the drain; and a third portion underlying at least some of the first channel, the first gate portion and the second gate portion. | 07-30-2015 |
20150303197 | Semiconductor Device and Fabricating the Same - An integrated circuit (IC) device comprises a substrate having a metal-oxide-semiconductor (MOS) region; a gate region disposed over the substrate and in the MOS region; and source/drain features in the MOS region and separated by the gate region. The gate region includes a fin structure and a nanowire over the fin structure. The nanowire extends from the source feature to the drain feature. | 10-22-2015 |
20150303198 | METHOD AND STRUCTURE FOR FINFET DEVICE - The present disclosure provides a method for fabricating a fin-like field-effect transistor (FinFET). The method includes forming a first fin structures over a substrate, forming a patterned oxidation-hard-mask (OHM) over the substrate to expose the first fin structure in a first gate region of a n-type FET region, forming a semiconductor oxide feature in a middle portion of the first fin structure in the first gate region, forming a second fin structure in a PFET region, forming dummy gates, forming source/drain (S/D) features, replacing the dummy gates by a first high-k/metal gate (HK/MG) in the NFET region and a second HK/MG in the PFET region. | 10-22-2015 |
20150303305 | FinFET Device with High-K Metal Gate Stack - The present disclosure provides a semiconductor device that includes a substrate, a first fin structure over the substrate. The first fin structure includes a first semiconductor material layer, having a semiconductor oxide layer as its outer layer, as a lower portion of the first fin structure. The first semiconductor has a first width. The first fin structure also includes a second semiconductor material layer as an upper portion of the first fin structure. The second semiconductor material layer has a third width, which is substantially smaller than the first width. The semiconductor structure also includes a gate region formed over a portion of the first fin and a high-k (HK)/metal gate (MG) stack on the substrate including wrapping over a portion of the first fin structure in the gate region. | 10-22-2015 |
20150311207 | Structure and Method for FinFET Device - The present disclosure provides an embodiment of a fin-like field-effect transistor (FinFET) device. The device includes a plurality of first fin structures over a substrate. The first fin structure includes a first semiconductor material layer, a second semiconductor material layer disposed over the first semiconductor material layer, being at least partially surrounded by a semiconductor oxide feature. The device also includes a third semiconductor material layer disposed over the second semiconductor material layer and a second fin structures over the substrate and adjacent to one of the first fin structures. The second fin structure includes the first semiconductor material layer and the third semiconductor material layer disposed over the dielectric layer. | 10-29-2015 |
20150311212 | Structure and Method for SRAM FinFET Device - The present disclosure provides an embodiment of a fin-like field-effect transistor (FinFET) device. The device includes a substrate having an n-type FinFET (NFET) region and a p-type FinFET (PFET) region. The device also includes a first and a second fin structures over the substrate in the NFET region and a third fin structure over the substrate in the PFET region. The device also includes a first high-k (HK)/metal gate (MG) stack in the NFET region, including wrapping over a portion of the first fin structure, a first subset of the first source/drain (S/D) features, adjacent to the first HK/MG stack, over the recessed first fin structure and a second subset of the first S/D features partially over the recessed second fin structure and partially over the recessed first fin structure. | 10-29-2015 |
20150311335 | STRUCTURE AND METHOD FOR FINFET DEVICE - The present disclosure provides a fin-like field-effect transistor (FinFET) device. The device includes a substrate having a first region, a second region and a third region. The first region includes a first fin structure, a first high-k (HK)/metal gate (MG) stack wrapping over an upper portion of the first fin structure and a first source/drain features, separated by the first HK/MG stack, over the recessed first fin structure. The second region includes a second fin structure, the first source/drain features over a portion of the recessed second fin structure. The third region includes a dummy gate stack over the second fin structure and the two first regions are separated by the second region, or by the third region. | 10-29-2015 |
20150311336 | Structure and Method for FinFET Device - The present disclosure provides an embodiment of a fin-like field-effect transistor (FinFET) device. The device includes a substrate having a first gate region, a first fin structure over the substrate in the first gate region. The first fin structure includes an upper semiconductor material member, a lower semiconductor material member, surrounded by an oxide feature and a liner wrapping around the oxide feature of the lower semiconductor material member, and extending upwards to wrap around a lower portion of the upper semiconductor material member. The device also includes a dielectric layer laterally proximate to an upper portion of the upper semiconductor material member. Therefore the upper semiconductor material member includes a middle portion that is neither laterally proximate to the dielectric layer nor wrapped by the liner. | 10-29-2015 |
20150332971 | Integrate Circuit with Nanowires - A method includes providing a substrate having a metal-oxide-semiconductor (MOS) region. The MOS region includes first gate, source, and drain regions for a first device, and second gate, source, and drain regions for a second device. The first gate region has a first length. The second gate region has a second length different from the first length. The method further includes forming first and second fins in the first and second gate regions, forming first and second semiconductor layer stacks over the first and second fins, and performing a thermal oxidation process to the first and second semiconductor layer stacks, thereby forming first and second nanowire sets in the first and second gate regions respectively. The first and second nanowire sets are wrapped by respective semiconductor oxide layers. The first nanowire set has a first diameter. The second nanowire set has a second diameter different from the first diameter. | 11-19-2015 |
20150380313 | METHOD OF FORMING SEMICONDUCTOR STRUCTURE WITH HORIZONTAL GATE ALL AROUND STRUCTURE - A method of forming a semiconductor device having a horizontal gate all around structure on a bulk substrate is provided. The method comprises forming a plurality of fins on a bulk substrate wherein each fin comprises a vertical slice of substrate material and a plurality of channel layers above the vertical slice of substrate material. The plurality of channel layers includes a top channel layer above a bottom channel layer. Each channel layer comprises a first sublayer of removable semiconductor material overlaid by a second sublayer of semiconductor material. The method further comprises providing shallow trench isolation (STI) material between the vertical slices of the bulk substrate in the plurality of fins, depositing poly material around a central portion of the plurality of fins, forming source and drain regions, and forming an interlayer dielectric layer (ILD0). The method also comprises removing the poly material, forming a plurality of channels from the channel layers, and forming a gate around the channels. | 12-31-2015 |
20150380410 | Structure and Method for SRAM FinFET Device - The present disclosure provides an embodiment of a fin-like field-effect transistor (FinFET) device. The device includes a first fin structure disposed over an n-type FinFET (NFET) region of a substrate. The first fin structure includes a silicon (Si) layer, a silicon germanium oxide (SiGeO) layer disposed over the silicon layer and a germanium (Ge) feature disposed over the SiGeO layer. The device also includes a second fin structure over the substrate in a p-type FinFET (PFET) region. The second fin structure includes the silicon (Si) layer, a recessed silicon germanium oxide (SiGeO) layer disposed over the silicon layer, an epitaxial silicon germanium (SiGe) layer disposed over the recessed SiGeO layer and the germanium (Ge) feature disposed over the epitaxial SiGe layer. | 12-31-2015 |
20160043225 | Nonplanar Device and Strain-Generating Channel Dielectric - A nonplanar circuit device having a strain-producing structure disposed under the channel region is provided. In an exemplary embodiment, the integrated circuit device includes a substrate with a first fin structure and a second fin structure disposed on the substrate. An isolation feature trench is defined between the first fin structure and the second fin structure. The circuit device also includes a strain feature disposed on a horizontal surface of the substrate within the isolation feature trench. The strain feature may be configured to produce a strain on a channel region of a transistor formed on the first fin structure. The circuit device also includes a fill dielectric disposed on the strain feature within the isolation feature trench. In some such embodiments, the strain feature is further disposed on a vertical surface of the first fin structure and on a vertical surface of the second fin structure. | 02-11-2016 |
20160049338 | STRUCTURE AND METHOD FOR FINFET DEVICE - The present disclosure provides an embodiment of a fin-like field-effect transistor (FinFET) device. The device includes a substrate having a first gate region, a first fin structure over the substrate in the first gate region. The first fin structure includes an upper semiconductor material member, a lower semiconductor material member, surrounded by an oxide feature and a liner wrapping around the oxide feature of the lower semiconductor material member, and extending upwards to wrap around a lower portion of the upper semiconductor material member. The device also includes a dielectric layer laterally proximate to an upper portion of the upper semiconductor material member. Therefore the upper semiconductor material member includes a middle portion that is neither laterally proximate to the dielectric layer nor wrapped by the liner. | 02-18-2016 |
20160087041 | Method and Structure for FinFET Device - The present disclosure describes a fin-like field-effect transistor (FinFET). The device includes one or more fin structures over a substrate, each with source/drain (S/D) features and a high-k/metal gate (HK/MG). A first HK/MG in a first gate region wraps over an upper portion of a first fin structure, the first fin structure including an epitaxial silicon (Si) layer as its upper portion and an epitaxial growth silicon germanium (SiGe), with a silicon germanium oxide (SiGeO) feature at its outer layer, as its middle portion, and the substrate as its bottom portion. A second HK/MG in a second gate region, wraps over an upper portion of a second fin structure, the second fin structure including an epitaxial SiGe layer as its upper portion, an epitaxial Si layer as it upper middle portion, an epitaxial SiGe layer as its lower middle portion, and the substrate as its bottom portion. | 03-24-2016 |
20160093726 | Integrated Circuit Structure with Substrate Isolation and Un-Doped Channel - The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin structure formed on a substrate; a gate stack formed over the fin structure; source/drain regions over the substrate and disposed on opposing sides of the gate stack; a channel region defined in the fin structure and underlying the gate stack, wherein the channel region is un-doped; and a buried isolation layer disposed vertically between the channel region and the substrate, wherein the buried isolation layer includes a compound semiconductor oxide. | 03-31-2016 |
20160104765 | SEMICONDUCTOR DEVICES WITH HORIZONTAL GATE ALL AROUND STRUCTURE AND METHODS OF FORMING THE SAME - A semiconductor device having a horizontal gate all around structure is provided. The semiconductor device includes a substrate and a fin. The fin is disposed on the substrate, and includes an anti-punch through (APT) layer formed of a material at a dose of about 1E18 atoms/cm | 04-14-2016 |
20160104793 | Structure and Method for FinFET Device - The present disclosure provides an embodiment of a fin-like field-effect transistor (FinFET) device. The device includes a fin structure disposed over a substrate. The fin structure includes a semiconductor oxide layer disposed over the substrate, which has a top surface facing away from the substrate, a first semiconductor material layer disposed over and spaced apart from the semiconductor oxide layer, which has a top surface facing away from the substrate and an opposing bottom surface facing the substrate, and a dielectric sidewall spacer disposed along a sidewall of the semiconductor oxide layer and extending to the first semiconductor material layer. The device also includes a gate dielectric layer disposed over the fin structure and a gate electrode layer disposed over the gate dielectric layer. The gate electrode extends between the top surface of the semiconductor oxide layer and the bottom surface of the first semiconductor material layer. | 04-14-2016 |
Patent application number | Description | Published |
20080296701 | ONE-TIME PROGRAMMABLE READ-ONLY MEMORY - A one-time programmable read-only memory (OTP-ROM) including a substrate, a first doped region, a second doped region, a gate dielectric layer, a first gate and a second gate. The substrate is of a first conductive type. The first doped region and the second doped region are of a second conductive type and are separately disposed in the substrate. The gate dielectric layer is disposed on the substrate between the first doped region and the second doped region. The first gate and the second gate are disposed on the gate dielectric layer, respectively. The first gate is adjacent to the first doped region, while the second gate is adjacent to the second doped region. Here, the first gate is electrically coupled grounded, and the OTP-ROM is programmed through a breakdown effect. | 12-04-2008 |
20090283814 | SINGLE-POLY NON-VOLATILE MEMORY CELL - A non-volatile memory cell includes an ion well of a semiconductor substrate; a first half-transistor having a firs select gate, a first diffusion region in the ion well, and a first gate dielectric layer between the first select gate and the ion well; a second half-transistor disposed adjacent to the first half-transistor, wherein the second half-transistor has a second select gate spaced apart from the first select gate, a second diffusion region in the ion well, and a second gate dielectric layer between the second select gate and the ion well. The first and second half-transistors are mirror-symmetrical to each other. | 11-19-2009 |
20100073985 | METHOD FOR OPERATING ONE-TIME PROGRAMMABLE READ-ONLY MEMORY - A method for operating a one-time programmable read-only memory (OTP-ROM) is provided. The OTP-ROM comprises a first gate and a second gate respectively disposed on a gate dielectric layer between a first doped region and a second doped region on a substrate, wherein the first gate is adjacent to the first doped region and coupled to the first doped region, the second gate is adjacent to the second doped region, the first gate is electrically coupled grounded, and the OTP-ROM is programmed through a breakdown effect. The method comprises a step of programming the OTP-ROM under the conditions that a voltage of the second doped region is higher than a voltage of the first doped region, the voltage of the second gate is higher than a threshold voltage to pass the voltage of the second doped region, and the first doped region and the substrate are at a reference voltage. | 03-25-2010 |
20100148238 | NON-VOLATILE MEMORY AND FABRICATING METHOD THEREOF - A non-volatile memory is formed on a substrate. The non-volatile memory includes an isolation structure, a floating gate, and a gate dielectric layer. The isolation structure is disposed in the substrate to define an active area. The floating gate is disposed on the substrate and crosses over the active area. The gate dielectric layer is disposed between the floating gate and the substrate. The floating gate includes a first region and a second region. An energy band of the second region is lower than an energy band of the first region, so that charges stored in the floating gate are away from an overlap region of the floating gate and the gate dielectric layer. | 06-17-2010 |
20100265755 | ONE TIME PROGRAMMABLE READ ONLY MEMORY AND PROGRAMMING METHOD THEREOF - A one time programmable read only memory disposed on a substrate of a first conductive type is provided. A gate structure is disposed on the substrate. A first doped region and a second doped region are disposed in the substrate at respective sides of the gate structure, and the first doped region and the second doped region are of a second conductive type which is different from the first conductive type. A third doped region of the first conductive type is disposed in the substrate and is adjacent to the second doped region, and a junction is formed between the third doped region and the second doped region. A metal silicide layer is disposed on the substrate. An clearance is formed in the metal silicide layer, and the clearance at least exposes the junction. | 10-21-2010 |
20110242893 | NON-VOLATILE MEMORY UNIT CELL WITH IMPROVED SENSING MARGIN AND RELIABILITY - A non-volatile memory unit cell includes a first transistor pair and first and second control gates. The first transistor pair includes first and second transistors that are connected in series and of the same type. The first and second transistors have a first floating polysilicon gate and a second floating polysilicon gate, respectively. The first control gate is coupled to the first floating polysilicon gate through a tunneling junction and the second control gate is coupled to the second floating polysilicon gate through another tunneling junction. | 10-06-2011 |
20110299336 | SINGLE-POLYSILICON LAYER NON-VOLATILE MEMORY AND OPERATING METHOD THEREOF - A single-polysilicon layer non-volatile memory having a floating gate transistor, a program gate and a control gate is provided. The floating gate transistor has a floating gate and a tunneling dielectric layer. The floating gate is disposed on a substrate. The tunneling dielectric layer is disposed between the floating gate and the substrate. The program gate, the control gate and the erase gate are respectively disposed in the substrate under the floating gate separated by the tunneling dielectric layer. Therefore, during a program operation and an erase operation, charges are injected in and expelled out through different regions of the tunneling dielectric layer, so as to increase reliability of the non-volatile memory. | 12-08-2011 |
20110310669 | Logic-Based Multiple Time Programming Memory Cell - A non-volatile memory system includes one or more non-volatile memory cells. Each non-volatile memory cell comprises a floating gate, a coupling device, a first floating gate transistor, and a second floating gate transistor. The coupling device is located in a first conductivity region. The first floating gate transistor is located in a second conductivity region, and supplies read current sensed during a read operation. The second floating gate transistor is located in a third conductivity region. Such non-volatile memory cell further comprises two transistors for injecting negative charge into the floating gate during a programming operation, and removing negative charge from the second floating gate transistor during an erase operation. The floating gate is shared by the first floating gate transistor, the coupling device, and the second floating gate transistor, and extends over active regions of the first floating gate transistor, the coupling device and the second floating gate transistor. | 12-22-2011 |
20120236635 | Logic-Based Multiple Time Programming Memory Cell - A non-volatile memory system includes one or more non-volatile memory cells. Each non-volatile memory cell comprises a floating gate, a coupling device, a first floating gate transistor, and a second floating gate transistor. The coupling device is located in a first conductivity region. The first floating gate transistor is located in a second conductivity region, and supplies read current sensed during a read operation. The second floating gate transistor is located in a third conductivity region. Such non-volatile memory cell further comprises two transistors for injecting negative charge into the floating gate during a programming operation, and removing negative charge from the second floating gate transistor during an erase operation. The floating gate is shared by the first floating gate transistor, the coupling device, and the second floating gate transistor, and extends over active regions of the first floating gate transistor, the coupling device and the second floating gate transistor. | 09-20-2012 |
20120236646 | NON-VOLATILE MEMORY CELL - The non-volatile memory cell includes a coupling device and a first select transistor. The coupling device is formed in a first conductivity region. The first select transistor is serially connected to a first floating gate transistor and a second select transistor, all formed in a second conductivity region. An electrode of the coupling device and a gate of the first floating gate transistor are a monolithically formed floating gate; wherein the first conductivity region and the second conductivity region are formed in a third conductivity region; wherein the first conductivity region, the second conductivity region, and the third conductivity region are wells. | 09-20-2012 |
20120273860 | NON-VOLATILE MEMORY UNIT CELL WITH IMPROVED SENSING MARGIN AND RELIABILITY - An only-one-polysilicon layer non-volatile memory unit cell includes a first P-type transistor, a second P-type transistor, a N-type transistor pair, a first and second coupling capacitors is provided. The N-type transistor pair has a third transistor and a fourth transistor that are connected. The third transistor and the fourth transistor have a first floating polysilicon gate and a second floating polysilicon gate to serve as charge storage mediums, respectively. One end of the second coupling capacitor is connected to the gate of the second transistor and is coupled to the second floating polysilicon gate, the other end of the second coupling capacitor receives a second control voltage. One end of the second coupling capacitor is connected to the gate of the second transistor and is coupled to the second floating polysilicon gate, the other end of the second coupling capacitor receives a second control voltage. | 11-01-2012 |
20130119453 | NON-VOLATILE MEMORY UNIT CELL WITH IMPROVED SENSING MARGIN AND RELIABILITY - A non-volatile memory unit cell includes a transistor pair, and first, second, third and fourth control gates. The transistor pair has a first transistor and a second transistor that are connected in parallel and of opposite types. The first transistor and the second transistor have a first floating polysilicon gate and a second floating polysilicon gate, respectively, wherein the first floating polysilicon gate and the second floating polysilicon gate are electrically or physically isolated. The first control gate is capacitively coupled to the first floating polysilicon gate through a first coupling junction. The second control gate is capacitively coupled to the second floating polysilicon gates through a second coupling junction. The third control gate is capacitively coupled to the first floating polysilicon gate through a first tunneling junction. The fourth control gate is capacitively coupled to the second floating polysilicon gates through a second tunneling junction. | 05-16-2013 |
20130176793 | FLASH MEMORY APPARATUS - A flash memory apparatus is provided. The flash memory apparatus includes a plurality of memory cells and a plurality of programming voltage control generators. Each of the memory cells receives a programming control voltage through a control end thereof, and executes data programming operation according to the programming control voltages. Each of the programming voltage control generators includes a pre-charge voltage transmitter and a pumping capacitor. The pre-charge voltage transmitter provides pre-charge voltage to the end of each of the corresponding memory cells according to pre-charge enable signal during a first period. A pumping voltage is provided to the pumping capacitor during a second period, and the programming control voltage is generated at the control end of each of the memory cells. | 07-11-2013 |
20130234228 | ERASABLE PROGRAMMABLE SINGLE-PLOY NONVOLATILE MEMORY - An erasable programmable single-poly nonvolatile memory includes a floating gate transistor having a floating gate, a gate oxide layer under the floating gate, and a channel region; and an erase gate region, wherein the floating gate is extended to and is adjacent to the erase gate region. The gate oxide layer comprises a first portion above the channel region of the floating gate transistor and a second portion above the erase gate region, and a thickness of the first portion of the gate oxide layer is different from a thickness of the second portion of the gate oxide layer. | 09-12-2013 |
20130237048 | METHOD OF FABRICATING ERASABLE PROGRAMMABLE SINGLE-PLOY NONVOLATILE MEMORY - The present invention provides method of fabricating an erasable programmable single-poly nonvolatile memory, comprising steps of: defining a first area and a second area in a first type substrate; forming a second type well region in the first area; forming a first gate oxide layer and a second gate oxide layer covered on a surface of the first area, wherein the second gate oxide layer is extended to and is adjacent to the second area; forming a DDD region in the second area; etching a portion of the second gate oxide layer above the second area; forming two polysilicon gates covered on the first and the second gate oxide layers; and defining a second type doped region in the DDD region and a first type doped regions in the second type well region. | 09-12-2013 |
20130302977 | METHOD OF FABRICATING ERASABLE PROGRAMMABLE SINGLE-PLOY NONVOLATILE MEMORY - The present invention provides method of fabricating an erasable programmable single-poly nonvolatile memory, comprising steps of: defining a first area and a second area in a first type substrate; forming a second type well region in the first area; forming a first gate oxide layer and a second gate oxide layer covered on a surface of the first area, wherein the second gate oxide layer is extended to and is adjacent to the second area; forming a DDD region in the second area; etching a portion of the second gate oxide layer above the second area; forming two polysilicon gates covered on the first and the second gate oxide layers; and defining a second type doped region in the DDD region and a first type doped regions in the second type well region. | 11-14-2013 |
20140160859 | FLASH MEMORY APPARATUS - A flash memory apparatus is provided. The flash memory apparatus includes a plurality of memory cell regions. Each of the memory cell regions includes a plurality of memory cells, a programming voltage control generator and an erase voltage control generator. The memory cells receives a programming control voltage through a control end point for programming operation, and the memory cells receives an erase control voltage through an erase end point for erasing operation. The programming voltage control generator provides the programming control voltage to the memory cells, and the erase voltage control generator provides the erase control voltage to the memory cells. | 06-12-2014 |
20140177338 | NON-VOLATILE MEMORY CELL - A non-volatile memory cell comprises a coupling device, a first and a second select transistor, and a first and a second floating gate transistor is disclosed. The coupling device is formed in a first conductivity region. The first select transistor is serially connected to the first floating gate transistor and the second select transistor. Moreover, the first select transistor, the first floating gate transistor, and the second select transistor are formed in a second conductivity region. The second floating gate transistor is formed in a third conductivity region, wherein the first conductivity region, the second conductivity region, and the third conductivity region are formed in a fourth conductivity region. The first conductivity region, the second conductivity region, and the third conductivity region are wells, and the fourth conductivity region is a deep well. The third conductivity region surrounds the first conductivity region and the second conductivity region. | 06-26-2014 |
20150092498 | Non-volatile memory for high rewrite cycles application - A non-volatile memory has an array of non-volatile memory cells. Each of the non-volatile memory cells includes a coupling device formed on a first well, a read device, a floating gate device formed on a second well and coupled to the coupling device, a program device formed on the second well, and an erase device formed on a third well and coupled to the first floating gate device. The read device, the program device, and the erase device are formed on separate wells so as to separate the cycling counts of a read operation, a program operation and an erase operation of the non-volatile memory cell. | 04-02-2015 |
20160035421 | Non-volatile memory for high rewrite cycles application - A non-volatile memory has an array of non-volatile memory cells. Each of the non-volatile memory cells includes a coupling device formed on a first well, a read device, a floating gate device formed on a second well and coupled to the coupling device, a program device formed on the second well, and an erase device formed on a third well and coupled to the first floating gate device. The read device, the program device, and the erase device are formed on separate wells so as to separate the cycling counts of a read operation, a program operation and an erase operation of the non-volatile memory cell. | 02-04-2016 |
20160104537 | MEMORY ARRAY WITH MEMORY CELLS ARRANGED IN PAGES - A memory array includes a first memory page and a second memory page. The first memory page includes a first word line, a first select gate line, a first control line, a first erase line, and a plurality of first memory cells each coupled to the first word line, the first select gate line, the first control line, and the first erase line, and for receiving a bit line signal and a source line signal. The second memory page includes a second control line, a second erase line, and a plurality of second memory cells each coupled to the first word line, the first select gate line, the second control line, and the second erase line, and for receiving a bit line signal and a source line signal. | 04-14-2016 |